Document Outline

1 FEATURES
2 GENERAL DESCRIPTION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION
- 7.1 Decoder part
  - 7.1.1 PRINCIPLE OPERATIONAL MODES OF THE DECODER
  - 7.1.2 CRYSTAL FREQUENCY SELECTION
  - 7.1.3 STANDBY MODES
- 7.2 Crystal oscillator
- 7.3 Data slicer and clock regenerator
- 7.4 Demodulator
  - 7.4.1 FRAME SYNC PROTECTION
  - 7.4.2 EFM DEMODULATION
- 7.5 Subcode data processing
  - 7.5.1 Q-CHANNEL PROCESSING
  - 7.5.2 EIAJ 3 AND 4-WIRE SUBCODE (CD GRAPHICS) INTERFACES
  - 7.5.3 V4 SUBCODE INTERFACE
- 7.6 FIFO and error corrector
  - 7.6.1 FLAGS OUTPUT (CFLG)
  - 7.6.2 C2FAIL
- 7.7 Audio functions
  - 7.7.1 DE-EMPHASIS AND PHASE LINEARITY
  - 7.7.2 DIGITAL OVERSAMPLING FILTER
  - 7.7.3 CONCEALMENT
  - 7.7.4 MUTE, FULL SCALE, ATTENUATION AND FADE
  - 7.7.5 PEAK DETECTOR
- 7.8 DAC interface
- 7.9 EBU interface
  - 7.9.1 FORMAT
- 7.10 KILL circuit
- 7.11 The VIA interface
- 7.12 Spindle motor control
  - 7.12.1 MOTOR OUTPUT MODES
  - 7.12.2 SPINDLE MOTOR OPERATING MODES
  - 7.12.3 LOOP CHARACTERISTICS
  - 7.12.4 FIFO OVERFLOW
- 7.13 Servo part
  - 7.13.1 DIODE SIGNAL PROCESSING
  - 7.13.2 SIGNAL CONDITIONING
  - 7.13.3 FOCUS SERVO SYSTEM
  - 7.13.4 RADIAL SERVO SYSTEM
  - 7.13.5 OFF-TRACK COUNTING
  - 7.13.6 DEFECT DETECTION
  - 7.13.7 OFF-TRACK DETECTION
  - 7.13.8 HIGH-LEVEL FEATURES
  - 7.13.9 DRIVER INTERFACE
  - 7.13.10 LASER INTERFACE
  - 7.13.11 RADIAL SHOCK DETECTOR
- 7.14 Microcontroller interface
  - 7.14.1 MICROCONTROLLER INTERFACE (4-WIRE BUS MODE)
  - 7.14.2 MICROCONTROLLER INTERFACE (I 2 C-BUS MODE)
  - 7.14.3 SUMMARY OF FUNCTIONS CONTROLLED BY REGISTERS 0 TO F
  - 7.14.4 SUMMARY OF SERVO COMMANDS
  - 7.14.5 SUMMARY OF SERVO COMMAND PARAMETERS
8 LIMITING VALUES
9 OPERATING CHARACTERISTICS
10 OPERATING CHARACTERISTICS (SUBCODE INTERFACE TIMING)
11 OPERATING CHARACTERISTICS (I 2 S-BUS TIMING)
12 OPERATING CHARACTERISTICS (MICROCONTROLLER INTERFACE TIMING)
13 APPLICATION INFORMATION
14 PACKAGE OUTLINE
- SOT393-1
15 SOLDERING
- 15.1 Introduction
- 15.2 Reflow soldering
- 15.3 Wave soldering
- 15.4 Repairing soldered joints
16 DEFINITIONS
17 LIFE SUPPORT APPLICATIONS
18 PURCHASE OF PHILIPS I 2 C COMPONENTS

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

CONTENTS

FEATURES

GENERAL DESCRIPTION

QUICK REFERENCE DATA

ORDERING INFORMATION

BLOCK DIAGRAM

PINNING

FUNCTIONAL DESCRIPTION

7.1

Decoder part

7.1.1

Principle operational modes of the decoder

7.1.2

Crystal frequency selection

7.1.3

Standby modes

7.2

Crystal oscillator

7.3

Data slicer and clock regenerator

7.4

Demodulator

7.4.1

Frame sync protection

7.4.2

EFM demodulation

7.5

Subcode data processing

7.5.1

Q-channel processing

7.5.2

EIAJ 3 and 4-wire subcode (CD graphics)
interfaces

7.5.3

V4 subcode interface

7.6

FIFO and error corrector

7.6.1

Flags output (CFLG)

7.6.2

C2FAIL

7.7

Audio functions

7.7.1

De-emphasis and phase linearity

7.7.2

Digital oversampling filter

7.7.3

Concealment

7.7.4

Mute, full scale, attenuation and fade

7.7.5

Peak detector

7.8

DAC interface

7.9

EBU interface

7.9.1

Format

7.10

KILL circuit

7.11

The VIA interface

7.12

Spindle motor control

7.12.1

Motor output modes

7.12.2

Spindle motor operating modes

7.12.3

Loop characteristics

7.12.4

FIFO overflow

7.13

Servo part

7.13.1

Diode signal processing

7.13.2

Signal conditioning

7.13.3

Focus servo system

7.13.4

Radial servo system

7.13.5

Off-track counting

7.13.6

Defect detection

7.13.7

Off-track detection

7.13.8

high-level features

7.13.9

Driver interface

7.13.10

Laser interface

7.13.11

Radial shock detector

7.14

Microcontroller interface

7.14.1

Microprocessor interface (4-wire bus mode)

7.14.2

Microcontroller interface (I

C-bus mode)

7.14.3

Summary of functions controlled by registers
0 to F

7.14.4

Summary of servo commands

7.14.5

Summary of servo command parameters

LIMITING VALUES

OPERATING CHARACTERISTICS

OPERATING CHARACTERISTICS
(SUBCODE INTERFACE TIMING)

OPERATING CHARACTERISTICS (I

S-BUS

TIMING)

OPERATING CHARACTERISTICS
(MICROCONTROLLER INTERFACE TIMING)

APPLICATION INFORMATION

PACKAGE OUTLINE

SOLDERING

15.1

Introduction

15.2

Reflow soldering

15.3

Wave soldering

15.4

Repairing soldered joints

DEFINITIONS

LIFE SUPPORT APPLICATIONS

PURCHASE OF PHILIPS I

C COMPONENTS

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

FEATURES

�

Single-speed mode

�

Full error correction strategy, t = 2 and e = 4

�

Full CD graphics interface

�

All standard decoder functions implemented digitally on
chip

�

FIFO overflow concealment for rotational shock
resistance

�

Digital audio interface (EBU), audio only

�

2 and 4 times oversampling integrated digital filter,
including f

mode

�

Audio data peak level detection

�

Kill interface for DAC deactivation during digital silence

�

All TDA1301 (DSIC2) digital servo functions, plus extra
high-level functions

�

Low focus noise

�

Improved playability on ABEX TCD-721R, TCD-725 and
TCD-714 discs

�

Automatic closed loop gain control available for focus
and radial loops

�

Pulsed sledge support

�

Microcontroller loading LOW

�

High-level servo control option

�

High-level mechanism monitor

�

Communication may be via TDA1301/SAA7345
compatible bus or I

C-bus

�

On-chip clock multiplier allows the use of 8.4672 MHz
crystal.

GENERAL DESCRIPTION

The SAA7377 is a single chip combining the functions of a
CD decoder IC and digital servo IC. The decoder part is
based on the SAA7345 (CD6) with an improved error
correction strategy. The servo part is based on the
TDA1301T (DSIC2) with improvements incorporated,
extra features have also been added.

Supply of this Compact Disc IC does not convey an implied
license under any patent right to use this IC in any
Compact Disc application.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

supply voltage

3.4

5.0

5.5

supply current

xtal

crystal frequency

8.4672

MHz

amb

operating ambient temperature

+85

�

stg

storage temperature

+125

�

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

SAA7377GP

QFP64

plastic quad flat package; 64 leads (lead length 1.6 mm);
body 14

�

2.7 mm

SOT393-1

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

DECODER

MICRO-

CONTROLLER

INTERFACE

VERSATILE PINS

INTERFACE

SUBCODE

PROCESSOR

KILL

PEAK

DETECT

SERIAL DATA

INTERFACE

TIMING

TEST

ADC

Vref

GENERATOR

FRONT END

DIGITAL

PLL

MOTOR

CONTROL

AUDIO

PROCESSOR

EBU

INTERFACE

ERROR

CORRECTOR

MICROCONTROLLER

INTERFACE

PRE-

PROCESSING

CONTROL

FUNCTION

CONTROL

PART

EFM

DEMODULATOR

SRAM

RAM

ADDRESSER

OUTPUT
STAGES

FLAGS

VRL

VRH

Iref

SCL

SDA

RAB

SILD

HFIN

HFREF

ISLICE

TEST1

TEST2

TEST3

SELPLL

CRIN

CROUT

CL16

CL11

CL4

SBSY

SFSY

SUB

RCK

STATUS

RESET

D4 IrefT VSSA1

VSSA3

VDDA2

VSSD2

VSSD4

VDDD2(P)

VSSA2

VDDA1

VSSD1

VSSD3 VDDD1(P) VDDD3(C)

KILL

TEST4

DATA

WCLK

SCLK

DOBM

C2FAIL

MOTO2

MOTO1

LDON

CFLG

SAA7377

MGR291

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

PINNING

SYMBOL

PIN

DESCRIPTION

SSA1

(1)

analog ground 1

DDA1

(1)

analog supply voltage 1

unipolar current input (central diode signal input)

reference voltage input for ADC

unipolar current input (central diode signal input)

unipolar current input (satellite diode signal input)

refT

current reference output for ADC calibration

reference voltage output from ADC

SSA2

(1)

analog ground 2

SELPLL

selects whether internal clock multiplier PLL is used

ISLICE

current feedback output from data slicer

HFIN

comparator signal input

SSA3

(1)

analog ground 3

HFREF

comparator common mode input

ref

reference current output pin (nominally 0.5V

)

DDA2

(1)

analog supply voltage 2

TEST1

test control input 1; this pin should be tied LOW

CRIN

crystal/resonator input

CROUT

crystal/resonator output

TEST2

test control input 2; this pin should be tied LOW

CL16

16.9344 MHz system clock output

CL11

11.2896 or 5.6448 MHz clock output (3-state)

radial actuator output

focus actuator output

sledge control output

TEST3

test control input 3; this pin should be tied LOW

DDD1(P)

(1)

digital supply voltage 1 for periphery

DOBM

bi-phase mark output (externally buffered; 3-state)

SSD1

(1)

digital ground 1

MOTO1

motor output 1; versatile (3-state)

MOTO2

motor output 2; versatile (3-state)

SBSY

subcode block sync output (3-state)

SFSY

subcode frame sync output (3-state)

RCK

subcode clock input

SUB

P-to-W subcode output bits (3-state)

SSD2

(1)

digital ground 2

versatile output pin 5

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

Note

1. All supply pins must be connected to the same external power supply voltage.

versatile output pin 4

versatile output pin 3 (open-drain)

KILL

kill output (programmable; open-drain)

TEST4

test output pin; this pin should be left unconnected

DATA

serial data output (3-state)

WCLK

word clock output (3-state)

DDD2(P)

(1)

digital supply voltage 2 for periphery

SCLK

serial bit clock output (3-state)

SSD3

(1)

digital ground 3

CL4

4.2336 MHz microcontroller clock output

SDA

microcontroller interface data I/O line (open-drain output)

SCL

microcontroller interface clock line input

RAB

microcontroller interface R/W and load control line input (4-wire bus mode)

SILD

microcontroller interface R/W and load control line input (4-wire-bus mode)

n.c.

not connected

SSD4

(1)

digital ground 4

RESET

power-on reset input (active LOW)

STATUS

servo interrupt request line/decoder status register output (open-drain)

DDD3(C)

(1)

digital supply voltage 3 for core

C2FAIL

indication of correction failure output (open-drain)

CFLG

correction flag output (open-drain)

versatile input pin 1

versatile input pin 2

LDON

laser drive on output (open-drain)

SYMBOL

PIN

DESCRIPTION

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

FUNCTIONAL DESCRIPTION

7.1

Decoder part

7.1.1

RINCIPLE OPERATIONAL MODES OF THE DECODER

The decoding part operates at single-speed and supports
a full audio specification.

A simplified data flow through the decoder part is
illustrated in Fig.6.

7.1.2

RYSTAL FREQUENCY SELECTION

The SAA7377, which has an internal phase-locked loop
clock multiplier, can be used with 33.8688, 16.9344 or
8.4672 MHz crystal frequencies by setting register B and
SELPLL as shown in Table 1. The internal clock multiplier,
controlled by SELPLL, should only be used if a
8.4672 MHz crystal, ceramic resonator or external clock is
present. It should be noted that the CL11 output is a
5.6448 MHz clock if a 16.9344 MHz external clock is used.

Table 1

Crystal frequency selection

7.1.3

TANDBY MODES

The SAA7377 may be placed in two standby modes
selected by register B (it should be noted that the device
core is still active)

Standby 1: "CD-STOP" mode. Most I/O functions are
switched off.

Standby 2: "CD-PAUSE" mode. Audio output features
are switched off, but the motor loop, the motor output
and the subcode interfaces remain active. This is also
called a "Hot Pause".

In the standby modes the various pins will have the
following values;

MOTO1 and MOTO2: put in high-impedance, PWM
mode (standby 1 and RESET, operating in standby 2).
Put in high-impedance, PDM mode (standby 1 and
RESET, operating in standby 2).

SCL, SDA, SILD and RAB: no interaction. Normal
operation continues.

SCLK, WCLK, DATA, CL11 and DOBM: 3-state in both
standby modes. Normal operation continues after reset.

REGISTER B

SELPLL

CRYSTAL FREQUENCY

(MHz)

00xx

33.8688

00xx

8.4672

01xx

16.9344

CRIN, CROUT, CL16 and CL4: no interaction. Normal
operation continues.

V1, V2, V3, V4, V5, CFLG and C2FAIL: no interaction.
Normal operation continues.

7.2

Crystal oscillator

The crystal oscillator is a conventional 2 pin design
operating between 8 and 35 MHz. This oscillator is
capable of operating with ceramic resonators and also with
both fundamental and third overtone crystals. External
components should be used to suppress the fundamental
output of the third overtone crystals as shown in Figs 3
and 4. Typical oscillation frequencies required are 8.4672,
16.9344 or 33.8688 MHz depending on the internal clock
settings used and whether or not the clock multiplier is
enabled.

Fig.3 8.4672 MHz fundamental configuration.

8.4672 MHz

CRIN

CROUT

SAA7377

22 pF

330

100 k

OSCILLATOR

MGR293

Fig.4 33.8688 MHz overtone configuration.

OSCILLATOR

33.8688 MHz

CRIN

CROUT

SAA7377

3.3

�

1 nF

10 pF

330

100 k

MGR294

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

7.3

Data slicer and clock regenerator

The SAA7377 has an integrated slice level comparator
which can be clocked by the crystal frequency clock, or
8 times the crystal frequency clock (if SELPLL is set HIGH
while using an 8.4672 MHz crystal, and register 4 is set
to 0xxx). The slice level is controlled by an internal current
source applied to an external capacitor under the control
of the Digital Phase-Locked Loop (DPLL).

Regeneration of the bit clock is achieved with an internal
fully digital PLL. No external components are required and
the bit clock is not output. The PLL has two registers
(8 and 9) for selecting bandwidth and equalization.

For certain applications an off-track input is necessary.
This is internally connected from the servo part (its polarity
can be changed by the foc_parm1 parameter), but may be
input via the V1 pin if selected by register C. If this flag is
HIGH, the SAA7377 will assume that its servo part is
following on the wrong track and will flag all incoming HF
data as incorrect.

7.4

Demodulator

7.4.1

RAME SYNC PROTECTION

A double timing system is used to protect the demodulator
from erroneous sync patterns in the serial data.

The master counter is only reset if:

�

A sync coincidence detected; sync pattern occurs
588

�

1 EFM clocks after the previous sync pattern

�

A new sync pattern is detected within

�

6 EFM clocks of

its expected position.

The sync coincidence signal is also used to generate the
PLL lock signal, which is active HIGH after 1 sync
coincidence found, and reset LOW if, during 61
consecutive frames, no sync coincidence is found. The
PLL lock signal can be accessed via the SDA or STATUS
pins selected by register 2 and 7.

Also incorporated in the demodulator is a Run Length 2
(RL2) correction circuit. Every symbol detected as RL2 will
be pushed back to RL3. To do this, the phase error of both
edges of the RL2 symbol are compared and the correction
is executed at the side with the highest error probability.

7.4.2

EFM

DEMODULATION

The 14-bit EFM data and subcode words are decoded into
8-bit symbols.

Fig.5 Data slicer showing typical application components.

47 pF

22 nF

2.2 k

HFIN

HFREF

Iref

ISLICE

22 k

100 nF

2.2 nF

input

crystal

clock

DPLL

1/2VDD

VSSA

VSS

VSSA

MGA368 - 1

100

�

100

�

1998

Jul

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc

decoder (CD7)

SAA7377

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handbook, full pagewidth

SUBCODE

PROCESSOR

DIGITAL PLL AND

DEMODULATOR

FIFO

ERROR

CORRECTOR

FADE/MUTE/

INTERPOLATE

DIGITAL

FILTER

PHASE

COMPENSATION

DE-EMPHASIS

FILTER

KILL

S-BUS

INTERFACE

SCLK
WCLK
DATA

reg 3

reg C

reg 3

reg F

reg A

0 : reg D

xx01

V4 SUBCODE

INTERFACE

MICROCONTROLLER

INTERFACE

CD GRAPHICS

INTERFACE

EBU

INTERFACE

SBSY
SFSY
SUB

DOBM

SDA

output from

data slicer

1 : reg 3 = xx10

(1fs mode)

0 : reg 3

xx10

1 : no pre-emphasis detected
OR reg D

01xx (de-emphasis signal at V5)

0 : pre-emphasis detected
AND reg D

01xx

KILL
V3

MGD039

Fig.6 Simplified data flow of decoder functions.

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

7.5

Subcode data processing

7.5.1

Q-

CHANNEL PROCESSING

The 96-bit Q-channel word is accumulated in an internal
buffer. The last 16 bits are used internally to perform a
Cyclic Redundancy Check (CRC). If the data is good, the
SUBQREADY-I signal will go LOW. SUBQREADY-I can
be read via the SDA or STATUS pins, selected via
register 2. Good Q-channel data may be read from SDA.

7.5.2

EIAJ 3

AND

WIRE SUBCODE

(CD

GRAPHICS

)

INTERFACES

Data from all the subcode channels (P-to-W) may be read
via the subcode interface, which conforms to
EIAJ CP-2401. The interface is enabled and configured as
either a 3-wire or 4-wire interface via register F. The
subcode interface output formats are illustrated in Fig.7,
where the RCK signal is supplied by another device such
as a CD graphics decoder.

7.5.3

SUBCODE INTERFACE

Data of subcode channels, Q-to-W, may be read via pin V4
if selected via register D. The format is similar to RS232
and is illustrated in Fig.8. The subcode sync word is
formed by a pause of 200

�

s minimum. Each subcode byte

starts with a logic 1 followed by 7 bits (Q-to-W). The gap
between bytes is variable between 11.3

�

s and 90

�

The subcode data is also available in the EBU output
(DOBM) in a similar format.

Fig.7 EIAJ subcode (CD graphics) interface format.

handbook, full pagewidth

SBSY

SFSY

RCK

SUB

SFSY

RCK

SUB

SFSY

RCK

SUB

EIAJ 4-wire subcode interface

EIAJ 3-wire subcode interface

SF0

SF1

SF2

SF3

SF97

SF0

SF1

P-W

MBG410

SF0

SF1

SF2

SF3

SF97

SF0

SF1

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

Fig.8 Subcode format and timing on pin V4.

W96

200

�

min

11.3

�

11.3

�

s min

�

s max

MGD038

7.6

FIFO and error corrector

The SAA7377 has a

�

8 frame FIFO. The error corrector is

a t = 2, e = 4 type, with error corrections on both C1
(32 symbol) and C2 (28 symbol) frames. Four symbols are
used from each frame as parity symbols. This error
corrector can correct up to two errors on the C1 level and
up to four errors on the C2 level.

The error corrector also contains a flag processor. Flags
are assigned to symbols when the error corrector cannot
ascertain if the symbols are definitely good. C1 generates
output flags which are read after (de-interleaving) by C2,
to help in the generation of C2 output flags.

The C2 output flags are used by the interpolator for
concealment of uncorrectable errors. They are also output
via the EBU signal (DOBM).

7.6.1

LAGS OUTPUT

(CFLG)

The flags output pin CFLG (open-drain) shows the status
of the error corrector and interpolator and is updated every
frame (7.35 kHz). In the SAA7377 chip a 1-bit flag is
present on the CFLG pin as illustrated in Fig.9. This signal
shows the status of the error corrector and interpolator.

The first flag bit, F1, is the absolute time sync signal, the
FIFO-passed subcode sync and relates the position of the
subcode sync to the audio data (DAC output). This flag
may also be used in a super FIFO or in the synchronization
of different players. The output flags can be made
available at bit 4 of the EBU data format (LSB of the 24-bit
data word), if selected by register A.

Fig.9 Flag output timing diagram.

handbook, full pagewidth

11.3

�

33.9

�

33.9

�

MGD037

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

Table 2

Output flags

DESCRIPTION

no absolute time sync

absolute time sync

C1 frame contained no errors

C1 frame contained 1 error

C1 frame contained 2 errors

C1 frame uncorrectable

C2 frame contained no errors

C2 frame contained 1 error

C2 frame contained 2 errors

C2 frame contained 3 errors

C2 frame contained 4 errors

C2 frame uncorrectable

no interpolations

at least one 1 sample interpolation

at least one hold and no interpolations

at least one hold and one 1 sample interpolation

7.6.2

C2FAIL

The C2FAIL pin indicates that invalid data has occurred on
the I

S-bus interface. However, due to the structure of the

corrector it is impossible to determine which byte has
failed. C2FAIL will go LOW for 140

�

s when invalid data is

detected, this data may then occur 15 ms before or after
the pin is activated.

7.7

Audio functions

7.7.1

EMPHASIS AND PHASE LINEARITY

When pre-emphasis is detected in the Q-channel
subcode, the digital filter automatically includes a
de-emphasis filter section. When de-emphasis is not
required, a phase compensation filter section controls the
phase of the digital oversampling filter to

�

within the

band 0 to 16 kHz. With de-emphasis the filter is not phase
linear.

If the de-emphasis signal is set to be available at V5,
selected via register D, then the de-emphasis filter is
bypassed.

7.7.2

IGITAL OVERSAMPLING FILTER

The SAA7377 contains a 2 to 4 times oversampling IIR
filter. The filter specification of the 4 times oversampling
filter is given in Table 3.

These attenuations do not include the sample-and-hold at
the external DAC output or the DAC post filter. When using
the oversampling filter, the output level is scaled

0.5 dB

down, to avoid overflow on full-scale sine wave inputs
(0 to 20 kHz).

Table 3

Filter specification

PASS BAND

STOP BAND

ATTENUATION

0 to 9 kHz

0.001 dB

19 to 20 kHz

0.03 dB

24 kHz

25 dB

24 to 27 kHz

38 dB

27 to 35 kHz

40 dB

35 to 64 kHz

50 dB

64 to 68 kHz

31 dB

68 kHz

35 dB

69 to 88 kHz

40 dB

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

7.7.3

ONCEALMENT

A 1-sample linear interpolator becomes active if a single
sample is flagged as erroneous but cannot be corrected.
The erroneous sample is replaced by a level midway
between the preceding and following samples. Left and
right channels have independent interpolators. If more
than one consecutive non-correctable sample is found, the
last good sample is held. A 1-sample linear interpolation is
then performed before the next good sample (see Fig.10).

7.7.4

UTE

FULL SCALE

ATTENUATION AND FADE

A digital level controller is present on the SAA7377 which
performs the functions of soft mute, full scale, attenuation
and fade; these are selected via register 0:

Mute: signal reduced to 0 in a maximum of 128 steps;
3 ms.

Attenuate: signal scaled by

12 dB.

Full scale: ramp signal back to 0 dB level. From mute
takes 3 ms.

Fade: activates a 128 stage counter which allows the
signal to be scaled up/down by 0.07 dB steps

128 = full scale.

120 =

0.5 dB (i.e. full scale if oversampling filter

used).

32 =

12 dB.

0 = mute.

7.7.5

EAK DETECTOR

The peak detector measures the highest audio level
(absolute value) on positive peaks for left and right
channels. The 8 most significant bits are output in the
Q-channel data in place of the CRC bits. Bits 81 to 88
contain the left peak value (bit 88 = MSB) and
bits 89 to 96 contain the right peak value (bit 96 = MSB).
The values are reset after reading Q-channel data via
SDA.

Fig.10 Concealment mechanism.

Interpolation

Hold

Interpolation

MGA372

Error

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

7.8

DAC interface

The SAA7377 is compatible with a wide range of digital-to-analog converters (DACs). Nine formats are supported and
are given in Table 4. Figures 11 and 12 show the Philips I

S-bus and the EIAJ data formats respectively. All formats are

MSB first and f

is 44.1 kHz. The polarity of the WCLK and the data can be inverted; selectable by register 7.

Table 4

DAC interface formats

Note

1. In this mode the first 16 bits contain data, but if any of the fade, attenuate or de-emphasis filter functions are activated

then the first 18 bits contain data.

REGISTER 3

SAMPLE

FREQUENCY

NUMBER OF

BITS

SCLK (MHz)

FORMAT

INTERPOLATION

1110

16/18

(1)

2.1168

Philips I

S-bus; 16/18 bits

(1)

yes

0010

2.1168

EIAJ 16 bits

yes

0110

2.1168

EIAJ 18 bits

yes

0000

8.4672

EIAJ 16 bits

yes

0100

8.4672

EIAJ 18 bits

yes

1100

8.4672

Philips I

S-bus; 18 bits

yes

0011

4.2336

EIAJ 16 bits

yes

0111

4.2336

EIAJ 18 bits

yes

1111

4.2336

Philips I

S-bus; 18 bits

yes

1998

Jul

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc

decoder (CD7)

SAA7377

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LEFT CHANNEL DATA (WCLK NORMAL POLARITY)

SCLK

15 14

DATA

WCLK

MGD036

Fig.11 Philips I

S-bus data format (16-bit word length shown).

SCLK

DATA

WCLK

LEFT CHANNEL DATA

MGD035

Fig.12 EIAJ data format (18-bit word length shown).

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

7.9

EBU interface

The bi-phase mark digital output signal at pin DOBM is
in accordance with the format defined by the IEC958
specification. The DOBM pin can be held LOW and
selected via register A.

7.9.1

ORMAT

The digital audio output consists of 32-bit words
(`subframes') transmitted in bi-phase mark code (two
transitions for a logic 1 and one transition for a logic 0).
Words are transmitted in blocks of 384. Table 5 gives the
formats.

Table 5

Format

Table 6

Description of Table 5

Table 7

Bit assignment

FUNCTION

BITS

DESCRIPTION

Sync

0 to 3

Auxiliary

4 to 7

not used; normally zero

Error flags

CFLG error and interpolation flags when selected by register A

Audio sample

8 to 27

first 4 bits not used (always zero). 2's compliment. LSB = bit 12, MSB = bit 27

Validity flag

valid = logic 0

User data

used for subcode data (Q-to-W)

Channel status

control bits and category code

Parity bit

even parity for bits 4 to 30

FUNCTION

DESCRIPTION

Sync

The sync word is formed by violation of the bi-phase rule and therefore does not contain any data.
Its length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations:
sync B: start of a block (384 words), word contains left sample; sync M: word contains left sample
(no block start) and sync W: word contains right sample.

Audio sample

Left and right samples are transmitted alternately.

Validity flag

Audio samples are flagged (bit 28 = 1) if an error has been detected but was uncorrectable. This
flag remains the same even if data is taken after concealment.

User data

Subcode bits Q-to-W from the subcode section are transmitted via the user data bit. This data is
asynchronous with the block rate.

Channel status

The channel status bit is the same for left and right words. Therefore a block of 384 words contains
192 channel status bits. The category code is always CD. The bit assignment is given in Table 7.

FUNCTION

BITS

DESCRIPTION

Control

0 to 3

copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when copy
permitted; bit 3 is logic 1 when recording has pre-emphasis

Reserved mode

4 to 7

always zero

Category code

8 to 15

CD: bit 8 = logic 1, all other bits = logic 0

Clock accuracy

28 to 29

set by register A; 10 = level I; 00 = level II; 01 = level III

Remaining

16 to 27 and

30 to 191

always zero

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

7.10

KILL circuit

The KILL circuit detects digital silence by testing for an
all-zero or all-ones data word in the left or right channel
before the digital filter. The output is switched active LOW
when silence has been detected for at least 250 ms, or if
mute is active. Two modes are available which can be
selected by register C:

1 pin kill: KILL active LOW indicates silence detected on
both left and right channels.

2 pin kill: KILL active LOW indicates silence detected on
left channel. V3 active LOW indicates silence detected
on right channel.

7.11

The VIA interface

The SAA7377 has five pins that can be reconfigured for
different applications (see Table 8).

Table 8

Pin applications

PIN NAME

PIN

NUMBER

TYPE

CONTROL

REGISTER

ADDRESS

CONTROL

REGISTER

DATA

FUNCTION

input

1100

xxx1

external off-track signal input

xxx0

internal off-track signal used, input may be read
via decoder status bit; selected via register 2

input

input may be read via decoder status bit;
selected via register 2

output

1100

xx0x

KILL output for right channel

x01x

output = 0

x11x

output = 1

output

1101

0000

4-line motor drive (using V4 and V5)

xx01

Q-to-W subcode output

xx10

output = 0

xx11

output = 1

output

1101

01xx

de-emphasis output (active HIGH)

10xx

output = 0

11xx

output = 1

7.12

Spindle motor control

7.12.1

OTOR OUTPUT MODES

The spindle motor speed is controlled by a fully integrated
digital servo. Address information from the internal

�

8 frame FIFO and disc speed information are used to

calculate the motor control output signals. Several output
modes, selected by register 6, are supported:

�

Pulse density, 2-line (true complement output), 1 MHz
sample frequency

�

PWM output, 2-line, 22.05 kHz modulation frequency

�

PWM output, 4-line, 22.05 kHz modulation frequency

�

CDV motor mode.

7.12.1.1

Pulse density output mode

In the pulse density mode the motor output pin (MOTO1)
is the pulse density modulated motor output signal. A 50%
duty factor corresponds with the motor not actuated,
higher duty factors mean acceleration, lower mean
braking. In this mode, the MOTO2 signal is the inverse of
the MOTO1 signal. Both signals change state only on the
edges of a 1 MHz internal clock signal. Possible
application diagrams are illustrated in Fig.13.

7.12.1.2

PWM output mode (2-line)

In the PWM mode the motor acceleration signal is put
in pulse-width modulation form on the MOTO1 output.
The motor braking signal is pulse-width modulated on the
MOTO2 output. The timing is illustrated in Fig.14. A typical
application diagram is illustrated in Fig.15.

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

7.12.1.4

CDV/CAV output mode

In the CDV motor mode, the FIFO position will be put in
pulse-width modulated form on the MOTO1 pin (carrier
frequency = 300 Hz). The PLL frequency signal will be put
in pulse-density modulated form (carrier
frequency = 4.23 MHz) on the MOTO2 pin. The integrated
motor servo is disabled in this mode.

The PWM signal on MOTO1 corresponds to a total
memory space of 20 frames, therefore the nominal FIFO
position (half full) will result in a PWM output of 60%.

7.12.2

PINDLE MOTOR OPERATING MODES

The operation modes of the motor servo is controlled by
register 1 (see Table 9).

In the SAA7377 decoder there is an anti-wind-up mode for
the motor servo, selected via register 1. When the
anti-wind-up mode is activated the motor servo integrator
will hold if the motor output saturates.

7.12.2.1

Power limit

In start mode 1, start mode 2, stop mode 1 and stop
mode 2, a fixed positive or negative voltage is applied to
the motor.

This voltage can be programmed as a percentage of the
maximum possible voltage, via register 6, to limit current
drain during start and stop. The following power limits are
possible;

100% (no power limit), 75%, 50%, or 37% of maximum.

7.12.3

OOP CHARACTERISTICS

The gain and crossover frequencies of the motor control
loop can be programmed via registers 4 and 5.
The following parameter values are possible;

Gains: 3.2, 4.0, 6.4, 8.0, 12.8, 16, 25.6 and 32

Crossover frequency f

: 0.5 Hz, 0.7 Hz, 1.4 Hz, 2.8 Hz

Crossover frequency f

: 0.85 Hz, 1.71 Hz, 3.42 Hz.

7.12.4

FIFO

OVERFLOW

If FIFO overflow occurs during Play mode (e.g. as a result
of motor rotational shock), the FIFO will be automatically
reset to 50% and the audio interpolator tries to conceal as
much as possible to minimise the effect of data loss.

Table 9

Operating modes

MODE

DESCRIPTION

Start mode 1

The disc is accelerated by applying a positive voltage to the spindle motor. No decisions are
involved and the PLL is reset. No disc speed information is available for the microcontroller.

Start mode 2

The disc is accelerated as in start mode 1, however the PLL will monitor the disc speed. When the
disc reaches 75% of its nominal speed, the controller will switch to jump mode. The motor status
signals selectable via register 2 are valid.

Jump mode

Motor servo enabled but FIFO kept reset at 50%, integrator is held. The audio is muted but it is
possible to read the subcode.

Jump mode 1

Similar to jump mode but motor integrator is kept at zero. Used for long jumps where there is a large
change in disc speed.

Play mode

FIFO released after resetting to 50%. Audio mute released.

Stop mode 1

Disc is braked by applying a negative voltage to the motor. No decisions are involved.

Stop mode 2

The disc is braked as in stop mode 1 but the PLL will monitor the disc speed. As soon as the disc
reaches 12% (or 6%, depending on the programmed brake percentage, via register E) of its
nominal speed, the MOTSTOP status signal will go HIGH and switch the motor servo to Off mode.

Off mode

Motor not steered.

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

Fig.18 Motor servo mode diagram.

MGA362 - 2

7.13

Servo part

7.13.1

IODE SIGNAL PROCESSING

The photo detector in conventional two-stage three-beam
compact disc systems normally contains six discrete
diodes. Four of these diodes (three for single Foucault
systems) carry the central aperture signal (CA) while the
other two diodes (satellite diodes) carry the radial tracking
information. The CA signal is processed into an HF signal
(for the decoder function) and LF signal (information for the
focus servo loop) before it is supplied to the SAA7377.

The analog signals from the central and satellite diodes
are converted into a digital representation using
analog-to-digital converters (ADCs). The ADCs are
designed to convert unipolar currents into a digital code.
The dynamic range of the input currents is adjustable
within a given range, which is dependent on the value of
the external resistor connected to pin I

refT

. The maximum

current for the central diodes and satellite diodes is given
in the following formulae;

�

The V

voltage is internally generated by control circuitry

which ensures that the V

voltage is adjusted depending

on the spread of internal capacitors, using the reference

in max central

(

)

2.4

�

IrefT

------------------------

in max satellite

(

)

1.2

�

IrefT

------------------------

current generated by the external resistor on I

refT

. In the

application V

is connected to V

SSA1

. The maximum input

currents for a range of resistors is given Table 10.

Table 10 Maximum current input

This mode of V

automatic adjustment can be selected

by the preset latch command.

Alternatively, the dynamic range of the input currents can
be made dependent on the ADC reference voltages V

and V

. The maximum current for the central diodes and

satellite diodes is given in the following formulae;

IrefT

)

DIODE INPUT CURRENT RANGE

D1 TO D4 (

�

R1 AND R2 (

�

220

10.909

5.455

240

10.000

5.000

270

8.889

4.444

300

8.000

4.000

330

7.273

3.636

360

6.667

3.333

390

6.154

3.077

430

5.581

2.791

470

5.106

2.553

510

4.706

2.353

560

4.286

2.143

620

3.871

1.935

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

�

Where f

sys

= 4.2336 MHz.

is generated internally, and there are 32 levels which

can be selected under software control via the preset latch
command. With this command the V

voltage can be set

to 2.5 V then modified, decremented one level or
incremented, by re-sending the command the required
number of times. In the application V

is connected to

SSA1

7.13.2

IGNAL CONDITIONING

The digital codes retrieved from the ADCs are applied to
logic circuitry to obtain the various control signals. The
signals from the central aperture diodes are processed to
obtain a normalised focus error signal.

where the detector set-up is assumed as shown in Fig.19.

In the event of single Foucault focusing method, the signal
conditioning can be switched under software control such
that the signal processing is as follows;

in max central

(

)

sys

�

(

)

1.0

�

in max satellite

(

)

sys

�

(

)

0.5

�

----------------------

�

----------------------

�

----------------------

�

The error signal, FE

, is further processed by a

proportional integral and differential (PID) filter section.

A Focus OK (FOK) flag is generated by means of the
central aperture signal and an adjustable reference level.
This signal is used to provide extra protection for the
track-loss (TL) generation, the focus start-up procedure
and the drop out detection.

The radial or tracking error signal is generated by the
satellite detector signals R1 and R2. The radial error signal
can be formulated as follows;

where the index `s' indicates the automatic scaling
operation which is performed on the radial error signal.
This scaling is necessary to avoid non-optimum dynamic
range usage in the digital representation and reduces the
radial bandwidth spread. Furthermore, the radial error
signal will be made free from offset during start up of the
disc.

The four signals from the central aperture detectors,
together with the satellite detector signals generate a track
position signal (TPI) which can be formulated as follows;

TPI = sign [(D1 + D2 + D3 + D4)

(R1 + R2)

�

sum_gain]

Where the weighting factor sum_gain is generated
internally by the SAA7377 during initialization.

�

(

)

re_gain

�

(

)

re_offset

�

Fig.19 Detector arrangement.

handbook, full pagewidth

SATELLITE

DIODE R1

SATELLITE

DIODE R2

SATELLITE

DIODE R1

SATELLITE

DIODE R2

SATELLITE

DIODE R1

SATELLITE

DIODE R2

single Foucault

astigmatic focus

double Foucault

MBG422

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

7.13.3

OCUS SERVO SYSTEM

7.13.3.1

Focus start-up

Five initially loaded coefficients influence the start-up
behaviour of the focus controller. The automatically
generated triangle voltage can be influenced by
3 parameters; for height (ramp_height) and DC offset
(ramp_offset) of the triangle and its steepness
(ramp_incr).

For protection against false focus point detections two
parameters are available which are an absolute level on
the CA-signal (CA_start) and a level on the FE

signal

(FE_start). When this CA level is reached the FOK signal
becomes true.

If the FOK signal is true and the level on the FE

signal is

reached, the focus PID is enabled to switch on when the
next zero crossing is detected in the FE

signal.

7.13.3.2

Focus position control loop

The focus control loop contains a digital PID controller
which has 5 parameters which are available to the user.
These coefficients influence the integrating (foc_int),
proportional (foc_lead_length, part of foc_parm3) and
differentiating (foc_pole_lead, part of foc_parm1) action of
the PID and a digital low-pass filter (foc_pole_noise, part
of foc_parm2) following the PID. The fifth coefficient
foc_gain influences the loop gain.

7.13.3.3

Drop-out detection

This detector can be influenced by one parameter
(CA_drop). The FOK signal will become false and the
integrator of the PID will hold if the CA signal drops below
this programmable absolute CA level. When the FOK
signal becomes false it is assumed, initially, to be caused
by a black dot.

7.13.3.4

Focus loss detection and fast restart

Whenever FOK is false for longer than approximately
3 ms, it is assumed that the focus point is lost. A fast
restart procedure is initiated which is capable of restarting
the focus loop within 200 to 300 ms depending on the
programmed coefficients of the microcontroller.

7.13.3.5

Focus loop gain switching

The gain of the focus control loop (foc_gain) can be
multiplied by a factor of 2 or divided by a factor of 2 during
normal operation. The integrator value of the PID is
corrected accordingly. The differentiating (foc_pole_lead)

action of the PID can be switched at the same time as the
gain switching is performed.

7.13.3.6

Focus automatic gain control loop

The loop gain of the focus control loop can be corrected
automatically to eliminate tolerances in the focus loop.
This gain control injects a signal into the loop which is used
to correct the loop gain. Since this decreases the optimum
performance, the gain control should only be activated for
a short time (for example, when starting a new disc).

7.13.4

ADIAL SERVO SYSTEM

7.13.4.1

Level initialization

During start-up an automatic adjustment procedure is
activated to set the values of the radial error gain (re_gain),
offset (re_offset) and satellite sum gain (sum_gain) for TPI
level generation. The initialization procedure runs in a
radial open loop situation and is

300 ms. This start-up

time period may coincide with the last part of the motor
start-up time period.

Automatic gain adjustment: as a result of this
initialization the amplitude of the RE signal is adjusted to
within

�

10% around the nominal RE amplitude.

Offset adjustment: the additional offset in RE due to the
limited accuracy of the start-up procedure is less than

�

50 nm.

TPI level generation: the accuracy of the initialization
procedure is such that the duty factor range of TPI
becomes 0.4 < duty factor < 0.6 (definition of duty
factor = TPI HIGH/TPI period).

7.13.4.2

Sledge control

The microcontroller can move the sledge in both directions
via the steer sledge command.

7.13.4.3

Tracking control

The actuator is controlled using a PID loop filter with user
defined coefficients and gain. For stable operation
between the tracks, the S-curve is extended over

�

0.75 of

the track. On request from the microcontroller, S-curve
extension over

�

2.25 tracks is used, automatically

changing to access control when exceeding those
2.25 tracks.

Both modes of S-curve extension make use of a
track-count mechanism. In this mode, track counting
results in an `automatic return-to-zero track', to avoid
major music rhythm disturbances in the audio output for
improved shock resistance.

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

The sledge is continuously controlled, or provided with
step pulses to reduce power consumption using the
filtered value of the radial PID output. Alternatively, the
microcontroller can read the average voltage on the radial
actuator and provide the sledge with step pulses to reduce
power consumption. Filter coefficients of the continuous
sledge control can be preset by the user.

7.13.4.4

Access

The access procedure is divided into two different modes
(see Table 11), depending on the requested jump size.

Table 11 Access modes

Note

1. Microcontroller presettable.

The access procedure makes use of a track counting
mechanism, a velocity signal based on a fixed number of
tracks passed within a fixed time interval, a velocity set
point calculated from the number of tracks to go and a user
programmable parameter indicating the maximum sledge
performance.

If the number of tracks remaining is greater than the
brake_distance then the sledge jump mode should be
activated, or, the actuator jump should be performed.
The requested jump size together with the required sledge
breaking distance at maximum access speed defines the
brake_distance value.

During the actuator jump mode, velocity control with a PI
controller is used for the actuator. The sledge is then
continuously controlled using the filtered value of the radial
PID output. All filter parameters (for actuator and sledge)
are user programmable.

In the sledge jump mode maximum power (user
programmable) is applied to the sledge in the correct
direction while the actuator becomes idle (the contents of
the actuator integrator leaks to zero just after the sledge
jump mode is initiated).

ACCESS

TYPE

JUMP SIZE

(1)

ACCESS

SPEED

Actuator jump 1 - brake_distance

decreasing
velocity

Sledge jump

brake_distance - 32768

maximum
power to
sledge

(1)

7.13.4.5

Radial automatic gain control loop

The loop gain of the radial control loop can be corrected
automatically to eliminate tolerances in the radial loop.
This gain control injects a signal into the loop which is used
to correct the loop gain. Since this decreases the optimum
performance, the gain control should only be activated for
a short time (for example, when starting a new disc).

This gain control differs from the level initialization.
The level initialization should be performed first.
The disadvantage of using the level initialization without
the gain control is that only tolerances from the front-end
are reduced.

7.13.5

TRACK COUNTING

The track position signal (TPI) is a flag which is used to
indicate whether the radial spot is positioned on the track,
with a margin of

�

of the track-pitch. In combination with

the radial polarity flag (RP) the relative spot position over
the tracks can be determined. These signals are, however,
afflicted with some uncertainties caused by;

�

Disc defects such as scratches and fingerprints

�

The HF information on the disc, which is considered as
noise by the detector signals.

In order to determine the spot position with sufficient
accuracy, extra conditions are necessary to generate a
track loss signal (TL) and an off-track counter value. These
extra conditions influence the maximum speed and this
implies that, internally, one of the following three counting
states is selected;

1. Protected state: used in normal play situations. A good

protection against false detection caused by disc
defects is important in this state.

2. Slow counting state: used in low velocity track jump

situations. In this state a fast response is important
rather than the protection against disc defects (if the
phase relationship between TL and RP of

radians

is affected too much, the direction cannot then be
determined accurately).

3. Fast counting state: used in high velocity track jump

situations. Highest obtainable velocity is the most
important feature in this state.

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

7.13.6

EFECT DETECTION

Fig.20 Block diagram of defect detector.

handbook, full pagewidth

DECIMATION

FILTER

FAST

FILTER

DEFECT

GENERATION

PROGRAMMABLE

HOLD-OFF

SLOW

FILTER

defect
output

sat1

sat2

MBG421

A defect detection circuit is incorporated into the
SAA7377. If a defect is detected, the radial and focus error
signals may be zeroed, resulting in better playability. The
defect detector can be switched off, applied only to focus
control or applied to both focus and radial controls under
software control (part of foc_parm1).

The defect detector (see Fig.20) has programmable set
points selectable by the parameter defect_parm.

7.13.7

TRACK DETECTION

During active radial tracking, off-track detection has been
realised by continuously monitoring the off-track counter
value. The off-track flag becomes valid whenever the
off-track counter value is not equal to zero. Depending on
the type of extended S-curve, the off-track counter is reset
after 0.75 extend or at the original track in the 2.25 track
extend mode.

7.13.8

HIGH

LEVEL FEATURES

7.13.8.1

Interrupt mechanism and STATUS pin

The STATUS pin is an output which is active LOW, its
output is selected by register 7 to be either the status bit
(active LOW) selected by register 2 (only available in
4-wire bus mode) or the interrupt signal generated by the
servo part.

8 signals from the interrupt status register are selectable
from the servo part via the interrupt_mask parameter. The
interrupt is reset by sending the read high-level status
command. The 8 signals are as follows:

1. Focus lost: drop out of longer than 3 ms.

2. Subcode ready.

3. Subcode absolute seconds changed.

4. Subcode discontinuity detected: new subcode time

before previous subcode time, or more than 10 frames
later than the previous subcode time.

5. Radial error: during radial on-track, no new subcode

frame occurs within time defined by playwatchtime
parameter. During radial jump, less than 4 tracks have

been crossed during time defined by jumpwatchtime
parameter.

6. Autosequencer state change.

7. Autosequencer error.

8. Subcode interface blocked: the internal decoder

interface is being used.

It should be noted that if the STATUS pin output is selected
via register 2 and either the microcontroller writes a
different value to register 2 or the decoder interface is
enabled then the STATUS output will change.

7.13.8.2

Decoder interface

The decoder interface allows registers 0 to F to be
programmed and subcode Q-channel data to be read via
servo commands. The interface is enabled/disabled by the
preset latch command (and the xtra_preset parameter).

7.13.8.3

Automatic error handling

Three watchdogs are present:

1. Focus: detects focus drop out of longer than 3 ms, sets

focus lost interrupt, switches off radial and sledge
servos, disables drive to disc motor.

2. Radial play: started when radial servo is on-track

mode and a first subcode frame is found. Detects
when maximum time between two subcode frames
exceeds time set by playwatchtime parameter; then
sets radial error interrupt, switches radial and sledge
servos off, puts disc motor in jump mode.

3. Radial jump: active when radial servo in long jump or

short jump modes. Detects when the off-track counter
value decreases by less than 4 tracks between two
readings (time interval set by jumpwatchtime
parameter); then sets radial jump error, switches radial
and sledge servos off to cancel jump.

The focus watchdog is always active, the radial watchdogs
are selectable via the radcontrol parameter.

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

7.13.8.4

Automatic sequencers and timer interrupts

Two automatic sequencers are implemented (and must be
initialized after power-on):

1. Autostart sequencer: controls the start-up of focus,

radial and motor.

2. Autostop sequencer: brakes the disc and shuts down

servos.

When the automatic sequencers are not used it is possible
to generate timer interrupts, defined by the
time_parameter coefficient.

7.13.8.5

High-level status

The read high-level status command can be used to obtain
the interrupt, decoder, autosequencer status registers and
the motor start time. Use of the read high-level status
command clears the interrupt status register, and
re-enables the subcode read via a servo command.

7.13.9

RIVER INTERFACE

The control signals (pins RA, FO and SL) for the
mechanism actuators are pulse density modulated. The
modulating frequency can be set to either 1.0584 MHz
(DSD mode) or 2.1168 MHz; controlled via the xtra_preset
parameter. An analog representation of the output signals
can be achieved by connecting a first-order low-pass filter
to the outputs.

During reset (i.e. RESET pin is held LOW) the RA, FO and
SL pins are high impedance.

7.13.10 L

ASER INTERFACE

The LDON pin (open-drain output) is used to switch the
laser off and on. When the laser is on the output is high
impedance. The action of the LDON pin is controlled by the
xtra_preset parameter; the pin is automatically driven if the
focus control loop is active.

7.13.11 R

ADIAL SHOCK DETECTOR

The shock detector (see Fig.21) can be switched on during
normal track following, and detects within an adjustable
frequency whether disturbances in the radial spot position
relative to the track exceed an adjustable level (controlled
by shock_level). Every time the radial tracking error (RE)
exceeds this level the radial control bandwidth is switched
to twice its original bandwidth and the loop gain is
increased by a factor of 4.

The shock detection level is adjustable in 16 steps from
0 to 100% of the traverse radial amplitude which is sent to
an amplitude detection unit via an adjustable band-pass
filter (controlled by sledge_parm1); lower corner frequency
can be set at either 0 or 20 Hz, and upper corner
frequency at 750 or 1850 Hz. The shock detector is
switched off automatically during jump mode.

Fig.21 Block diagram of radial shock detector.

handbook, full pagewidth

MGC914

SHOCK

OUTPUT

HIGH-PASS FILTER

(0 or 20 Hz)

LOW-PASS FILTER

(750 or 1850 Hz)

AMPLITUDE
DETECTION

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

7.14

Microcontroller interface

Communication on the microcontroller interface can be
set-up in two different modes:

1. 4-wire bus mode: protocol compatible with SAA7345

(CD6) and TDA1301 (DSIC2) where:

a) SCL = serial bit clock

b) SDA = serial data

c) RAB = R/W control and data strobe (active HIGH)

for writing to registers 0 to F, reading status bit
selected via register 2 and reading Q-channel
subcode.

d) SILD = R/W control and data strobe (active LOW)

for servo commands.

2. I

C-bus mode: I

C-bus protocol where SAA7377

behaves as slave device, activated by setting
RAB = HIGH and SILD = LOW where:

a) I

C-bus slave address (write mode) = 30H.

b) I

C-bus slave address (read mode) = 31H.

c) Maximum data transfer rate = 400 kbits/s

It should be noted that only servo commands can be used
therefore, writing to registers 0 to F, reading decoder
status and reading Q-channel subcode data must be
performed by servo commands.

7.14.1

ICROCONTROLLER INTERFACE

(4-

WIRE BUS MODE

)

7.14.1.1

Writing data to registers 0 to F

The sixteen 4-bit programmable configuration registers,
0 to F (see Table 12), can be written to via the
microcontroller interface using the protocol shown in
Fig.22.

It should be noted that SILD must be held HIGH; A3 to A0
identifies the register number and D3 to D0 is the data; the
data is latched into the register on the LOW-to-HIGH
transition of RAB.

7.14.1.2

Writing repeated data to registers 0 to F

The same data can be repeated several times (e.g. for a
fade function) by applying extra RAB pulses as shown in
Fig.23. It should be noted that SCL must stay HIGH
between RAB pulses.

7.14.1.3

Reading decoder status information on SDA

There are several internal status signals, selected via
register 2, which can be made available on the SDA line;

SUBQREADY-I: LOW if new subcode word is ready in
Q-channel register.

MOTSTART1: HIGH if motor is turning at 75% or more
of nominal speed.

MOTSTART2: HIGH if motor is turning at 50% or more
of nominal speed.

MOTSTOP: HIGH if motor is turning at 12% or less of
nominal speed. Can be set to indicate 6% or less
(instead of 12% or less) via register E.

PLL Lock: HIGH if sync coincidence signals are found.

V1: follows input on V1 pin.

V2: follows input on V2 pin.

MOTOR-OV: HIGH if the motor servo output stage
saturates.

FIFO-OV: HIGH if FIFO overflows.

SHOCK: MOTSTART2 + PLL Lock + MOTOR-OV +
FIFO-OV + servo interrupt signal + OTD (HIGH if shock
detected).

LA-SHOCK: latched SHOCK signal.

The status read protocol is shown in Fig.24. It should be
noted that SILD must be held HIGH.

7.14.1.4

Reading Q-channel subcode

To read the Q-channel subcode direct in the 4-wire bus
mode, the SUBQREADY-I signal should be selected as
status signal. The subcode read protocol is illustrated in
Fig.25.

It should be noted that SILD must be held HIGH; after
subcode read starts, the microcontroller may take as long
as it wants to terminate the read operation; when enough
subcode has been read (1 to 96 bits), terminate reading by
pulling RAB LOW.

Alternatively, the Q-channel subcode can be read using a
servo command as follows:

�

Use the read high-level status command to monitor the
subcode ready signal.

�

Send the read subcode command, and read the
required number of bytes (up to 12).

�

Send the read high-level status command; to re-enable
the decoder interface.

7.14.1.5

Behaviour of the SUBQREADY-I signal

When the CRC of the Q-channel word is good, and no
subcode is being read, the SUBQREADY-I status signal
will react as shown in Fig.26.

When the CRC is good and the subcode is being read, the
timing in Fig.27 applies.

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

If t

(SUBQREADY-I status LOW to end of subcode read

is below 2.6 ms, then t

= 13.1 ms (i.e. the microcontroller

can read all subcode frames if it completes the read
operation within 2.6 ms after the subcode is ready). If this
criterion is not met, it is only possible to guarantee that t

will be below 26.2 ms (approximately).

If subcode frames with failed CRCs are present, the t

and

times will be increased by 13.1 ms for each defective

subcode frame.

7.14.1.6

Write servo commands

A write data command is used to transfer data (a number
of bytes) from the microcontroller, using the protocol
shown in Fig.28. The first of these bytes is the command
byte and the following are data bytes; the number
(between 1 and 7) depends on the command byte.

It should be noted that RAB must be held LOW; the
command or data is interpreted by the SAA7377 after the
HIGH-to-LOW transition of SILD; there must be a
minimum time of 70

�

s between SILD pulses.

7.14.1.7

Writing repeated data in servo commands

The same data byte can be repeated by applying extra
SILD pulses as shown in Fig.29. SCL must stay HIGH
between the SILD pulses.

7.14.1.8

Read servo commands

A read data command is used to transfer data (status
information) to the microcontroller, using the protocol
shown in Fig.30. The first byte written determines the type
of command. After this byte a variable number of bytes can
be read. It should be noted that RAB must be held LOW;
after the end of the command byte (LOW-to-HIGH
transition on SILD) there must be a delay of 70

�

s before

reading data is started (i.e the next HIGH-to-LOW
transition on SILD); there must be a minimum time of 70

�

between SILD pulses.

7.14.2

ICROCONTROLLER INTERFACE

C-

BUS MODE

)

Bytes are transferred over the interface in groups (i.e.
servo commands) of which there are two types: write data
commands and read data commands.

The sequence for a write data command (that requires
3 data bytes) is as follows;

�

Send START condition

�

Send address 30H (write)

�

Write command byte

�

Write data byte 1

�

Write data byte 2.

�

Write data byte 3

�

Send STOP condition.

It should be noted that more than one command can be
sent in one write sequence.

The sequence for a read data command (that reads 2 data
bytes) is as follows;

�

Send START condition

�

Send address 30H (write)

�

Write command byte

�

Send STOP condition.

�

Send START condition

�

Send address 31H (read)

�

Read data byte 1

�

Read data byte 2

�

Send STOP condition.

It should be noted that the timing constraints specified for
the read and write servo commands must still be adhered
to.

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

7.14.3

UMMARY OF FUNCTIONS CONTROLLED BY REGISTERS

Table 12 Registers 0 to F

REGISTER

ADDRESS

DATA

FUNCTION

INITIAL

(1)

0
(fade and
attenuation)

0000

mute

reset

0010

attenuate

0001

full scale

0100

step down

0101

step up

1
(motor mode)

0001

x000

motor off mode

reset

x 001

motor stop mode 1

x010

motor stop mode 2

x011

motor start mode 1

x100

motor start mode 2

x101

motor jump mode

x111

motor play mode

x110

motor jump mode 1

1xxx

anti-windup active

0xxx

anti-windup off

reset

2
(status control)

0010

0000

status = SUBQREADY-I

reset

0001

status = MOTSTART1

0010

status = MOTSTART2

0011

status = MOTSTOP

0100

status = PLL Lock

0101

status = V1

0110

status = V2

0111

status = MOTOR-OV

1000

status = FIFO overflow

1001

status = shock detect

1010

status = latched shock detect

1011

status = latched shock detect reset

3
(DAC output)

0011

1100

S-bus; 18-bit; 4f

mode

reset

1111

S-bus; 18-bit; 2f

mode

1110

S-bus; 16-bit; f

mode

0000

EIAJ; 16-bit; 4f

0011

EAIJ; 16-bit; 2f

0010

EIAJ; 16-bit; f

0100

EIAJ; 18-bit; 4f

0111

EIAJ; 18-bit; 2f

0110

EIAJ; 18-bit; f

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

4
(motor gain)

0100

x000

motor gain G = 3.2

reset

x001

motor gain G = 4.0

x010

motor gain G = 6.4

x011

motor gain G = 8.0

x100

motor gain G = 12.8

x101

motor gain G = 16.0

x110

motor gain G = 25.6

x111

motor gain G = 32.0

0xxx

disable comparator clock divider

reset

1xxx

enable comparator clock divider; only if SELLPLL set HIGH

5
(motor bandwidth)

0101

xx00

motor f4 = 0.5 Hz

reset

xx01

motor f4 = 0.7 Hz

xx10

motor f4 = 1.4 Hz

xx11

motor f4 = 2.8 Hz

00xx

motor f3 = 0.85 Hz

reset

01xx

motor f3 = 1.71 Hz

10xx

motor f3 = 3.42 Hz

6
(motor output
configuration)

0110

xx00

motor power maximum 37%

reset

xx01

motor power maximum 50%

xx10

motor power maximum 75%

xx11

motor power maximum 100%

00xx

MOTO1, MOTO2 pins 3-state

reset

01xx

motor PWM mode

10xx

motor PDM mode

11xx

motor CDV mode

7
(DAC output and
status control)

0111

xx00

interrupt signal from servo at STATUS pin

reset

xx10

status bit from decoder status register at STATUS pin

x0xx

DAC data normal value

reset

x1xx

DAC data inverted value

0xxx

left channel first at DAC (WCLK normal)

reset

1xxx

right channel first at DAC (WCLK inverted)

8 (PLL loop filter
bandwidth)

see Table 13

9
(PLL equalization)

1001

0011

PLL loop filter equalization

reset

0001

PLL 30 ns over-equalization

0010

PLL 15 ns over-equalization

0100

PLL 15 ns under-equalization

0101

PLL 30 ns under-equalization

REGISTER

ADDRESS

DATA

FUNCTION

INITIAL

(1)

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

Note

1. The initial column shows the power-on reset state.

A
(EBU output)

1010

x010

level II clock accuracy (<1000 ppm)

reset

x011

level I clock accuracy (<50 ppm)

x110

level III clock accuracy (>1000 ppm)

x111

EBU off - output LOW

0xxx

flags in EBU off

reset

1xxx

flags in EBU on

B
(speed control)

1011

00xx

33.8688 MHz crystal present, or 8.4672 MHz crystal with
SELPLL set HIGH

reset

01xx

16.9344 MHz crystal present

xx00

standby 1:'CD-STOP' mode

reset

xx10

standby 2:'CD-PAUSE' mode

xx11

operating mode

C
(versatile pins
interface)

1100

xxx1

external off-track signal input at V1

xxx0

internal off-track signal used (V1 may be read via STATUS)

reset

xx0x

kill-L at KILL output, kill-R at V3 output

001x

V3 = 0; single KILL output

reset

011x

V3 = 1; single KILL output

D
(versatile pins
interface)

1101

0000

4-line motor (using V4 and V5)

xx01

Q-to-W subcode at V4

xx10

V4 = 0

xx11

V4 = 1

reset

01xx

de-emphasis signal at V5, no internal de-emphasis filter

10xx

V5 = 0

11xx

V5 = 1

reset

1110

0100

motor brakes to 12%

reset

0101

motor brakes to 6%

F
(subcode
interface)

1111

x000

subcode interface off

reset

x100

subcode interface on

0xxx

4-wire subcode

reset

1xxx

3-wire subcode

REGISTER

ADDRESS

DATA

FUNCTION

INITIAL

(1)

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

7.14.4

UMMARY OF SERVO COMMANDS

A list of the servo commands are given in Table 14. It should be noted that these are not fully backwards compatible with
DSIC2.

Table 14 CD7 servo commands

Notes

1. These commands only available when internal decoder interface is enabled.

2. <peak_l> and <peak_r> bytes are clocked out LSB first.

3. Decoder status flag information in <dec_stat> is only valid when the internal decoder interface is enabled.

COMMANDS

CODE

BYTES

PARAMETERS

Write commands

Write_focus_coefs1

17H

<foc_parm3> <foc_int> <ramp_incr> <ramp_height> <ramp_offset>
<FE_start> <foc_gain>

Write_focus_coefs2

27H

<defect_parm> <rad_parm_jump> <vel_parm2> <vel_parm1>
<foc_parm1> <foc_parm2> <CA_drop>

Write_focus_command

33H

<foc_mask> <foc_stat> <shock_level>

Focus_gain_up

42H

<foc_gain> <foc_parm1>

Focus_gain_down

62H

<foc_gain> <foc_parm1>

Write_radial coefs

57H

<rad_length_lead> <rad_int> <rad_parm_play> <rad_pole_noise>
<rad_gain> <sledge_parm2> <sledge_parm_1>

Preset_Latch

81H

<chip_init>

Radial_off

C1H

`1CH'

Radial_init

C1H

`3CH'

Short_jump

C3H

<tracks_hi> <tracks_lo> <rad_stat>

Long_jump

C5H

<brake_dist> <sledge_U_max> <tracks_hi> <tracks_lo> <rad_stat>

Steer_sledge

B1H

<sledge_level>

Preset_init

93H

<re_offset> <re_gain> <sum_gain>

Write_decoder_reg

(1)

D1H

<decoder_reg_data>

Write_parameter

A2H

<param_ram_addr> <param_data>

Read commands

Read_Q_subcode

(1)(2)

up to 12

<Q_sub1..10> <peak_l> <peak_r>

Read_status

70H

up to 5

<foc_stat> <rad_stat> <rad_int_lpf> <tracks_hi> <tracks_lo>

Read_hilevel_status

(3)

E0H

up to 4

Read_aux_status

F0H

up to 3

<re_offset> <re_gain> <sum_gain>

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

7.14.5

UMMARY OF SERVO COMMAND PARAMETERS

Table 15 Servo command parameters

PARAMETER

RAM

ADDRESS

AFFECTS

POR

VALUE

DETERMINES

foc_parm_1

focus PID

end of focus lead

defect detector enabling

foc_parm_2

focus PID

focus low-pass

focus error normalising

foc_parm_3

focus PID

focus lead length

minimum light level

foc_int

14H

focus PID

focus integrator crossover frequency

foc_gain

15H

focus PID

70H

focus PID loop gain

CA_drop

12H

focus PID

sensitivity of drop-out detector

ramp_offset

16H

focus ramp

asymmetry of focus ramp

ramp_height

18H

focus ramp

peak-to-peak value of ramp voltage

ramp_incr

focus ramp

slope of ramp voltage

FE_start

19H

focus ramp

minimum value of focus error

rad_parm_play

28H

radial PID

end of radial lead

rad_pole_noise

29H

radial PID

radial low-pass

rad_length_lead

1CH

radial PID

length of radial lead

rad_int

1EH

radial PID

radial integrator crossover frequency

rad_gain

2AH

radial PID

70H

radial loop gain

rad_parm_jump

27H

radial jump

filter during jump

vel_parm1

1FH

radial jump

PI controller crossover frequencies

vel_parm2

32H

radial jump

jump pre-defined profile

speed_threshold

48H

radial jump

maximum speed in fastrad mode

hold_mult

49H

radial jump

00H

sledge bandwidth during jump

brake_dist_max

21H

radial jump

maximum sledge distance allowed in fast actuator
steered mode

sledge_long_brake

58H

radial jump

7FH

brake distance of sledge

sledge_Umax

sledge

voltage on sledge during long jump

sledge_level

sledge

voltage on sledge when steered

sledge_parm_1

36H

sledge

sledge integrator crossover frequency

sledge_parm_2

17H

sledge

sledge low-pass frequencies

sledge gain

sledge operation mode

sledge_pulse1

46H

pulsed sledge

pulse width

sledge_pulse2

64H

pulsed sledge

pulse height

defect_parm

defect detector

defect detector setting

shock_level

shock detector

shock detector operation

playwatchtime

54H

watchdog

radial on-track watchdog time

jumpwatchtime

57H

watchdog

radial jump watchdog time-out

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

radcontrol

59H

watchdog

enable/disable automatic radial off feature

chip_init

set-up

level setting

enable/disable decoder interface

xtra_preset

4AH

set-up

38H

laser on/off

RA, FO and SL PDM modulating frequency

microcontroller communication to decoder part

cd6cmd

4DH

decoder interface

decoder part commands

interrupt_mask

53H

STATUS pin

enabled interrupts

seq_control

42H

autosequencer

autosequencer control

focus_start_time

5EH

autosequencer

focus start time

motor_start_time1

5FH

autosequencer

motor start 1 time

motor_start_time2

60H

autosequencer

motor start 2 time

radial_init_time

61H

autosequencer

radial initialization time

brake_time

62H

autosequencer

brake time

RadCmdByte

63H

autosequencer

radial command byte

osc_inc

68H

focus/radial AGC

AGC control

frequency of injected signal

phase_shift

67H

focus/radial AGC

phase shift of injected signal

level1

69H

focus/radial AGC

amplitude of signal injected

level2

6AH

focus/radial AGC

amplitude of signal injected

agc_gain

6CH

focus/radial AGC

focus/radial gain

PARAMETER

RAM

ADDRESS

AFFECTS

POR

VALUE

DETERMINES

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. All V

and V

connections must be made externally to the same power supply.

2. Equivalent to discharging a 100 pF capacitor via a 1.5 k

series resistor with a rise time of 15 ns.

3. Equivalent to discharging a 200 pF capacitor via a 2.5

�

H series inductor.

OPERATING CHARACTERISTICS

= 3.4 to 5.5 V; V

= 0 V; T

amb

10 to +70

�

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

supply voltage

note 1

0.5

+6.5

I(max)

maximum Input voltage (any input)

0.5

+ 0.5

output voltage (any output)

0.5

+6.5

DDdiff

difference between V

DDA

and V

DDD

�

0.25

output current (continuous)

�

DC input diode current (continuous)

�

amb

operating ambient temperature

+85

�

stg

storage temperature

+125

�

electrostatic handling

note 2

2000

+2000

note 3

200

+200

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

supply voltage

3.4

5.0

5.5

supply current

= 5 V

Decoder analog front-end (V

DDA

= 5 V; V

SSA

= 0 V; T

amb

= 25

�

OMPARATOR INPUTS

: HFIN

AND

HFREF

clk

clock frequency

note 1

MHz

th(sw)

switching voltage threshold

1.2

0.8

tpt

HFIN input voltage level

1.0

EFERENCE GENERATOR

: I

ref

Iref

reference voltage level
(pin 18)

0.5V

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

Servo analog part (V

DDA

= 5 V; V

SSA

= 0 V; T

amb

= 25

�

INS

D4, R1, R2, V

, V

AND

refT

input reference current

1.935

5.45

�

IrefT

external resistor on pin 10

220

620

IrefT

voltage on reference
current input

1.2

D(max)

maximum input current for
central diode input signal

note 2

3.871

10.9

�

R(max)

maximum input current for
satellite diode input signal

note 2

1.935

5.45

�

LOW level reference voltage

HIGH level reference
voltage

output state 0; note 3

0.5

output state v; note 3

30%

0.5

�

v/44.4

+30%

output state 31;
note 3

2.5

(THD+N)/S

total harmonic distortion plus
noise

at 0 dB; note 4

S/N

signal-to-noise ratio

PSRR

power supply ripple rejection
at V

DDA2

note 5

tol

gain tolerance

note 6

+12

variation of gain between
channels

channel separation

Digital inputs

NPUTS

: RESET, V1, V2, SELPLL (CMOS

INPUT WITH PULL

UP RESISTOR AND HYSTERESIS

)

thr(sw)

switching voltage threshold
rising

0.8V

DDD

thf(sw)

switching voltage threshold
falling

0.2V

DDD

hys

hysteresis voltage

0.33V

DDD

I(pu)

input pull-up resistance

= 0 V

input capacitance

resL

reset pulse width
(active LOW)

RESET only

�

NPUTS

: SCL, RAB, SILD

AND

RCK (CMOS

INPUT

)

LOW level input voltage

0.3

0.3V

HIGH level input voltage

0.7V

+ 0.3

input leakage current

= 0

+10

�

input capacitance

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

Digital outputs

UTPUT

: CL4

LOW level output voltage

= 1 mA

0.4

HIGH level output voltage

1 mA

DDD

0.4

DDD

load capacitance

output rise time

= 20 pF;

0.8 to (V

DDD

0.8)

output fall time

= 20 pF;

DDD

0.8) to 0.8

UTPUT

: CL16

LOW level output voltage

= 1 mA

0.4

HIGH level output voltage

1 mA

DDD

0.4

DDD

load capacitance

output rise time

= 20 pF;

0.8

DDD

0.8)

output fall time

= 20 pF;

DDD

0.8)

0.8

UTPUTS

: V4

AND

LOW level output voltage

DDD

= 4.5 to 5.5 V;

= 10 mA

1.0

DDD

= 3.4 to 5.5 V;

= 5 mA

1.0

HIGH level output voltage

DDD

= 4.5 to 5.5 V;

10 mA

DDD

= 3.4 to 5.5 V;

5 mA

DDD

load capacitance

output rise time

= 20 pF;

0.8

DDD

0.8)

output fall time

= 20 pF;

DDD

0.8)

0.8

Open-drain outputs

UTPUTS

: CFLG, C2FAIL, STATUS, KILL, V3

AND

LDON (

OPEN

DRAIN OUTPUT WITH PROTECTION DIODE TO

)

LOW level output voltage

= 1 mA

0.4

LOW level output current

load capacitance

output fall time

= 20 pF;

DDD

0.8)

0.8

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

3-state outputs

UTPUTS

: CLK, WCLK, DATA

AND

CL11

LOW level output voltage

= 1 mA

0.4

HIGH level output voltage

1 mA

0.4

load capacitance

output rise time

= 20 pF;

0.8

0.8)

output fall time

= 20 pF;

0.8)

0.8

output 3-state leakage
current

= 0

+10

�

UTPUT

: CL11

output HIGH time (relative to
clock period)

= 1.5 V

UTPUTS

: RA, FO, SL, SBSY, SFSY

AND

SUB

LOW level output voltage

= 1 mA

0.4

HIGH level output voltage

1 mA

0.4

load capacitance

output rise time

= 20 pF;

0.8

0.8)

output fall time

= 20 pF;

0.8)

0.8

3-state leakage current

= 0

+10

�

UTPUTS

: MOTO1, MOTO2

AND

DOBM

LOW level output voltage

= 4.5 to 5.5 V;

= 10 mA

1.0

= 3.4 to 5.5 V;

= 5 mA

1.0

HIGH level output voltage

= 4.5 to 5.5 V;

10 mA

= 3.4 to 5.5 V;

5 mA

load capacitance

output rise time

= 20 pF;

0.8

0.8)

output fall time

= 20 pF;

0.8)

0.8

3-state leakage current

= 0

+10

�

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

Notes

1. Highest clock frequency at which data slicer produces 1010 output in analog self-test mode.

2. V

= 0 V, f

sys

= 4.2336 MHz. The maximum input current depends on the value of the external resistor connected

to I

refT

a) For D1 to D4: I

max

= 2.4/R

IrefT

2.4/220 k

= 10.9

�

b) For R1 and R2: I

max

= 1.2/R

IrefT

1.2/20 k

= 5.45

�

3. Internal reference source with 32 different output voltages. Selection is achieved during a calibration period or via

the serial interface. The values given are for an unloaded V

4. V

= 2.5 V and V

= 0 V, measuring bandwidth: 200 Hz to 20 kHz, f

i(ADC)

= 1 kHz.

5. f

ripple

= 1 kHz, V

ripple

= 0.5 V (p-p).

6. Gain of the ADC is defined as G

ADC

= f

sys

max

(counts/

�

A); thus digital output = I

�

ADC

where;

a) Digital output = the number of pulses at the digital output in counts/s and I

= the DC input current in

�

b) The maximum input current depends on the system frequency (f

sys

= 4.2336 MHz) and on V

c) The gain tolerance is the deviation from the calculated gain regarding note 2.

7. It is recommended that the series resistance of the crystal or ceramic resonator is

Digital input/output

NPUT

OUTPUT

: SDA [CMOS

INPUT

OPEN

DRAIN

C-

BUS OUTPUT

(

WITH PROTECTION DIODE TO

DDD

)]

LOW level input voltage

0.3

0.3V

DDD

HIGH level input voltage

0.7V

DDD

+ 0.3

3-state leakage current

= 0

DDD

+10

�

input capacitance

LOW level output voltage

= 2 mA

0.4

LOW level output current

load capacitance

output fall time

= 20 pF;

DDD

0.8)

0.8

Crystal oscillator

NPUT

: CRIN (

EXTERNAL CLOCK

)

LOW level input voltage

0.3

0.3V

HIGH level input voltage

0.7V

+ 0.3

input leakage current

+10

�

input capacitance

UTPUT

: CROUT; see Figs 3 and 4

xtal

crystal frequency

note 7

8.4672

MHz

mutual conductance at
100 kHz

mA/V

small signal voltage gain

= g

�

V/V

feedback capacitance

out

output capacitance

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

11 OPERATING CHARACTERISTICS (I

S-BUS TIMING)

= 3.4 to 5.5 V; V

= 0 V; T

amb

10 to +70

�

C; unless otherwise specified

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

S-bus timing; see Fig.32

LOCK OUTPUT

: SCLK (C

= 20 pF)

output clock period

sample rate = f

472.4

sample rate = 2f

236.2

sample rate = 4f

118.1

clock HIGH time

sample rate = f

166

sample rate = 2f

sample rate = 4f

clock LOW time

sample rate = f

166

sample rate = 2f

sample rate = 4f

UTPUTS

: WCLK

AND

DATA (C

= 20 pF)

set-up time

sample rate = f

sample rate = 2f

sample rate = 4f

hold time

sample rate = f

sample rate = 2f

sample rate = 4f

Fig.32 I

S-bus timing diagram.

V � 0.8 V

0.8 V

V � 0.8 V

0.8 V

t CH

MGD026

t CL

clock period Tcy

SCLK

WCLK

DATA

t h

t su

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

12 OPERATING CHARACTERISTICS (MICROCONTROLLER INTERFACE TIMING)

= 3.4 to 5.5 V; V

= 0 V; T

amb

10 to +70

�

C; unless otherwise specified.

Notes

1. Negative set-up time means that the data may change after clock transition.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Microcontroller interface timing (4-wire bus mode; writing to registers 0 to F; reading Q-channel subcode and
decoder status); see Figs 33 and 34

NPUTS

SCL

AND

RAB

input LOW time

500

input HIGH time

500

rise time

480

fall time

480

EAD MODE

= 20 pF)

dRD

delay time RAB to SDA valid

propagation delay SCL to SDA

700

980

dRZ

delay time RAB to SDA high-impedance

RITE MODE

((C

= 20 pF)

suD

set-up time SDA to SCL

note 1

700

hold time SCL to SDA

980

suCR

set-up time SCL to RAB

260

dWZ

delay time SDA high-impedance to RAB

Microcontroller interface timing (4-wire bus mode; servo commands); see Figs 35 and 36

NPUTS

SCL

AND

SILD

input LOW time

710

input HIGH time

710

rise time

240

fall time

240

EAD MODE

= 20 pF)

dLD

delay time SILD to SDA valid

propagation delay SCL to SDA

950

dLZ

delay time SILD to SDA high-impedance

sCLR

set-up time SCL to SILD

480

hCLR

hold time SCL to SILD

830

RITE MODE

= 20 pF)

set-up time SDA to SCL

hold time SCL to SDA

950

sCL

set-up time SCL to SILD

480

hCL

hold time SILD to SCL

120

dPLP

delay between two SILD pulses

�

dWZ

delay time SDA high-impedance to SILD

1998

Jul

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc

decoder (CD7)

SAA7377

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APPLICA

TION INFORMA

TION

handbook, full pagewidth

53 52 51 50

100

64 63 62 61 60 59 58 57 56 55 54

28 29 30 31 32

17 18 19 20 21 22 23 24 25 26 27

(1)

(3)

LDON

D3
D4

RFE

TDA1300

(2)

SAA7377

to DOBM
transformer

to power

amplifiers

22 nF

2.2

VSSA1
VDDA1

VDDA

VDD

HFREF

LDON

VRL
D4

IrefT
VRH
VSSA2
SELPLL

ISLICE

HFIN

VSSA3

VDDA

I ref

DDA2

TEST1

CRIN

CROUT

TEST2

CL16

CL11

TEST3

DDD1(P)

DOBM

SSD1

CFLG

C2FAIL

DDD3C

STATUS

RESET

SSD4

n.c.

SILD

RAB

SCL

SDA

CL4

SSD3

VDDD

VDDD2(P)

VDDD

WCLK

SCLK

DATA

TEST4

KILL

VSSD2

SUB

RCK

SFSY

SBSY

MOTO2

MOTO1

to DAC

to CD

graphics

2.2

4.7
k

270

2.2 k

100 nF

microcontroller

interface

�

220 pF

47
pF

220 pF

100 k

2.2 nF

MOTOR

INTERFACE

100 nF

MGR305

Fig.37 Typical SAA7377 application diagram.

(1) The diagram is for 5 V application. For 3.4 V

application an additional resistor of 150 k

should be

connected between pin 18 and ground.

(2) For crystal oscillator circuit see Figs 3 and 4.

(3) The connections to TDA1300 are shown for single

Foucault mechanisms.

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

15 SOLDERING

15.1

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

15.2

Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

"Quality

Reference Handbook" (order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250

�

15.3

Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.

If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

�

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

�

The footprint must be at an angle of 45

�

to the board

direction and must incorporate solder thieves
downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

�

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

�

C within

6 seconds. Typical dwell time is 4 seconds at 250

�

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

15.4

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

�

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

�

1998 Jul 06

Philips Semiconductors

Product specifications

Digital servo processor and Compact Disc
decoder (CD7)

SAA7377

16 DEFINITIONS

17 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

18 PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Short-form specification

The data in this specification is extracted from a full data sheet with the same type
number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors � a worldwide company

� Philips Electronics N.V. 1998

SCA60

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Printed in The Netherlands

545102/00/01/pp56

Date of release: 1998 Jul 06

Document order number:

9397 750 04003

Электронный компонент: SAA7377GP/E

Document Outline