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Электронный компонент: SAA7385GP

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DATA SHEET
Preliminary specification
File under Integrated Circuits, IC01
1996 Jun 19
INTEGRATED CIRCUITS
SAA7385
Error correction and host interface
IC for CD-ROM (SEQUOIA)
1996 Jun 19
2
Philips Semiconductors
Preliminary specification
Error correction and host interface IC
for CD-ROM (SEQUOIA)
SAA7385
CONTENTS
1
FEATURES
1.1
General
1.2
53CF94 SCSI controller
1.3
80C32 high-speed microcontroller
1.4
Front-end interface logic
1.5
Buffer controller
1.6
Hardware third-level error correction
1.7
Additional product support
2
GENERAL DESCRIPTION
3
QUICK REFERENCE DATA
4
ORDERING INFORMATION
5
BLOCK DIAGRAM
6
PINNING
7
FUNCTIONAL DESCRIPTION
7.1
80C32 microcontroller
7.2
53CF94 fast SCSI controller
7.3
Input clock doubler
7.4
Front-end
8
MICROCONTROLLER INTERFACE
8.1
Microcontroller interface status register
8.2
Microcontroller interface command register
8.3
Microcontroller interrupts
8.4
Microcontroller RAM organization
9
FRONT PANEL AND MISCELLANEOUS
CONTROL SIGNALS
9.1
S2B UART registers
9.2
Miscellaneous control registers
10
FRONT-END
10.1
Minute Second Frame (MSF) addressing and
header information
10.2
Front-end status and control
11
BUFFER MANAGER
11.1
Front-end to buffer manager interface
11.2
Microcontroller to buffer manager interface
11.3
ECC to buffer manager interface
11.4
SCSI to buffer manager interface
11.5
Miscellaneous buffer manager considerations
11.6
53CF94 related registers
12
FRAME BUFFER ORGANIZATION
13
SUMMARY OF CONTROL REGISTER MAP
14
LIMITING VALUES
15
OPERATING CHARACTERISTICS
15.1
I
2
S-bus timing; data mode
15.2
EIAJ timing; audio mode
15.3
R-W timing (see Fig.15)
15.4
C-flag timing (see Fig.16)
15.5
S2B interface timing
15.6
SCSI interface timing
15.7
Microprocessor interface
15.8
DRAM interface (the SAA7385 is designed to
operate with standard 70 ns DRAMs)
16
PACKAGE OUTLINE
17
SOLDERING
17.1
Introduction
17.2
Reflow soldering
17.3
Wave soldering
17.4
Repairing soldered joints
18
DEFINITIONS
19
LIFE SUPPORT APPLICATIONS
1996 Jun 19
3
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (SEQUOIA)
SAA7385
1
FEATURES
1.1
General
Single chip digital solution for an 8
speed CD-ROM
controller chip
10 Mbytes/s NCR53CF94 equivalent SCSI controller
included
High-speed 80C32 microcontroller with 256
8
scratch-pad SRAM included
High performance CD-ROM interface logic
128 pin QFP package.
1.2
53CF94 SCSI controller
Separate clock input to allow operation up to the
maximum 10 Mbytes/s
Fast synchronous SCSI-2 compatible
24-bit transfer counter for single transfers up to
16 Mbytes
High-speed 16-bit DMA interface to the buffer manager
DRAM
On-chip 48 mA SCSI drivers
Software compatible with members of the 53C90 family
Allows for SCAM support.
1.3
80C32 high-speed microcontroller
33.87 MHz full system speed operation
Three timers/event counters
Programmable full duplex serial channel
Eight general purpose microcontroller I/O pins
External program ROM.
1.4
Front-end interface logic
Full 8
speed hardware operation
Block decoder
Sector sequencer
CRC checking of Mode 1 and Mode 2, Form 1 sectors
212 ms watch-dog timer
Sub-code interface with synchronization
C-flag interface for absolute time stamp.
1.5
Buffer controller
Ten level arbitration logic
Utilizes low cost 70 ns DRAMs
Page mode DRAM access for high-speed error
correction and SCSI data transfer
Data organization by 3 kbyte frames
256 kbyte or 1 Mbyte DRAM supported.
1.6
Hardware third-level error correction
Third-level correction provides superior performance in
unfavourable conditions
Full hardware error correction to reduce microcontroller
overhead
Corrections are automatically written to the DRAM
frame buffer.
1.7
Additional product support
All control registers mapped into 80C32 special function
memory space
Dedicated S2B interface UART
Input clock synthesizer
Red book audio pass through.
2
GENERAL DESCRIPTION
The SAA7385 is a high integration ASIC that incorporates
all of the digital electronics necessary to connect a CD
decoder to a SCSI host. An 80C32 microcontroller and a
53CF94 SCSI controller are embedded in the ASIC.
The following functions are supported:
Input clock doubler
Block decoder
CRC checking of Mode 1 and Mode 2, Form 1 sectors
Red book audio pass through to SCSI
Buffer manager
Third-level error correction
Sub-code and Q-channel support
Dedicated S2B interface UART
Embedded 80C32 microcontroller
Embedded 53CF94 SCSI controller.
1996 Jun 19
4
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (SEQUOIA)
SAA7385
The SAA7385 uses a 33.8688 MHz clock and is capable
of accepting data at eight times (n = 8 or 1.4 Mbytes/s) the
normal CD-ROM data rate.
Third level error correction hardware is included to
improve the correction efficiency of the system. The buffer
manager hardware utilizes a ten-level arbitration unit and
can stop the clock to the microcontroller to emulate a wait
condition when necessary.
The SAA7385 comprises five major functional blocks:
The 80C32 microcontroller is an industry standard core
The 53CF94 is an industry standard core
The front-end block connects to the external CD-60
based decoder and fully processes the incoming data
stream to provide bytes of data that are stored in the
external buffer
The buffer manager block provides the address
generation and timing control for the external DRAM
buffer
The ECC block performs the error correction functions in
hardware on the data in the DRAM buffer.
Supply of this Compact Disc IC does not convey an
implied license under any patent right to use this IC in
any Compact Disc application.
3
QUICK REFERENCE DATA
4
ORDERING INFORMATION
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
V
DD
digital supply voltage
4.5
5.0
5.5
V
T
amb
operating ambient temperature
0
-
70
C
T
stg
storage temperature
-
55
-
+150
C
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
SAA7385GP
SQFP128
plastic quad flat package; 128 leads (lead length 1.6 mm);
body 14
20
2.8 mm
SOT387-2
1996 Jun 19
5
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (SEQUOIA)
SAA7385
5
BLOCK DIAGRAM
6
PINNING
All input, output and bidirectional signals are TTL level unless otherwise stated (Pull-Down = PD25 = 25
A;
Pull-Up = PU25 = 25
A, PU400 = 400
A; Slew = S2 = 2 mA, S4 = 4 mA;
CMOS slew = CMOS S2 = CMOS 2 = 2 mA; SCSI pad = SCSI = 48 mA).
SYMBOL
PIN
I/O
PAD
DESCRIPTION
DA2
1
O
S4
DRAM address bus; bit DA2
DA3
2
O
S4
DRAM address bus; bit DA3
DA4
3
O
S4
DRAM address bus; bit DA4
V
SS1
4
-
-
ground 1
DA5
5
O
S4
DRAM address bus; bit DA5
DA6
6
O
S4
DRAM address bus; bit DA6
DA7
7
O
S4
DRAM address bus; bit DA7
DA8
8
O
S4
DRAM address bus; bit DA8
DA9
9
O
S4
DRAM address bus; bit DA9
V
DD1
10
-
-
power supply 1
Fig.1 Block diagram (simplified).
handbook, full pagewidth
MGE388
DATA
CONVERTER
AND SUB-CODE
UART
LAYERED
ERROR
CORRECTOR
BUFFER
MAPPER
53CF94
SCSI
BUFFER MANAGER
data
subcode
MICROCONTROLLER INTERFACE
DEBUG UART
80C32 MICROCONTROLLER
CD
DECODER
SERVO
PROCESSOR
data
SAA7385
subcode
C-flag
64K
8 ROM
256K
8 or 1M
8
DRAM BUFFER
SCSI
interface
debug
UART
S2B serial interface