1997 May 30

Philips Semiconductors

Product specification

Digital Audio Processing IC (DAPIC)

SAA7740H

FEATURES

Hardware

Two digital inputs and two digital outputs in the I

S-bus

format (i.e. 4 audio channels)

Independent input/output interfaces

Slave input/output interfaces

Slave processing

C-bus microcontroller interface

DC filtering at the inputs

One programmable 2nd-order digital filter unit

Two multiply accumulate processor units
(24

16-bit/MAC)

DRAM interface and address computation unit for
external delay lines

On-chip coefficient and external delay line address
storage

Hardware controlled soft mute via the MUTE pin

Hardware controlled soft demute via the RST pin

Operating ambient temperature;

40 to +85

Software

5-band parametric equalizer with selectable centre
frequency, slope setting and boost/cut gain settings
from

12 to +12 dB

Stereo width control from mono to stereo to spatial
stereo

Stereo Hall-effects for field acoustics, such as concert
halls, with 8 coefficients and 8 delayed taps per channel

External delay line processing for delays up to 1 second

Reverberation with selectable reverberation time (up to
5 seconds) and energy

Three different surround sound programs to obtain a
spatial effect on 4 loudspeakers

Passive DOLBY surround processing with the addition
of an external dynamic noise reduction IC

Karaoke processing

Dual 16th-order correction filtering

Quad 8th-order correction filtering

Digital volume and balance control

Soft controlled soft mute/demute via the microcontroller
interface

Input switching matrix

Output rear and front switching matrix.

APPLICATIONS

Digital amplifiers

Audio combination sets

Car audio systems

TV audio channels.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

DD(tot)

total DC supply voltage

all V

pins

4.5

5.0

5.5

DD(tot)

total DC supply current

xtal

= 16.9344 MHz

xtal

input crystal frequency

12.288

16.9344

23.0

MHz

tot

total power dissipation

xtal

= 16.9344 MHz

0.3

amb

operating ambient temperature

+85

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

SAA7740H

QFP64

plastic quad flat package; 64 leads (lead length 1.95 mm); body
14

2.8 mm

SOT319-2

1997 May 30

Philips Semiconductors

Product specification

Digital Audio Processing IC (DAPIC)

SAA7740H

PINNING

SYMBOL

PIN

DESCRIPTION

RST

reset input (active LOW)

SCL

serial clock input (I

C-bus)

SDA

serial data input/output (I

C-bus)

MUTE

mute input (active HIGH)

n.c.

not connected

n.c.

not connected

supply voltage

ground supply

CAS

column address strobe (DRAM)
(active LOW)

input/output data bus line 0 (DRAM)

input/output data bus line 1 (DRAM)

ground supply

output buffer enable (DRAM)
(active LOW)

input/output data bus line 2 (DRAM)

input/output data bus line 3 (DRAM)

CAS2

second column address strobe
(active LOW)

write enable (DRAM; active LOW)

RAS

row address strobe (DRAM;
active LOW)

A8B

inverse MSB address line output
(DRAM)

address line output 8 (DRAM)

address line output 7 (DRAM)

address line output 6 (DRAM)

address line output 5 (DRAM)

ground supply

supply voltage

address line output 4 (DRAM)

address line output 3 (DRAM)

address line output 2 (DRAM)

address line output 1 (DRAM)

address line output 0 (DRAM)

supply voltage

MUX

address latch strobe output (SRAM)

DO1D

digital audio output 1 (I

S-bus)

DO2D

digital audio output 2 (I

S-bus)

DOWS

digital audio input word select

DOBCK

digital audio input serial bit clock

supply voltage

n.c.

not connected

ground supply

DI1D

digital audio input 1 (I

S-bus)

DI2D

digital audio input 2 (I

S-bus)

DIWS

digital audio input word select

DIBCK

digital audio input serial bit clock

TSTCLK

clock input for test mode
(should be tied LOW)

ground supply

TST1

test pin input 1
(should be tied LOW)

TST2

test pin input 2
(should be tied LOW)

TST3

test pin input 3
(should be tied LOW)

ground supply

AS1

address select input 1 (I

C-bus)

AS2

address select input 2 (I

C-bus)

supply voltage

ground supply

CLK1/
XTAL1

clock or crystal input

n.c.

not connected

n.c.

not connected

XTAL2

crystal output 2

DDX

crystal supply voltage

SSX

crystal ground supply

SCCLK

scan test clock input
(should be tied LOW)

CLKO

clock signal output

ALL

mode select input
(should be tied HIGH)

SYMBOL

PIN

DESCRIPTION

1997 May 30

Philips Semiconductors

Product specification

Digital Audio Processing IC (DAPIC)

SAA7740H

GENERAL DESCRIPTION

The SAA7740H is a function-specific digital signal
processor. The device is capable of performing processing
for listening-environments such as equalization,
hall-effects, reverberation, surround-sound and digital
volume/balance control. The SAA7740H can also be
reconfigured (in a dual and quad filter mode) so that it can
be used as a digital filter with programmable
characteristics.

For reasons of silicon efficiency, the SAA7740H realises
most functions directly in hardware. The flexibility exists in
the possibility to download function parameters, correction
coefficients and various configurations from a host
microcontroller (see Fig.1). The parameters can be
passed in real time and all functions can be switched on
simultaneously.

The communication with a host microcontroller conforms
with the standard I

C-bus format. The SAA7740H accepts

2 digital stereo signals in the I

S-bus format at audio

sampling frequency (f

) and provides 2 digital stereo

outputs.

Mode description

The SAA7740H can be set in four basic modes of
operation.

ENERAL

DAPIC

MODE

In the general DAPIC mode two variants are available
(see Figs 3 and 4). In this mode the DAPIC accepts
2 stereo input signals. DC filtering is performed on the
inputs before further processing. On one of the stereo
inputs a 5-band graphic equalization can be performed.
The stereo image of this signal can be controlled from
mono to stereo.

In the first variant (see Fig.3) a stereo hall-effect can be
added to the signal by means of direct reflections. In the
second variant (see Fig.4) a reverberation effect can be
added to the signal by means of exponential decaying
reflections. Surround-sound can then be created for the
rear loudspeakers. The surround-sound module is also
able to provide karaoke.

The surround-sound module accepts the second stereo
input, a microphone signal can be added via the 5-band
equalizer. At the output, each of the 4 channels can be
individually delayed via the external DRAM.
The interfacing and addressing of the DRAM is performed
by the DAPIC.

The applications for the general mode are digital
amplifiers, audio combination sets and TV audio channels.

1997 May 30

Philips Semiconductors

Product specification

Digital Audio Processing IC (DAPIC)

SAA7740H

UAD

FILTER MODE

In the quad-filter mode two stereo signals are accepted
(see Fig.6). DC filtering is performed at the inputs before
further processing. A correction can be performed on the
input signals using a 4-band graphic equalizer, i.e. 8 poles
and 8 zeros can be placed arbitrarily in the Z-domain.
At the output, different delays can be applied to the
4 channels via the external DRAM. The interfacing and
addressing of the DRAM is performed by the DAPIC.

The application for this mode is in 4-channel correction
applications such as car and home audio systems.

TEREO EXPANSION MODE

In the stereo expansion mode one stereo signal is
accepted (see Fig.7). DC filtering is performed at the
inputs before further processing. A 4-band graphic
equalization is first performed after which a complex
stereo expansion is applied. A room effect can be added
by the addition of early reflections.

The applications for this mode are in the headphone
out-of-head and incredible stereo applications.

Fig.6 Quad filter mode.

handbook, full pagewidth

DELAY

MLC154

SWITCHES

FILTERS

SWITCHES

8 POLE/ZERO

CORRECTION

FILTER

(1)

8 POLE/ZERO

CORRECTION

FILTER

8 POLE/ZERO

CORRECTION

FILTER

8 POLE/ZERO

CORRECTION

FILTER

(1) External DRAM.

1997 May 30

Philips Semiconductors

Product specification

Digital Audio Processing IC (DAPIC)

SAA7740H

FUNCTIONAL DESCRIPTION

The SAA7740H is used as a slave device. The internal
operation is automatically synchronized with the word
select clock of the incoming data (I

S-bus format). Within

an input frame of data, at f

, 384 clock cycles are needed

to compute a stereo output sample. The external clock
therefore, should be minimum 384f

. External clocks

which generate more than 384 clocks cycles will cause the
processor to return to a wait state.

The external clock can be either a crystal connected
directly to the DAPIC, or any clock generated in the system
which contains DAPIC.

The I

S-bus

Two I

S-bus inputs and outputs are available on the

DAPIC. The serial clock (DIBCK and DOBCK) and the
word select (DIWS and DOWS) are applied from an
external source. The two inputs and outputs are fully
synchronized. However, the inputs do not have to be
synchronized with the outputs. The clock and word select
signals can be separated at the input and output.

The input and output buses support word lengths in
accordance with the I

S-bus standard. Up to 20 significant

bits can be read by the DAPIC. Zeros will be added at the
LSB position should less than 20 bits be applied. If more
than 20 bits are applied the extra LSBs will be ignored.
The stereo word rate (f

) can be either 32, 44.1 or 48 kHz.

Because the DAPIC is a slave device it can only be
connected to a master I

S-bus transmitter or receiver

(see Chapter "Timing characteristics" and Fig.9).

C-bus control (SCL and SDA)

The I

C-bus interface is used to control the operation of

the DAPIC for the audio signal processing and write the
coefficients and the external delay line addresses of the
different signal processing algorithms. New coefficients
are updated in real time to the internal RAM.

The transfer byte organization is as follows:

START condition

First byte (8 bits)

Acknowledge (1-bit)

Second byte (8 bits)

Acknowledge (1-bit)

Third to tenth byte (8 bits)

Acknowledge (1-bit)

STOP condition.

The first byte is the address of the I

C-bus device being

addressed. If the device detects its address it answers with
an acknowledge by pulling down the data line (SDA) for
one clock period (SCL line). The second byte contains the
address of the internal RAM to which the first new
coefficient should have written. The data will then be
transmitted. Each new word (coefficient) is 2 bytes wide.
Up to four words of data can be written within one transfer.
Should the mode of the feature register be addressed then
only one data word will be transferred.

Because the I

C-bus (on the DAPIC) is a slave receiver

bus, the clock has to be generated by the host
microcontroller.

The minimum time interval between two I

C-bus transfers

(bus free between a STOP and START condition) should

be:

Where:

Number of coefficients = coeff

Frequency f

should be in kHz.

inv

coeff

------------------------

Table 1

C-bus slave address.

Note

1. AS1 and AS2 are the hardware (pin) programmable address bits. When the device detects this address it will

respond with an acknowledge pulse on the SDA line.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

AS2

(1)

AS1

(1)

1997 May 30

Philips Semiconductors

Product specification

Digital Audio Processing IC (DAPIC)

SAA7740H

Improper acknowledge generated by the DAPIC

If an I

C-bus device, other than DAPIC, is addressed by the master then the DAPIC will generate a short acknowledge

pulse. The DAPIC starts pulling down the SDA line at the trailing edge of the SCL clock pulse. and releases the SDA line
approximately 390 ns after the leading edge of the following SCL LOW-to-HIGH transition (see Fig.8).

This improper acknowledge pulse can cause the I

C-bus master to detect an incorrect acknowledgement, depending on

the capturing moment of the SDA line by the I

C-bus master. Any possible non-acknowledgements of involved I

C-bus

devices, including the SAA7740H, will be masked thus making the system unreliable.

To avoid these problems the I

C-bus master should only capture the SDA line at such a moment that the improper

acknowledge pulse will not be detected.

Fig.8 Improper acknowledge generated by the DAPIC.

handbook, full pagewidth

MGK425

data output
from DAPIC

SCL from
master

START condition

data output
from transmitter

390 ns (typ)

non-DAPIC device address

improper acknowledge
generated by DAPIC

1997 May 30

Philips Semiconductors

Product specification

Digital Audio Processing IC (DAPIC)

SAA7740H

DRAM interface

The DRAM interface contains a nibble wide data bus, a
9-bit wide address bus and all necessary control signals to
enable the different DRAM configurations.

Timing of the control signals RAS, CAS, CAS2, A8B, OE
and WE is related to the applied clock frequency of the
DAPIC. The important timing parameters are the page
mode cycle time (t

cy;CAS

), the access time (t

acc;RAS

), the

refreshing rate and the maximum value for RAS to CAS
delay time (t

dRAS;CAS

) (see Chapter "Timing

characteristics" and Fig.10). A read/write operation will
always be executed in the page mode (one row address
and four column addresses) because every data transfer
consists of 4 nibbles.

The refresh time of the DRAM (t

rfsh

) must be greater than;

where `addr' is the number of physical address lines and
f

is measured in kHz.

rfsh

addr

-------------

For fast DRAMs, the maximum value for RAS to CAS
delay time (t

dRAS;CAS

) is important.

Different DRAM combinations can be connected to the
DAPIC. The smallest DRAM is a 64

4-bit (256 kbits)

RAM. For this configuration, 16K data words can be
stored. When this RAM is connected to the DAPIC, the
MSB address signal (A8) can be felt floating.

The DAPIC can address up to 1 Mbit DRAMs. However,
RAMs greater than 1 Mbit can also be connected. This,
therefore, implies that the redundant address lines of the
RAM must be fixed to V

or V

or must be joined with

one of the other address pins.

The choice of a 256 kbit or a 1 Mbit DRAM device must be
indicated by a flag bit residing in the start address control
word of the different delay lines.

1997 May 30

Philips Semiconductors

Product specification

Digital Audio Processing IC (DAPIC)

SAA7740H

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. Human body model: C = 100 pF; R = 1.5 k

2. Machine model: C = 200 pF; L = 2.5

H; R = 0

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

DC supply voltage
(each supply pin)

0.5

+6.5

voltage difference between V

and V

DDX

550

DC input clamp diode current

< -

0.5 V or V

> V

+ 0.5 V

DC output clamp diode current
(output type 4 mA)

0.5 V or

> V

+ 0.5 V

DC output sink or source
current (output type 4 mA)

0.5 < V

< V

+ 0.5 V

DC supply current per pin

LTCH

latch-up protection

CIC specification/test method

100

power dissipation per output

100

tot

total power dissipation

stg

storage temperature

+150

amb

operating ambient temperature

+85

electrostatic discharge

note 1

3000

+3000

note 2

300

+300

SYMBOL

PARAMETER

VALUE

UNIT

th j-a

thermal resistance from junction to ambient in free air

K/W

1997 May 30

Philips Semiconductors

Product specification

Digital Audio Processing IC (DAPIC)

SAA7740H

DC CHARACTERISTICS

4.5 to 5.5 V; T

amb

= -

40 to +85

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

DDn

DC supply voltage (pins 7, 8,
26, 32, 38, 53, 54 and 60)

4.5

5.0

5.5

DD(tot)

total of all DC supply current
pins

xtal

= 16.9344 MHz

tot

total power dissipation

xtal

= 16.9344 MHz

300

HIGH level input voltage
(pins 1, 3, 4, 11, 12, 15, 16,
36, 37, 41 to 45, 47 to 49, 51,
52, 62 and 64)

0.7V

LOW level input voltage
(pins 1, 3, 4, 11, 12, 15, 16,
36, 37, 41 to 45, 47 to 49, 51,
52, 62 and 64)

0.3V

th(pos)

Schmitt trigger positive-going
threshold (pin 2)

0.8V

th(neg)

Schmitt trigger negative-going
threshold (pin 2)

0.2V

hys

hysteresis voltage (pin 2)

0.33V

HIGH level output voltage
(pins 10 to 12, 14 to 24, 27 to
31, 33 to 35 and 63)

= 4.5 V; I

= 4 mA

4.0

LOW level output voltage
(pins 3, 10 to 12, 14 to 24, 27
to 31, 33 to 35 and 63)

= 4.5 V; I

= 4 mA

0.5

input leakage current
(pins 1, 2, 4, 36, 37, 41 to 45,
47 to 49, 51, 52 and 62)

= 0 or 5.5 V

output leakage current; 3-state
(pins 3, 11, 12, 15 and 16)

= 0 or 5.5 V

internal pull-down resistance
to V

(pin 64)

= V

134

r(i)

input rise time

= 5.5 V

200

f(i)

input fall time

= 5.5 V

200

r(o)

output rise time for
LOW-to-HIGH transition

= 4.5 V; T

amb

= 85

= pF; pins 11, 12, 15 and 16

9.5 + 0.4C

= 4.5 V; T

amb

= 85

= pF; pins 10, 14, 17 to 24,

27 to 31, 33 to 35 and 63

8.5 + 0.4C

f(o)

output fall time for
HIGH-to-LOW transition

= 4.5 V; T

amb

= 85

= pF; pins 11, 12, 15 and 16

11 + 0.5C

= 4.5 V; T

amb

= 85

= pF; pins 10, 14, 17 to 24,

27 to 31, 33 to 35 and 63

9.0 + 0.5C

1997 May 30

Philips Semiconductors

Product specification

Digital Audio Processing IC (DAPIC)

SAA7740H

AC CHARACTERISTICS

DDX

= 5 V; T

amb

= +25

C; unless otherwise specified.

TIMING CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

xtal

crystal input frequency

384f

12.288

16.9344

23.0

MHz

spurious frequency
attenuation

crystal current output
(pin 59)

slave mode only

transconductance at
maximum current

0.4

xtal

voltage across crystal

500

load capacitance

clk

half clock period of
external clock

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

pulse width HIGH, DIBCK and DOBCK

110

pulse width LOW, DIBCK and DOBCK

110

DIBCK and DOBCK rise time

DIBCK and DOBCK fall time

DIWS and DOWS hold time

su1

DIWS and DOWS set-up time

DI1D and DI2D hold time

su2

DI1D and DI2D set-up time

acc

DO1D and DO2D access time

25 + 0.5C

in pF)

DRAM timing

clk

half clock period

p;RAS

RAS precharge time

clk

W;RAS

RAS pulse width

clk

su;RA

row address set-up time

clk

h;RA

row address hold time

clk

dRAS;CAS

RAS to CAS delay time

clk

h;CAS

CAS hold time

clk

h;RAS

RAS hold time

clk

RAS;CA

RAS to column address

clk

+ 8

hCA;RAS

column address hold time from RAS

clk

hCA;RASp

column address hold time from RAS precharge

clk

lCA;RAS

column address to RAS lead time

clk

pCAS;RAS

CAS to RAS precharge time

clk

su;CA

column address set-up time

clk

1997 May 30

Philips Semiconductors

Product specification

Digital Audio Processing IC (DAPIC)

SAA7740H

h1CA;CAS

column address hold time to CAS

clk

h2CA;CAS

column address hold time to CAS precharge

clk

W;CAS

CAS pulse width

clk

p;CAS

CAS precharge time

clk

cy;CAS

CAS page mode cycle time

clk

acc;CA

access time from column address

clk

acc;CAS

access time from CAS

clk

acc;RAS

access time from RAS

clk

hDAT;CAS

data hold time from CAS

rcy;def

read cycle definition time

clk

su;DAT

data input set-up time

clk

h;DAT

data input hold time

clk

hDAT;RAS

data input hold time from RAS

clk

wcy;def

write cycle definition time

clk

off

output data disable time

clk

+ 8

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

Fig.9 I

S-bus timing diagram.

handbook, full pagewidth

MLC157

DATA IN

DATA OUT

t acc

t h2

t su2

t h1

t su1

t HC

t LC

1997 May 30

Philips Semiconductors

Product specification

Digital Audio Processing IC (DAPIC)

SAA7740H

S-BUS PROTOCOL

The I

S-bus digital interface is used for communication to

external digital sources. It is a 3-line serial bus with one
line each for data, clock and word select. Figure 11
illustrates an excerpt from the Philips I

S-bus specification

interface report with respect to general timing and format
of the bus. Word select (WS) at logic 0 signifies the left
channel and logic 1 the right channel.

The serial data is transmitted in two's complement with
MSB first. One clock period after the negative edge of the
WS line, the MSB of the left channel is transmitted. Data is
synchronized on the negative edge of the clock and
latched on the positive edge.

Two data line have been implemented as input from an
external processor for the four audio channels. Because of
this configuration the DAPIC operates in the following
manner.

The I

S-bus input block reads 4 samples (left and right

samples of the front and rear channel) and stores the
information into the register file. The operators read from
the register file, process the data and store the
intermediate results back into the register file. If a delay
line is required, the external RAM will need to be
accessed. The output samples are read from the register
file and are passed via the fade unit to the I

S-bus output

block. The same operation is repeated for each incoming
audio sample.

Fig.11 I

S-bus timing format.

handbook, full pagewidth

MLC159

SCK

MSB

LEFT

MSB

RIGHT

tHC

t LC

thr

t sr

VIH

VIL

VIH
VIL

1997 May 30

Philips Semiconductors

Product specification

Digital Audio Processing IC (DAPIC)

SAA7740H

C-BUS PROTOCOL

The I

C-bus is intended for 2-way, 2-line communication

between different ICs or modules. The two lines are the
serial data line (SDA) and the serial clock line (SCL). Both
lines must be connected to the supply rail via a pull-up
resistor when connected to the output stages of a
microcontroller. Data transfer can only be initiated when
the bus is not busy. Full details of the I

C-bus are given in

the document

"The I

C-bus and how to use it". This

document may be ordered using the code
9398 393 40011.

Bit transfer

One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulses as changes in the data line
at this time will be interpreted as control signals.
The maximum clock frequency is 100 kHz (see Fig.12).

START and STOP condition

In the START and STOP condition the data and clock lines
remain HIGH when the bus is not busy. A HIGH-to-LOW
transition on the data line, while the clock is HIGH, is
defined as the START condition (S). A LOW-to-HIGH
transition on the data line, while the clock is HIGH, is
defined as the STOP condition (P); (see Fig.13).

Data transfer

A device generating a message is a `transmitter', a device
receiving a message is a `receiver'. The device that
controls the message is the `master' and the devices which
are controlled by the device are the `slaves' (see Fig.14).

Acknowledge

The number of data bytes that are transferred between the
START and STOP conditions, from transmitter to receiver,
is unlimited. Each byte is followed by an acknowledge bit.
The acknowledge bit is a HIGH level bit placed on the bus
by the transmitter, whereas the master generates an extra
acknowledge bit which is related to the clock pulse. A slave
receiver which is addressed must generate an
acknowledge bit after the reception of each byte.
The master must also generate an acknowledge bit after
the reception of each byte that has been clocked out of the
slave transmitter.

The device that acknowledges has to pull down the SDA
line during the acknowledge clock pulse so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse. Set-up and hold times
must also be taken into account. A master receiver must
signal an end-of-data to the transmitter. This is achieved
by not generating an acknowledge on the last byte that has
been clocked out of the slave. In this condition the
transmitter must leave the data line HIGH to enable the
master to generate a STOP condition (see Fig.15).

Fig.12 Bit transfer on the I

C bus.

handbook, full pagewidth

MLC160

SDA

SCL

data line

stable

data valid

change

of data

allowed

1997 May 30

Philips Semiconductors

Product specification

Digital Audio Processing IC (DAPIC)

SAA7740H

APPLICATION INFORMATION

Clock circuit and oscillator

The clock generation of the SAA7740H is designed to
accommodate two main modes, the master and the slave.

In the master mode, the DAPIC is the master in the
system. The clock is generated by connecting a crystal to
the oscillator pins CLK1/XTAL1 and XTAL2 (see Fig.16).

In the slave mode, the DAPIC is supplied as a slave.
The external clock should be connected to the oscillator at
pin CLK1/XTAL1 (see Fig.17).

Crystal oscillator supply

The power supply for the oscillator is separate from the
other supply line. This is to minimize feedback from the
ground bounce of the IC to the oscillator. Pin V

SSX

is the

ground supply and V

DDX

is the positive supply.

Power supply connection and EMC

The SAA7740H has in total 8 positive supply lines (V

)

including V

DDX

, and 8 ground supply lines (V

) including

SSX.

For correct current distribution all positive supply

lines should be connected together on the printed
circuit-board. The ground supply lines should also be
connected together on the printed circuit-board.

To minimize radiation the IC should be placed on a
double-layer printed circuit-board with a large ground
plane on one side. The ground supply lines should have a
short connection to the ground plane. An LC network in the
positive supply lines can be used as a high frequency filter.

Test mode connections

Pins SCCLK, TSTCLK, TST1, TST2 and TST3 are used to
put the IC in the test mode and to test the internal
connections. In the application these pins must be
connected to ground.

Fig.16 Master mode.

handbook, halfpage

MLC164

CLK1/XTAL1

XTAL2

10 pF

100

Fig.17 Slave mode.

handbook, halfpage

MLC165

CLK1/XTAL1

XTAL2

max 1 V (p-p)

external

clock

10 pF

30 pF

100

10
nF

1997 May 30

Philips Semiconductors

Product specification

Digital Audio Processing IC (DAPIC)

SAA7740H

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

"Quality

Reference Handbook" (order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45

Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

The footprint must be at an angle of 45

to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

1997 May 30

Philips Semiconductors

Product specification

Digital Audio Processing IC (DAPIC)

SAA7740H

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors a worldwide company

SCA54

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Tel. +353 1 7640 000, Fax. +353 1 7640 200

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Printed in The Netherlands

547027/1200/04/pp28

Date of release: 1997 May 30

Document order number:

9397 750 02262

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAA7740H

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SAA7740H