DATA SHEET
Preliminary specification
File under Integrated Circuits, IC02
February 1995
INTEGRATED CIRCUITS
Philips Semiconductors
SAB9075H
Picture-in-Picture (PIP) controller
for NTSC
February 1995
2
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
FEATURES
Display
One or two live pictures can be displayed
simultaneously
Wide range of multi-Picture-In-Picture (PIP) modes
available
Six 6-bit Analog-to-Digital Converters (ADC) with
clamping circuit
Enhanced vertical resolution at most modes for live
pictures
Two Phase-Locked-Loops (PLL) with Voltage
Controlled Oscillator (VCO) to generate the line-locked
clocks
Three 7-bit Digital-to-Analog Converters (DAC)
4 : 1 : 1 data format
Data reduction factors 1 to 4, 1 to 9 and 1 to 16.
I
2
C-bus programmable
Different single, double and multi-PIP modes can be set
Several aspect ratios can be handled
Reduction factors can be set automatically and
manually
Selection of vertical filtering type
Freeze of live pictures
Single-PIP display position, four corners on-screen
Multi-PIP display position, left or right on-screen
Fine tuned display position, H (6-bit), V (6-bit)
Fine tuned acquisition area, H (4-bit), V (4-bit)
Channel-border and live PIP selectable
Eight main-border, sub-border, channel-border and
background colours selectable
Border and background brightness adjustable, 30%,
50%, 70% and 100% IRE
Several types of decoder input signals can be set
6-bit HUE and SAT signals (0 to 5 V) adjustable by
I
2
C-bus
Main and sub-audio mute controllable by I
2
C-bus.
GENERAL DESCRIPTION
The SAB9075H is a picture-in-picture controller for the
NTSC environment in combination with the Integrated
NTSC decoder and sync processor TDA8315.
The device inserts one or two live video channels with
reduced sizes into a live video signal. All video signals are
expected to be analog baseband signals. The conversion
into the digital environment and back to the analog
environment is carried out on-chip. Internal clocks are
generated by two PLLs.
Due to the two PIP channels and a large external memory,
a wide range of PIP modes are offered. The emphasis is
put on double-PIP and multi-PIP modes. In combination
with the different border colours and some external
software the IC concept can be used as an excellent
channel selection tool.
Some of the I
2
C-bus registers are for controlling the
saturation and HUE of the colours. There are also outputs
for the mute function of main and sub-channel.
February 1995
3
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
ORDERING INFORMATION
Note
1. When using IR reflow soldering it is recommended that the Drypack instructions in the
"Quality Reference Handbook"
(order number 9398 510 63011) are followed.
QUICK REFERENCE DATA
Notes
1. Digital clocks are silent and analog bias current is zero.
2. The internal system frequencies are 1728 times the input frequency. For more detailed information about the clock
generation see Section "PLLs and clock generation".
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
SAB9075H QFP100
(1)
plastic quad flat package; 100 leads (lead length 1.95 mm);
body 14
20
2.8 mm
SOT317-2
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DD
supply voltage
all positive supply pins
4.5
5.0
5.5
V
I
tot
total supply current
note 1
tbf
220
tbf
mA
f
sys
system frequency
note 2
-
27
30
MHz
f
loop
loop bandwidth frequency
4
-
-
kHz
t
jitter
short term stability time
jitter during 1 line (64
s)
-
-
4
ns
damping factor
-
0.7
-
-
February 1995
4
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
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BLOCK DIAGRAM
d
book, full pagewidth
MBE084
D/A CONVERTER
AND BUFFER
18
DY
14
DU
16
DV
19
DAIbias
13
DAVrefTU
15
DAVrefTV
17
DAVrefTY
11
10
20
21
DDA
SSA
DDD
DAV
DAV
DAV
DAV
SSD
27
29,31,35,33
26,25,30,28
48 to 56
AD0 to 8
DAI0 to 7
DAO0 to 7
SC
47
45
44
32
36,39,40,38
41,46,37,34
DT
WE
CAS
RAS
72
73
9
8
MVDDD
MVSSD
SV DDD
SV SSD
82
81
89
90
SAVDDA
SAVSSA
SAVDDD
SAVSSD
99
100
92
91
MAVDDA
MAVSSA
MAVDDD
MAVSSD
MEMORY
CONTROL
24
DBF
SAB9075H
94
MY
96
MV
93
MAI bias
97
MAVrefT
95
MAVrefB
98
MU
83
SY
85
SV
88
SAI bias
86
SAVrefT
84
SAVrefB
87
SU
70
69
SAT
67
MMUTE
68
SMUTE
HUE
CLAMP AND
A/D CONVERTER
ACQUISITION
MAIN
CLAMP AND
A/D CONVERTER
ACQUISITION
SUB
HUE AND SAT
D/A CONVERTERS
VDD
22
42
43
DISPLAY
DISPLAY TIMING CONTROL
AND PLL BLOCK
65
SCL
66
SDA
63
POR
64
A0
75
6
58
61
TM2
60
59
TM0
TC
TM1
MTCLK
STCLK
MVsync
SVsync
SPVDDD
VDDD
V SSS
71
23
74
SPVSSA
SPVDDA
79
SH sync
78
SPVSSD
76
80
SPI bias
77
MH sync
MPI bias
MPVSSD
MPVDDD
3
4
5
7
MPVSSA
MPV DDA
2
1
I C-BUS
2
I C
2
Fig.1 Block diagram.
February 1995
5
Philips Semiconductors
Preliminary specification
Picture-in-Picture (PIP) controller for NTSC
SAB9075H
PINNING
SYMBOL
PIN
I/O
TYPE
DESCRIPTION
MPV
DDA
1
I/O
E030
analog positive power supply for PLL main-channel
MPV
SSA
2
I/O
E009
analog negative power supply for PLL main-channel
MH
sync
3
I
E027
horizontal synchronization for main-channel
MPI
bias
4
I
E027
analog bias reference current for PLL main-channel
MPV
SSD
5
I/O
E009
digital negative power supply for PLL main-channel
MTCLK
6
I
HPP01
test clock for main-channel
MPV
DDD
7
I/O
E030
digital positive power supply for PLL main-channel
MV
DDD
8
I/O
E030
digital positive power supply for main-channel core
MV
SSD
9
I/O
E009
digital negative power supply for main-channel core
DAV
DDD
10
I/O
E030
digital positive power supply for DACs
DAV
SSD
11
I/O
E009
digital negative power supply for DACs
n.c.
12
-
-
not connected
DAV
refTU
13
I/O
E027
analog reference voltage for top U DAC
DU
14
O
E027
analog U output
DAV
refTV
15
I/O
E027
analog reference voltage for top V DAC
DV
16
O
E027
analog V output
DAV
refTY
17
I/O
E027
analog reference voltage for top Y DAC
DY
18
O
E027
analog Y output
DAI
bias
19
I
E027
analog bias reference current for DACs
DAV
SSA
20
I/O
E009
analog negative power supply for DACs
DAV
DDA
21
I/O
E030
analog positive power supply for DACs
I
2
CV
DD
22
I/O
E030
positive supply for HUE and SAT decoders
MV
sync
23
I
HPP01
vertical synchronization for main-channel
DBF
24
O
SPF20
fast blanking control output signal
DAI5
25
I
HPP01
data bus input from memory; bit 5
DAI4
26
I
HPP01
data bus input from memory; bit 4
SC
27
O
OPF20
memory shift clock
DAI7
28
I
HPP01
data bus input from memory; bit 7
DAI0
29
I
HPP01
data bus input from memory; bit 0
DAI6
30
I
HPP01
data bus input from memory; bit 6
DAI1
31
I
HPP01
data bus input from memory; bit 1
DT
32
O
OPF20
memory data transfer; active LOW
DAI3
33
I
HPP01
data bus input from memory; bit 3
DAO7
34
O
OPF20
data bus output to memory; bit 7
DAI2
35
I
HPP01
data bus input from memory; bit 2
DAO0
36
O
OPF20
data bus output to memory; bit 0
DAO6
37
O
OPF20
data bus output to memory; bit 6
DAO3
38
O
OPF20
data bus output to memory; bit 3
DAO1
39
O
OPF20
data bus output to memory; bit 1
DAO2
40
O
OPF20
data bus output to memory; bit 2
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