Philips Semiconductors

Product specification

SC26C562

CMOS dual universal serial communications controller
(CDUSCC)

1998 Sep 04

853-1663 19973

DESCRIPTION

The Philips Semiconductors SC26C562 Dual Universal Serial
Communications Controller (CDUSCC) is a single-chip CMOS-LSI
communications device that provides two independent,
multi-protocol, full-duplex receiver/transmitter channels in a single
package. It supports bit-oriented and character-oriented (byte count
and byte control) synchronous data link controls as well as
asynchronous protocols. The SC26C562 interfaces to synchronous
bus MPUs and is capable of program-polled, interrupt driven,
block-move or DMA data transfers.

The SC26C562 (CDUSCC) is (PIN) hardware and (REGISTER)
software compatible with the existing SCN26562 (DUSCC).
CDUSCC will automatically configure to the NMOS DUSCC register
map (default mode) on power up.

The operating mode and data format of each channel can be
programmed independently. Each channel consists of a receiver, a
transmitter, a 16-bit multifunction counter/timer, a digital
phase-locked loop (DPLL), a parity/CRC generator and checker, and
associated control circuits. The two channels share a common bit
rate generator (BRG), operating directly from a crystal or an external
clock, which provides sixteen common bit rates simultaneously. The
operating rate for the receiver and transmitter of each channel can
be independently selected from the BRG, the DPLL, the
counter/timer, or from an external 1X or 16X clock, making the
CDUSCC well-suited for dual-speed channel applications. Data
rates up to 10Mbits per second are supported.

The transmitter and receiver each contain a sixteen-deep FIFO with
appended transmitter command and receiver status bits and a shift
register. This permits reading and writing of up to sixteen characters
at a time, minimizing the potential of receiver overrun or transmitter
underrun, and reducing interrupt or DMA overhead. In addition, a
flow control capability is provided to disable a remote transmitter
when the FIFO of the local receiving device is full.

Two modem control inputs (DCD and CTS) and three modem
control outputs (RTS and two general purpose) are provided.
Because the modem control inputs and outputs are general purpose
in nature, they can be optionally programmed for other functions.

The SC26C562 CDUSCC is optimized to interface with processors
using a synchronous bus interface, such as the 8086, and iAPX86
family. For systems using an asynchronous bus, such as the 68000
and 68010, refer to the SC68C562 documentation.

Refer to the CMOS Dual Universal Serial Communication Controller
(CDUSCC) User's Manual for a complete operational description.

FEATURES

General Features

Dual full-duplex synchronous/ asynchronous receiver and
transmitter

Multi-protocol operation

BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,

etc.

COP: Single SYNC, dual SYNC, BiSYNC, DDCMP

ASYNC: 5-8 bits plus optional parity

Sixteen character receive and transmit FIFOs with interrupt
threshold control

FIFO'ed status bits

Watchdog timer

0 to 10 Mbit/sec data rate

Programmable bit rate for each receiver and transmitter selectable
from:

19 fixed rates: 50 to 64K baud

One user-defined rate derived from programmable

counter/timer

External 1X or 16X clock

Digital phase-locked loop

Parity and FCS (frame check sequence LRC or CRC) generation
and checking

Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,
Manchester

Programmable channel mode: full- or half-duplex, auto-echo, or
local loopback

Programmable data transfer mode: polled, interrupt, DMA, wait

DMA interface

Compatible with Synchronous and Asynchronous bus DMA

controllers

Half- or full-duplex operation

Single or dual address data transfers

Automatic frame termination on counter/ timer terminal count or

DMA DONE (EOPN)

Transmit path clear status

High speed data bus interface: 160ns bus cycle

DPLL operation up to 312.5kHz with internal clock

Interrupt capabilities

Vector output (fixed or modified by status)

Individual interrupt enable bits

Programmable internal priorities

Maskable interrupt conditions

80XX/X compatible

Multi-function programmable 16-bit counter/timer

Bit rate generator

Event counter

Count received or transmitted characters

Delay generator

Automatic bit length measurement

Modem controls

RTS, CTS, DCD, and up to four general purpose I/O pins per

channel

CTS and DCD programmable auto-enables for Tx and Rx

Programmable interrupt on change of CTS or DCD

On-chip oscillator for crystal

TTL compatible

Single +5V power supply

Asynchronous Mode Features

Character length: 5 to 8 bits

Philips Semiconductors

Product specification

SC26C562

CMOS dual universal serial communications controller
(CDUSCC)

1998 Sep 04

Odd or even parity, no parity, or force parity

Up to two stop bits programmable in 1/16-bit increments

1X or 16X Rx and Tx clock factors

Parity, overrun and framing error detection

False start bit detection

Break generation with handshake for counting break characters

Detection of start and end of received break

Character compare with optional interrupt on match

Transmit and receive up to 10Mbps at 1x or 1Mbps at 16x data
rates

Bit-Oriented Protocol

Character length: 5 to 8 bits

Detection and transmission of residual character: 07 bits

Automatic switch to programmed character length for I field

Zero insertion and deletion

Optional opening PAD transmission

Detection and generation of FLAG, ABORT, and IDLE bit patterns

Transmit 7 or 8 bit ABORT

Detection and generation of shared (single) FLAG between
frames

Detection of overlapping (shared zero) FLAGs

Idle in MARK or FLAGs

Secondary address recognition including group and global
address

Single- or dual-octet secondary address

Extended address and control fields

Short frame rejection for receiver

Detection and notification of received end of message

CRC generation and checking

SDLC loop mode capability

Character-Oriented Protocols

Character length: 5 to 8 bits

Odd or even parity, no parity, or force parity

LRC or CRC generation and checking

Optional opening PAD transmission

One or two SYN characters

External sync capability

SYN detection and optional stripping

SYN or MARK line-fill or underrun

Idle in MARK or SYNs

Parity, FCS, overrun and underrun error detection

Optional SYNC exclusion from FCS

BISYNC features
EBCDIC or ASCII header, text and control messages

SYN, DLE stripping

EOM (end of message) detection and transmission

Auto transparency mode switching

Auto hunt after receipt of EOM sequence (with closing PAD

check after EOT or NAK)

Control character sequence detection for both transparent and

normal text

Parity generation for data and LRC characters

ORDERING INFORMATION

COMMERCIAL

INDUSTRIAL

DESCRIPTION

Serial Data Rate =

10Mbps Maximum

Serial Data Rate =

8Mbps Maximum

DWG #

48-Pin Plastic Dual In-Line Package (DIP)

SC26C562C1N

Not available

SOT240-1

52-Pin Plastic Leaded Chip Carrier (PLCC) Package

SC26C562C1A

SC26C562A8A

SOT238-3

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

RATING

UNIT

SYMBOL

PARAMETER

COMMERCIAL

INDUSTRIAL

UNIT

Operating ambient temperature

0 to +70

-40 to +85

STG

Storage temperature

-65 to +150

Voltage from V

to GND

0.5 to +7.0

Voltage from any pin to ground

0.5 to V

+0.5

0.5 to V

+0.5

Philips Semiconductors

Product specification

SC26C562

CMOS dual universal serial communications controller
(CDUSCC)

1998 Sep 04

PIN CONFIGURATIONS

IACKN

RTxDAKBN/

IRQN

RDYN

RTSBN/

TRxCB

RTxCB

DCDBN/

TxDAKBN/

RTxDRQBN/

TxDRQBN/

CTSBN/LCBN

RDN

RESETN

GND

CEN

EOPN

CTSAN/LCAN

TxDRQAN/

RTxDRQAN/

TxDAKAN/

TxDA

DCDAN/

RTxCA

TRxCA

RTSAN/

X1/CLK

RTxDAKAN/

VCC

N PACKAGE

GPI1BN

SYNOUTBN

SYNIBN

RxDB

TxDB

GPI2BN

GPO1BN

GPO2BN/RTSBN

WRN

GPO2AN/RTSAN

GPO1AN

GPI2AN

RxDA

SYNIAN

SYNOUTAN

GPI1AN

DIP

PIN FUNCTION PIN FUNCTION

IACKN

27 CEN

28 WRN

29 EOPN

30 D3

RTxDAKBN/

31 D2

GPI1BN

32 D1

IRQN

33 D0

34 NC

RDYN

35 CTSAN/LCAN

RTSBN/

36 TxDRQAN/

SYNOUTBN

GPO2AN/RTSAN

10 TRxCB

37 RTxDRQAN/

RTxCB

GPO1AN

12 DCDBN/

38 TxDAKAN/

SYNIBN

GPI2AN

13 NC

39 TxDA

14 RxDB

40 RxDA

15 TxDB

41 NC

16 TxDAKBN/

42 DCDAN/

GPI2BN

SYNIAN

17 RTxDRQBN/

43 RTxCA

GPO1BN

44 TRxCA

18 TxDRQBN/

45 RTSAN/

GPO2BN/RTSBN

SYNOUTAN

19 CTSBN/LCBN

46 X2

20 D7

47 X1/CLK

21 D6

48 RTxDAKAN/

22 D5

GPI1AN

23 D4

49 A6

24 RDN

50 A5

25 RESETN

51 A4

26 GND

52 VCC

PLCC

TOP VIEW

INDEX

CORNER

A PACKAGE

SD00203

Figure 1. Pin Configurations

Philips Semiconductors

Product specification

SC26C562

CMOS dual universal serial communications controller
(CDUSCC)

1998 Sep 04

BLOCK DIAGRAM

D0D7

RDYN

RDN

A1A6

CEN

RESETN

BUS

BUFFER

CHANNEL

MODE AND
TIMING A/B

DPLL CLK

MUX A/B

DPLLA/B

CTCRA/B

CTPRHA/B

CTPRLA/B

RxD A/B

TxD A/B

CONTROL

INTERNAL

BUS

BRG

COUNTER

TIMER A/B

C/T CLK

MUX A/B

CTHA/B

CTLA/B

TRANS CLK

MUX

TRANSMIT

A/B

TPRA/B

TTRA/B

TX SHIFT

REG

TRANSMIT

16 DEEP

FIFO

CRC

GENERATOR

SPEC CHAR

GEN LOGIC

RCVR CLK

MUX

RCVR

SHIFT REG

RECEIVER

16 DEEP

FIFO

CRC

ACCUM

RECEIVER

A/B

RPRA/B

RTRA/B

S1RA/B

S2RA/B

BISYNC

COMPARE

LOGIC

ADDRESS

DECODE

DMA

CONTROL

INTERFACE/
OPERATION

CONTROL

CCRA/B

PCRA/B

RSRA/B

TRSRA/B

ICTSRA/B

R/W

DECODE

GSR

CMR1A/B

CMR2A/B

OMRA/B

MPU

INTERFACE

WRN

RTxDRQAN/GPO1AN

DMA

INTERFACE

RTxDRQBN/GPO1BN

TxDRQAN/GPO2AN

TxDRQBN/GPO2BN

RTxDAKAN/GPI1AN

RTxDAKBN/GPI1BN

TxDAKAN/GPI2AN

TxDAKBN/GPI2BN

EOPN

TRxCA/B

SPECIAL

FUNCTION

PINS

RTxCA/B

CTSAN/LCAN

CTSBN/LCBN

DCDBN/SYNIBN

DCDAN/SYNIAN

RTSBN/SYNOUTBN

RTSAN/SYNOUTAN

INTERRUPT

CONTROL

ICRA/B

IERA/B

IVRM

IER1 A/B

IRQN

IACKN

X1/CLK

OSCILLATOR

CDUSCC

LOGIC

IER2 A/B

IER3 A/B

TRCR A/B

FTLR A/B

TRMR A/B

TELR

A/B

RFLR

A/B

A7 CONTROL

LOGIC

CID

SD00239

Figure 2. Block Diagram

Philips Semiconductors

Product specification

SC26C562

CMOS dual universal serial communications controller
(CDUSCC)

1998 Sep 04

PIN DESCRIPTION

MNEMONIC

PIN NO.

TYPE

NAME AND FUNCTION

MNEMONIC

DIP

PLCC

TYPE

NAME AND FUNCTION

A1A6

4-2,

47-45

4-2,

51-49

Address Lines: Active-high. Address inputs which specify which of the internal registers
is accessed for read/write operation.

D0D7

31-28,

21-18

33-30,

23-20

I/O

Bidirectional Data Bus: Active-high, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All
data, command and status transfers between the CPU and the CDUSCC take place over
this bus. The data bus is enabled when CSN and RDN, or CSN and WRRN are low during
interrupt acknowledge cycles and single address DMA acknowledge cycles.

RDN

Read Strobe: Active-low input. When active and CSN is also active, causes the content
of the addressed register to be present on the data bus. RDN is ignored unless CSN is
active.

WRN

Write Strobe: Active-low input. When active and CSN is also active, the content of the
data bus is loaded into the addressed register. The transfer occurs on the rising edge of
WRN. WRN is ignored unless CEN is active.

CSN

Chip Select: Active-low input. When active, data transfers between the CPU and the
CDUSCC are enabled on D0D7 as controlled by RDN or WRN and A1A6 inputs. When
CSN is high, the data lines are placed in the 3-State condition (except during interrupt
acknowledge cycles and single address DMA transfers).

RDYN

Ready: Active-low, open drain. Used to synchronize data transfers between the CPU and
the CDUSCC. It is valid only during read and write cycles where the CDUSCC is
configured in `wait on Rx', `wait on Tx' or `wait on Tx or Rx' modes, otherwise it is always
inactive. RDYN becomes active on the leading edge of RDN and WRN if the requested
operation cannot be performed (viz, no data in RxFIFO in the case of a read or no room in
the TxFIFO in the case of a write).

IRQN

Interrupt Request: Active-low, open-drain. This output is asserted upon occurrence of
any enabled interrupting condition. The CPU can read the general status register to
determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle
to cause the CDUSCC to output an interrupt vector on the data bus.

IACKN

Interrupt Acknowledge: Active-low. When IACKN is asserted, the CDUSCC responds
by either forcing the bus into high-impedance, placing a vector number, call instruction or
zero on the data bus. The vector number can be modified or unmodified by the status. If
no interrupt is pending, IACKN is ignored and the data bus placed in high-impedance.

X1/CLK

Crystal or External Clock: When using the crystal oscillator, the crystal is connected

between pins X1 and X2. If a crystal is not used, an external clock is supplied at this input.

This clock is used to drive the internal bit rate generator, as an optional input to the
counter/timer or DPLL, and to provide other required clocking signals. When a crystal is
used, a capacitor must be connected from this pin to ground.

Crystal 2: Connection for other side of crystal. When a crystal is used, a capacitor must
be connected from this pin to ground. If an external clock is used on X1, this pin should be
left floating.

RESETN

Master Reset: Active-low. A low on this pin resets the transmitters and receivers and
resets the registers shown in Table 1 of the CDUSCC Users' Guide. Reset is
asynchronous, i.e., no clock is required.

RxDA, RxDB

37, 12

40, 14

Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If
external receiver clock is specified for the channel, the input is sampled on the rising edge
of the clock.

TxDA, TxDB

36, 13

39, 15

Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted
first. This output is in the marking (high) condition when the transmitter is disabled or when
the channel is operating in local loopback mode. If external transmitter clock is specified
for the channel, the data is shifted on the falling edge of the clock.

RTxCA, RTxCB

39, 10

43, 11

I/O

Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to
supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply
the counter/timer output, the transmitter shift clock (1X), or the receiver sampling clock
(1X).

TRxCA, TRxCB

40, 9

44, 10

I/O

Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver,
transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer
output, the DPLL output, the transmitter shift clock (1X), the receiver sampling clock (1X),
the transmitter BRG clock (16X), The receiver BRG clock (16X), or the internal system
clock (X1

2).

Philips Semiconductors

Product specification

SC26C562

CMOS dual universal serial communications controller
(CDUSCC)

1998 Sep 04

PIN DESCRIPTION (Continued)

MNEMONIC

PIN NO.

TYPE

NAME AND FUNCTION

MNEMONIC

DIP

PLCC

TYPE

NAME AND FUNCTION

CTSA/BN,
LCA/BN

32, 17

35, 19

I/O

Channel A (B) Clear-to-Send Input or Loop Control Output: Active-low. The signal
can be programmed to act as an enable for the transmitter when not in loop mode. The
CDUSCC detects logic level transitions on this input and can be programmed to generate
an interrupt when a transition occurs. When operating in the BOP loop mode, this pin be-
comes a loop control output which is asserted and negated by CDUSCC commands. This
output provides the means of controlling external loop interface hardware to go on-line and
off-line without disturbing operation of the loop.

DCDA/BN,
SYNIA/BN

38, 11

42, 12

Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin is
programmable. As a DCD active-low input, it acts as an enable for the receiver or can be
used as a general purpose input. For the DCD function, the CDUSCC detects logic level
transitions on this pin and can be programmed to generate an interrupt when a transition
occurs. As an active-low external sync input, it is used in COP mode to obtain character
synchronization for the receiver without receipt of a SYN character. This mode can be
used in disc or tape controller applications or for the optional byte timing lead in X.21.

RTxDRQA/BN,
GPO1A/BN

34, 15

37, 17

Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose
Output: Active-low. For half-duplex DMA operation, this output indicates to the DMA
controller that one or more characters are available in the receiver FIFO (when the
receiver is enabled) or that the transmit FIFO is not full (when the transmitter is enabled).
For full-duplex DMA operation, this output indicates to the DMA controller that data is
available in the receiver FIFO. In non-DMA mode, this pin is a general purpose output that
can be asserted and negated under program control.

TxDRQA/BN,
GPO2A/BN,
RTSA/BN

33, 16

36, 18

Channel A (B) Transmitter DMA Service Request, General Purpose Output, or
Request-to-Send: Active-low. For full-duplex DMA operation, this output indicates to the
DMA controller that the transmit FIFO is not full and can accept more data. When not in
full-duplex DMA mode, this pin can be programmed as a general purpose or a
Request-to-Send output, which can be asserted and negated under program control.

RTxDAKA/BN,
GPI1A/BN

44, 5

48, 5

Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input:
Active-low. For half-duplex single address operation, this input indicates to the CDUSCC
that the DMA controller has acquired the bus and that the requested bus cycle (read
receiver FIFO when the receiver is enabled or load transmitter FIFO when the transmitter
is enabled) is beginning. For full-duplex single address DMA operation, this input indicates
to the CDUSCC that the DMA controller has acquired the bus and that the requested read
receiver FIFO bus cycle is beginning. Because the state of this input can be read under
program control, it can be used as a general purpose input when not in single address
DMA mode.

TxDAKA/BN,
GPI2A/BN

35, 14

38, 16

Channel A (B) Transmitter DMA Acknowledge or General Purpose Input: Active-low.
When the channel is programmed for full-duplex single address DMA operation, this input
is asserted to indicate to the CDUSCC that the DMA controller has acquired the bus and
that the requested load transmitter FIFO bus cycle is beginning. Because the state of this
input can be read under program control, it can be used as a general purpose input when
not in full-duplex single address DMA mode.

EOPN

I/O

Done (EOP): Active-low, open-drain. EOPN can be used and is active in both DMA and
non-DMA modes. As an input, EOPN indicates the last DMA transfer cycle to the TxFIFO.
As an output, EOPN indicates either the last DMA transfer from the RxFIFO or that the
transmitted character count has reached terminal count.

RTSA/BN,
SYNOUTA/BN

41, 8

45, 9

Channel A (B) Sync Detect or Request-to-Send: Active-low. If programmed as a sync
output, it is asserted one bit time after the specified sync character (COP or BISYNC
modes) or a FLAG (BOP modes) is detected by the receiver. As a Request-to-Send
modem control signal, it functions as described previously for the TxDRQN/RTSN pin.

34, 52

+5V Power Input

GND

26, 13,

41, 7

Signal and Power Ground Input

Philips Semiconductors

Product specification

SC26C562

CMOS dual universal serial communications controller
(CDUSCC)

1998 Sep 04

DC ELECTRICAL CHARACTERISTICS

4,5

= 0

C to +70

C, V

= 5.0V +10%

4,5

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

Min

Typ

Max

UNIT

Input low voltage:

All except X1/CLK

0.8

X1/CLK

0.8

Input high voltage except X1/CLK

0 to 70

2.0

40 to +85

2.3

X1/CLK

0.8 x V

Output low voltage:
All except IRQN

=5.3mA(Comm), 4.8mA(Ind)

IRQN

=8.8mA(Comm), 7.8mA(Ind)

0.5

Output high voltage:

0.5

(Except open drain outputs)

= 400

0.5

ILX1

X1/CLK input low current

= 0, X2 = open

150

0.0

IHX1

X1/CLK input high current

= V

, X2 = GND

150

SCX2

X2 short circuit current

X1 = open, V

= 0

= V

15
+15

mA
mA

Input low current

RESETN, TxDAKN, RxDAKN

= 0

0.5

Input leakage current

= 0 to V

CC,

0 to 70

40 to +85

+10

OZH

Output off current high, 3-State data bus

= V

CC,

0 to 70

40 to +85

+10

OZL

Output off current low, 3-State data bus

= 0

0 to 70

40 to +85

ODL

Open drain output low current in off
state: EOPN,

RDYN

0.5

IRQN

= 0

ODH

Open drain output high current in off
state:

EOPN, IRQN, RDYN

= V

Power supply current
(see Figure 19 for graphs)

0 to 70

40 to +85

80
95

Input capacitance

= GND = 0

OUT

Output capacitance

= GND = 0

I/O

Input/output capacitance

= GND = 0

NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not
implied.

2. Clock may be stopped (DC) for testing purposes, or when CDUSCC is in non-operational modes.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

4. Parameters are valid over specified temperature range.
5. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.2V and 3.0V with a transi-

tion time of 20ns maximum. For X1/CLK, this swing is between 0.2V and 4.4V. All time measurements are referenced at input voltages of
0.2V and 3.0V and output voltages of 0.8V and 2.0V, as appropriate.

6. See Figure 20 for test conditions for outputs.
7. Tests for open drain outputs are intended to guarantee switching of the output transistor. Measurement of this response is referenced from

midpoint of the switching signal to a point 0.2V above the actual output signal level. This point represents noise margin that assures true
switching has occurred.

8. Execution of the valid command (after it is latched) requires 3 rising edges of X1 (see Figure 15).
9. These values were not explicitly tested; they are guaranteed by design and characterization data.
10. X1/CLK and X2 are not tested with a crystal installed.
11. X1/CLK frequency must be at least the faster of the receiver or transmitter serial data rate.
12. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CSN as the `strobing' input. CSN

and RDN (also CSN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle.

13. V

= 0 to V

, Rx and Tx clocks at 10MHz, X1 clock at 10MHz.

Philips Semiconductors

Product specification

SC26C562

CMOS dual universal serial communications controller
(CDUSCC)

1998 Sep 04

AC ELECTRICAL CHARACTERISTICS

4,5,6,7

= 0

C to +70

C, 40 to +85

C, V

= 5V

10%

tRELREH

RESETN

SD00205

Figure 3. Reset Timing

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC26C562

COMMERCIAL SC26C562

UNIT

Min

Max

Min

Max

RELREH

RESETN low to RESETN high

200

A6A1

tADVRDL

CSN (CEN)

tCEHCEL

tCELRDL

RDN

tRDHCEH

tRDLADI

tRDLRDH

tRDHRDL

D0D7

tRDLDDV

tRDHDDF

tRDHDDI

RDYN

tRDLRYL

tRYZDDV

NOTE:

Wait on Rx. Receiver FIFO empty.

tRDLDLZ

SD00240

Figure 4. Read Cycle

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC26C562

COMMERCIAL SC26C562

UNIT

Min

Max

Min

Max

ADVRDL

Address valid to RDN low

CELRDL

CEN low to RDN low

RDLADI

RDN low to address invalid

RDLRYL

RDN low to RDYN low

160

150

RDLDDV

RDN low to read data valid

150

130

RDLRDH

RDN low to RDN high

150

130

RYZDDV

RDYN high impedance to read data valid

RDHCEH

RDN high to CEN high

CEHCEL

CEN high to CEN low

RDHDDI

RDN high to read data invalid

RDHRDL

RDN high to RDN low

RDHDDF

RDN high to data bus floating

RDLDLZ

RDN low to data bus low impedance

Philips Semiconductors

Product specification

SC26C562

CMOS dual universal serial communications controller
(CDUSCC)

1998 Sep 04

AC ELECTRICAL CHARACTERISTICS (Continued)

A6A1

tADVWRL

CSN (CEN)

tCEHCEL

tCELWRL

WRN

tWRHCEH

tWRLADI

tWRLWRH

tWRHWRL

D0D7

tWDVWRH

tWRHWDI

RDYN

tWRLRYL

NOTE:

Wait on Tx. Transmitter FIFO full.

tRYHZWRH

SD00241

Figure 5. Write Cycle

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC26C562

COMMERCIAL SC26C562

UNIT

Min

Max

Min

Max

ADVWRL

Address valid to WRN low

CELWRL

CSN low to WRN low

WRLRYL

WRN low to RDYN low

WRHCEH

WRN high to CSN high

WRLWRH

WRN low to WRN high

110

100

WDVWRH

Write data valid to WRN high

160

150

CEHCEL

CEN high to CEN low

160

150

WRLADI

WRN low to address invalid

WRHWRL

WRN high to WRN low

WRHWDI

WRN high to write data invalid

RYHZWRH

RDYN hi impedance to WRN high

Philips Semiconductors

Product specification

SC26C562

CMOS dual universal serial communications controller
(CDUSCC)

1998 Sep 04

AC ELECTRICAL CHARACTERISTICS (Continued)

IRQN

Cleared

through

software

INTERRUPT REQUEST LOCKED

SERVICE

ROUTINE

VECTOR SETTLING

IACKN

VECTOR
LOCKED

tIALDDV

tIAHDDI

tIAHDDF

D7D0

NOTES:

ICR[5:4] = 01 or 10 (mode 1 or mode 2)

Call instruction (mode 2)

ICR[5:4] = 11 (mode 3)

SD00208

Figure 6. Interrupt Acknowledge Cycle

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC26C562

COMMERCIAL SC26C562

UNIT

Min

Max

Min

Max

IALDDV

IACKN low to data bus valid

IAHDDF

IACKN high to data bus floating

140

130

IAHDDI

IACKN high to data bus invalid

IALDLZ

IACKN low to data bus low impedance

IAHIAL

IACKN high to low

CEN

tWRHGOV

WRN

GPO1_N

AND/OR

GPO2_N

OLD DATA

NEW DATA

SD00209

Figure 7. Output Port Timing

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC26C562

COMMERCIAL SC26C562

UNIT

Min

Max

Min

Max

WRHGOV

WRN high to GPO output data valid

100

Philips Semiconductors

Product specification

SC26C562

CMOS dual universal serial communications controller
(CDUSCC)

1998 Sep 04

AC ELECTRICAL CHARACTERISTICS (Continued)

CSN (CEN)

tRDLGII

RDN

GPI1N

AND/OR

GPI2N

tGIVRDL

SD00242

Figure 8. Input Port Timing

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC26C562

COMMERCIAL SC26C562

UNIT

Min

Max

Min

Max

GIVRDL

GPI input valid to RDN low

RDLGII

RDN low to GPI input invalid

tCLHCLL
tCCHCCL
tRCHRCL
tTCHTCL

X1/CLK

CTCLK

RxC

TxC

tCLLCLH
tCCLCCH
tRCLRCH
tTCLTCH

DRIVING

FROM EXTERNAL

SOURCE

TTL

X2 OPEN WHEN

X1 IS DRIVEN

NOTE: CL1 AND CL2 VALUES DEPEND ON

CRYSTAL
MANUFACTURER'S REQUIREMENTS, AND SHOULD
INCLUDE CP1 AND CP2

TO
CDUSCC
CIRCUITS

CP1

CP2

SC26C562

50-150k

CP1 = 7-12pF
CP2 = 12-17pF

CL1

CL2

VCC

*Pull-up resistor is not required when using CMOS levels

470

SD00243

Figure 9. Clock Timing

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC26C562

COMMERCIAL SC26C562

UNIT

Min

Typ

Max

Min

Typ

Max

CLHCLL

X1/CLK high to low time

CLLCLH

X1/CLK low to high time

CCHCCL

C/T CLK high to low time

CCLCCH

C/T CLK low to high time

RCHRCL

RxC high to low time

RCLRCH

RxC low to high time

TCHTCL

TxC high to low time

TCLTCH

TxC low to high time

X1/CLK frequency

16.0

MHz

C/T CLK frequency

14.7456

MHz

RxC frequency (16X or 1X @ 50% duty cycle)

14.7456

MHz

TxC frequency (16X or 1X @ 50% duty cycle)

MHz

fRTC

Tx/Rx frequency for FM/Manchester encoding

MHz

Philips Semiconductors

Product specification

SC26C562

CMOS dual universal serial communications controller
(CDUSCC)

1998 Sep 04

AC ELECTRICAL CHARACTERISTICS (Continued)

1 BIT TIME

(1 OR 16 CLOCKS)

tCILTXV

tCOLTXV

TxC

(INPUT)

TxD

TxC

(1X OUTPUT)

tCILTXV

tCOLTXV

TxC

(INPUT)

TxD

TxC

(1X OUTPUT)

tCILTXV

tCOLTXV

a. Transmit Timing NRZ

b. Transmit Timing FM0/1, Manchester Encoding

SD00244

Figure 10.

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC26C562

COMMERCIAL SC26C562

UNIT

Min

Max

Min

Max

CILTXV

TxC input low (1X) to TxD output

120

CILTXV

TxC input low (16X) to TxD output

120

COLTXV

TxC output low to TxD output

(NRZ, NRZI)

COLTXV

FM, MAN

*Characterized with no loads on TxD and TxC outputs. Tester load is approximately 50pF.

tRCHSOL

tSILRCH

tRCHSIH

tRXVRCH

tRCHRXI

SYNOUTN

SYNIN

RXC (1X)

INPUT

RxD

tRXVRCH

RXC

(INPUT)

RxD

tRCHRXI

tRXVRCH

a. Receive Timing NRZ

b. Receive Timing FM0/1, Manchester Encoding

SD00245

Figure 11.

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC26C562

COMMERCIAL SC26C562

UNIT

Min

Max

Min

Max

RXVRCH

RxD data valid to RxC high:
For NRZ data

For NRZI, Manchester, FM0, FM1 data

RCHRXI

RxC high to RxD data invalid:
For NRZ data

For NRZI, Manchester, FM0, FM1 data

SILRCH

SYNIN low to RxC high

RCHSIH

RxC high to SYNIN high

RCHSOL

RxC high to SYNOUT low

110

100

Philips Semiconductors

Product specification

SC26C562

CMOS dual universal serial communications controller
(CDUSCC)

1998 Sep 04

AC ELECTRICAL CHARACTERISTICS (Continued)

tTALTRH

tTAHTAL

tTALTAH

tTAHEIH

tEILTAH

tTAHWDI

tWDVTAH

tTALEOL

tTAHEOF

EOPN

(OUTPUT)

NOTES:

Ignored by the CDUSCC since CEN is not asserted, but it can be used externally to qualify TxDAKN.

Memory read signal; not seen by CDUSCC.

TxRQN

TxDAKN

WRN

MEMRN

EOPN

(INPUT)

D7D0

SD00248

Figure 14. DMA-Transmit Single Address Mode

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC26C562

COMMERCIAL SC26C562

UNIT

Min

Max

Min

Max

TAHTAL

Transmit DMA ACKN high to low time

TALTAH

Transmit DMA ACKN low to high time

110

100

TALTRH

Tx DMA ACKN low to Tx DMA REQN high

WDVTAH

Write data valid to Tx DMA ACKN high

110

100

TAHWDI

Tx DMA ACKN high to write data invalid

TALEOL

Tx DMA ACKN low to EOPN output low

TAHEOF

Tx DMA ACKN high to EOPN output float

100

EILTAH

EOPN input low to Tx DMA ACKN high

TAHEIH

Tx DMA ACKN high to EOPN input high

Philips Semiconductors

Product specification

SC26C562

CMOS dual universal serial communications controller
(CDUSCC)

1998 Sep 04

AC ELECTRICAL CHARACTERISTICS (Continued)

NOTES:

Ignored by the CDUSCC bit; it can be used to qualify RxDAKN.

Memory read signal; not seen by CDUSCC.

tRALRRH

tRAHRAL

tRALRAH

tRAHDDI

tRALDDV

tRALEOL

tRAHEOF

EOPN

(OUTPUT)

RxDRQN

RxDAKN

RDN

MEMWN

D7D0

tRAHDDF

SD00249

Figure 15. DMA-Receive Single Address Mode

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC26C562

COMMERCIAL SC26C562

UNIT

Min

Max

Min

Max

RAHRAL

Receive DMA ACKN high to low time

RALRAH

Receive DMA ACKN low to high time

140

130

RALRRH

Rx DMA ACKN low to Rx DMA REQN high

100

RALEOL

Rx DMA ACKN low to EOPN output low

100

RAHEOF

Rx DMA ACKN high to EOPN output float

RALDDV

Rx DMA ACKN low to read data valid

140

130

RAHDDI

Rx DMA ACKN high to read data invalid

RAHDDF

Rx DMA ACKN high to data bus float

Philips Semiconductors

Product specification

SC26C562

CMOS dual universal serial communications controller
(CDUSCC)

1998 Sep 04

AC ELECTRICAL CHARACTERISTICS (Continued)

RDN/WRN

tRWHIRH

VOL +0.2V

VOL

IRQN

SD00218

Figure 16. Interrupt Timing

SYMBOL

PARAMETER

LIMITS

UNIT

SYMBOL

PARAMETER

INDUSTRIAL SC26C562

COMMERCIAL SC26C562

UNIT

SYMBOL

PARAMETER

Min

Max

Min

Max

UNIT

RDN/WRN high to IRQN high for:

Read RxFIFO (RxRDY interrupt)

100

Write TxFIFO (TxRDY interrupt)

100

RWHIRH

Write RSR (Rx condition interrupt)

100

Write TRSR (Rx/Tx interrupt)

100

Write ICTSR (counter/timer interrupt)

100

Write TRMSR (Tx Path, Patt. Det.)

100

X1/CLK

WRN

COMMAND

VALID

SD00219

Figure 17. Command Timing

RxC

RxD

LCN

a. Loop Control Output Assertion

b. Loop Control Output Negation

RxC

RxD

LCN

SD00220

Figure 18. Relationship Between Received Data and the Loop Control Output

Philips Semiconductors

Product specification

SC26C562

CMOS dual universal serial communications controller
(CSUSCC)

1998 Sep 04

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381

Date of release: 08-98

Document order number:

9397 750 04355

Philips

Semiconductors

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

[1]

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1]

Please consult the most recently issued datasheet before initiating or completing a design.

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