General description

The SSTU32865 is a 1.8 V 28-bit 1:2 register specifically designed for use on two rank by
four (2R

4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is

similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the
functionality of the normally required two registers in a single package, thereby freeing up
board real-estate and facilitating routing to accommodate high-density Dual In-line
Memory Module (DIMM) designs.

The SSTU32865 also integrates a parity function, which accepts a parity bit from the
memory controller, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active-LOW).

The SSTU32865 is packaged in a 160-ball, 12

18 grid, 0.65 mm ball pitch, thin profile

fine-pitch ball grid array (TFBGA) package, which--while requiring a minimum
9 mm

13 mm of board space--allows for adequate signal routing and escape using

conventional card technology.

Features

28-bit data register supporting DDR2

Fully compliant to JEDEC standard JESD82-9

Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two
JEDEC-standard DDR2 registers (i.e. 2

SSTU32864 or 2

SSTU32866)

Parity checking function across 22 input data bits

Parity out signal

Controlled output impedance drivers enable optimal signal integrity and speed

Exceeds JESD82-9 speed performance (1.8 ns max. single-bit switching propagation
delay, 2.0 ns max. mass-switching)

Supports up to 450 MHz clock frequency of operation

Optimized pinout for high-density DDR2 module design

Chip-selects minimize power consumption by gating data outputs from changing state

Supports Stub Series Terminated Logic SSTL_18 data inputs

Differential clock (CK and CK) inputs

Supports Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
switching levels on the control and RESET inputs

Single 1.8 V supply operation

Available in 160-ball 9 mm

13 mm, 0.65 mm ball pitch TFBGA package

SSTU32865

1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
applications

Rev. 02 -- 28 September 2004

Product data sheet

9397 750 13799

Product data sheet

Rev. 02 -- 28 September 2004

2 of 29

Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

Applications

High-density (e.g. 2 rank by 4) DDR2 registered DIMMs

DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality

Ordering information

Table 1:

Ordering information

Type number

Solder process

Package

Name

Description

Version

SSTU32865ET/G

Pb-free (SnAgCu solder ball
compound)

TFBGA160

plastic thin fine-pitch ball grid array package;
160 balls; body 9

0.8 mm

SOT802-1

SSTU32865ET

SnPb solder ball compound

TFBGA160

plastic thin fine-pitch ball grid array package;
160 balls; body 9

0.8 mm

SOT802-1

9397 750 13799

Product data sheet

Rev. 02 -- 28 September 2004

5 of 29

Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

160-ball, 12

18 grid; top view.

An empty cell indicates no ball is populated at that grid point.

n.c. denotes a no-connect (ball present but not connected to the die).

m.c.l. denotes a pin that must be connected LOW.

m.c.h. denotes a pin that must be connected HIGH.

Fig 3.

Ball mapping

VREF

n.c.

PARIN

n.c.

QCKE1A

n.c.

QCKE1B

VDDL

GND

n.c.

VDDL

GND

VDDL

D11

VDDL

GND

D18

D12

VDDL

GND

CSGATEEN

D15

VDDL

GND

DCS0

GND

DCS1

VDDL

D14

GND

D10

GND

D17

D16

VDDL

D19

D21

GND

VDDL

D13

D20

GND

VDDL

DODT1

DODT0

002aab011

QCKE0A

Q21A

Q19A

Q18A

Q17B

Q17A

QCKE0B

Q21B

Q19B

Q18B

QODT0B

QODT0A

QODT1B

QODT1A

n.c.

GND

Q20B

Q20A

VDDR

GND

Q16B

Q16A

VDDR

Q1B

Q1A

VDDR

Q2B

Q2A

GND

Q5B

Q5A

VDDR

QCS0B

QCS0A

GND

QCS1B

QCS1A

VDDR

Q6B

Q6A

GND

Q10B

Q10A

VDDR

Q9B

Q9A

VDDR

GND

Q11B

Q11A

GND

Q15B

Q15A

Q14B

Q14A

DCKE0

DCKE1

m.c.l.

PTYERR

m.c.h.

Q3B

VREF

m.c.l.

n.c.

m.c.h.

Q3A

Q12B

Q7B

Q4B

Q13B

Q0B

Q8B

Q12A

Q7A

Q4A

Q13A

Q0A

Q8A

RESET

9397 750 13799

Product data sheet

Rev. 02 -- 28 September 2004

6 of 29

Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

6.2 Pin description

Table 2:

Pin description

Symbol

Pin

Type

Description

Ungated inputs

DCKE0, DCKE1

U1, U2

SSTL_18

DRAM function pins not associated with Chip Select.

DODT0, DODT1

T2, T1

Chip Select gated inputs

D0 to D21

M1, B1, B2, C1, C2, D2, D1,
E1, E2, F2, M2, F1, G2, R1,
L2, H2, N2, N1, G1, P1, R2,
P2

SSTL_18

DRAM inputs, re-driven only when Chip Select is LOW.

Chip Select inputs

DCS0, DCS1

J2, K2

SSTL_18

DRAM Chip Select signals. These pins initiate DRAM
address/command decodes, and as such at least one will
be LOW when a valid address/command is present. The
register can be programmed to re-drive all D-inputs only
(CSGATEEN = HIGH) when at least one Chip Select
input is LOW.

Re-driven outputs

Q0A to Q21A

V11, F12, G12, V6, V9, H12,
L12, V8, V12, N12, M12,
P12, V7, V10, T12, R12,
E12, A12, A10, A9, D12, A8

SSTL_18

Outputs of the register, valid after the specified clock
count and immediately following a rising edge of the
clock.

Q0B to Q21B

U11, F11, G11, U6, U9,
H11, L11, U8, U12, N11,
M11, P11, U7, U10, T11,
R11, E11, A11, B10, B9,
D11, B8

QCS0A, QDS1A,
QCS0B, QCS1B

J12, K12, J11, K11

QCKE0A, QCKE1A,
QCKE0B, QCKE1B

A7, A6, B7, B6

QODT0A, QODT1A,
QODT0B, QODT1B

B12, C12, B11, C11

Parity input

PARIN

SSTL_18

Parity input for the D0 to D21 inputs. Arrives one clock
cycle after the corresponding data input.

Parity error

PTYERR

open drain

When LOW, this output indicates that a parity error was
identified associated with the address and/or command
inputs. PTYERR will be active for two clock cycles, and
delayed by an additional clock cycle for compatibility with
final parity out timing on the industry-standard DDR2
register with parity (in JEDEC definition).

Program inputs

CSGATEEN

1.8 V
LVCMOS

Chip Select Gate Enable. When HIGH, the D0 to D21
inputs will be latched only when at least one Chip Select
input is LOW during the rising edge of the clock. When
LOW, the D0 to D21 inputs will be latched and redriven
on every rising edge of the clock.

9397 750 13799

Product data sheet

Rev. 02 -- 28 September 2004

7 of 29

Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

Clock inputs

CK, CK

J1, K1

SSTL_18

Differential master clock input pair to the register. The
register operation is triggered by a rising edge on the
positive clock input (CK).

Miscellaneous inputs

m.c.l.

U3, V2, V3

Must be connected to a logic LOW

m.c.h.

U5, V5

Must be connected to a logic HIGH.

RESET

1.8 V
LVCMOS

Asynchronous reset input. When LOW, it causes a reset
of the internal latches, thereby forcing the outputs LOW.
RESET also resets the PTYERR signal.

VREF

A1, V1

0.9 V
nominal

Input reference voltage for the SSTL_18 inputs. Two pins
(internally tied together) are used for increased reliability.

VDDL

D4, E4, E6, F4, G4, H4, K4,
K5, N4, N5, P5, P6, R5, R6

power supply voltage

VDDR

E7, F8, F9, G8, G9, J8, J9,
L8, L9, N8, N9, P7, P8

power supply voltage

GND

D5, D8, D9, E5, E8, E9, F5,
G5, H5, H8, H9, J4, J5, K8,
K9, L4, L5, M4, M5, M8, M9,
P4, P9, R4, R7, R8, R9

ground

n.c.

A2, A4, A5, B3, B4, B5, D6,
D7, V4

ball present but not connected to die

Table 2:

Pin description

...continued

Symbol

Pin

Type

Description

9397 750 13799

Product data sheet

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8 of 29

Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

Functional description

7.1 Function table

[1]

is the previous state of the associated output.

[1]

PARIN arrives one clock cycle after the data to which it applies. All Dn inputs must be driven to a known state for parity to be calculated
correctly.

Table 3:

Function table (each flip-flop)

Inputs

Outputs

[1]

RESET

DCS0

DCS1

CSGATEEN

Dn, DODTn,

DCKEn

QCS0

QCS1

QODTn,

QCKEn

L or H

X or

floating

X or

floating

X or floating

X or

floating

X or

floating

X or floating

Table 4:

Parity and standby function table

Inputs

Output

RESET

DCS0

DCS1

of inputs = H

(D0 to D21)

PARIN

[1]

PTYERR

[2] [3]

even

odd

even

odd

even

odd

even

odd

PTYERR

L or H

PTYERR

X or floating

9397 750 13799

Product data sheet

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Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

[2]

This condition assumes PTYERR is HIGH at the crossing of CK going HIGH and CK going LOW. If PTYERR is LOW, it stays latched
LOW for two clock cycles or until RESET is driven LOW.

CSGATEEN is `don't care' for PTYERR.

[3]

PTYERR

is the previous state of output PTYERR.

7.2 Functional information

This 28-bit 1:2 registered buffer with parity is designed for 1.7 V to 1.9 V V

operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized
to drive the DDR2 DIMM load.

The SSTU32865 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.

The device supports low-power standby operation. When the reset input (RESET) is LOW,
the differential input receivers are disabled, and undriven (floating) data, clock and
reference voltage (V

REF

) inputs are allowed. In addition, when RESET is LOW all registers

are reset, and all outputs except PTYERR are forced LOW. The LVCMOS RESET input
must always be held at a valid logic HIGH or LOW level.

To ensure defined outputs from the register before a stable clock has been supplied,
RESET must be held in the LOW state during power-up.

In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with
respect to CK and CK. Therefore, no timing relationship can be guaranteed between the
two. When entering reset, the register will be cleared and the data outputs will be driven
LOW quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable
the differential input receivers. As long as the data inputs are LOW, and the clock is stable
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTU32865 ensures that the outputs remain LOW, thus
ensuring no glitches on the output.

The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from
changing states when both DCS0 and DCS1 are HIGH. If either DCS0 or DCS1 input is
LOW, the Qn outputs will function normally. The RESET input has priority over the DCS0
and DCS1 control and will force the Qn outputs LOW and the PTYERR output HIGH. If the
DCSn-control functionality is not desired, then the CSGATEEN input can be hardwired to
ground, in which case, the setup-time requirement for DCSn would be the same as for the
other Dn data inputs.

The SSTU32865 includes a parity checking function. The SSTU32865 accepts a parity bit
from the memory controller at its input pin PARIN, compares it with the data received on
the Dn inputs (with either DCS0 or DCS1 active) and indicates whether a parity error has
occurred on its open-drain PTYERR pin (active LOW).

9397 750 13799

Product data sheet

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Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

7.3 Functional differences to SSTU32864

The SSTU32865 for its basic register functionality, signal definition and performance is
based upon the industry-standard SSTU32864, but provides key operational features
which differ (at least in part) from the industry-standard register in the following aspects:

7.3.1 Chip Select (CS) gating of key inputs (DCS0, DCS1, CSGATEEN)

As a means to reduce device power, the internal latches will only be updated when one or
both of the CS inputs are active (LOW) and CSGATEEN HIGH at the rising edge of the
clock. The 22 `Chip-Select-gated' input signals associated with this function include
addresses (ADDR0 to ADDR15, BA0 to BA2), and RAS, CAS, WE, with the remaining
signals (CS, CKE, ODT) continuously re-driven at the rising edge of every clock as they
are independent of CS. The CS gating function can be disabled by tying CSGATEEN
LOW, enabling all internal latches to be updated on every rising edge of the clock.

7.3.2 Parity error checking and reporting

The SSTU32865 incorporates a parity function, whereby the signal received on input pin
PARIN is received as parity to the register, one clock cycle later than the CS-gated inputs.
The received parity bit is then compared to the parity calculated across these same inputs
by the register parity logic to verify that the information has not been corrupted. The 22
CS-gated input signals will be latched and re-driven on the first clock, and any error will be
reported one clock cycle later via the PTYERR output pin (driven LOW for two consecutive
clock cycles). PTYERR is an open-drain output, allowing multiple modules to share a
common signal pin for reporting the occurrence of a parity error during a valid command
cycle (coincident with the re-driven signals). This output is driven LOW for two consecutive
clock cycles to allow the memory controller sufficient time to sense and capture the error
even. A LOW state on PTYERR indicates that a parity error has occurred.

7.3.3 Reset (RESET)

Similar to the RESET pin on the industry-standard SSTU32864, this pin is used to clear all
internal latches and all outputs will be driven LOW quickly except the PTYERR output,
which will be floated (and will normally default HIGH by their external pull-up).

7.3.4 Power-up sequence

The reset function for the SSTU32865 is similar to that of the SSTU32864 except that the
PTYERR signal is also cleared and will be held clear (HIGH) for three consecutive clock
cycles.

Table 5:

Chip Select gating mode

Mode

Signal name

Description

Gating

CSGATEEN

HIGH

Registers only re-drive signals to the DRAMs when
Chip Select inputs are LOW.

Non-gating

CSGATEEN

LOW

Registers always re-drive signals on every clock cycle,
independent of the state of the Chip Select inputs.

9397 750 13799

Product data sheet

Rev. 02 -- 28 September 2004

15 of 29

Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

Limiting values

[1]

Stresses beyond those listed under `absolute maximum ratings' may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under `recommended operating
conditions' is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

[2]

The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

Recommended operating conditions

[1]

The differential inputs must not be floating, unless RESET is LOW.

[2]

The RESET input of the device must be held at valid logic levels (not floating) to ensure proper device operation.

Table 6:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

supply voltage

0.5

+2.5

receiver input voltage

[2]

0.5

+2.5

driver output voltage

[2]

0.5

+ 0.5

input clamp current

< 0 V or V

> V

output clamp current

< 0 V or V

> V

continuous output current

0 V < V

< V

CCC

continuous current through
each V

or GND pin

100

stg

storage temperature

+150

esd

electrostatic discharge
voltage

Human Body Model (HBM); 1.5 k

;

100 pF

Machine Model (MM); 0

; 200 pF

200

Table 7:

Recommended operating conditions

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

supply voltage

1.7

1.9

REF

reference voltage

0.49

0.50

0.51

termination voltage

REF

40 mV

REF

+ 40 mV

input voltage

IH(AC)

AC HIGH-level input voltage

data inputs (Dn)

[1]

REF

+ 250 mV

IL(AC)

AC LOW-level input voltage

data inputs (Dn)

[1]

REF

250 mV

IH(DC)

DC HIGH-level input voltage

data inputs (Dn)

[1]

REF

+ 125 mV

IL(DC)

DC LOW-level input voltage

data inputs (Dn)

[1]

REF

125 mV

HIGH-level input voltage

RESET

[2]

0.65

LOW-level input voltage

RESET

[2]

0.35

ICR

common mode input voltage
range

CK, CK

0.675

1.125

differential input voltage

CK, CK

600

HIGH-level output current

LOW-level output current

amb

operating ambient temperature
in free air

+70

9397 750 13799

Product data sheet

Rev. 02 -- 28 September 2004

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Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

10. Characteristics

Table 8:

Characteristics

Over recommended operating conditions, unless otherwise noted.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

HIGH-level output voltage

6 mA; V

= 1.7 V

1.2

LOW-level output voltage

= 6 mA; V

= 1.7 V

0.5

input current

all inputs; V

= V

or GND;

= 1.9 V

static standby current

RESET = GND; V

= 1.9 V

100

static operating current

RESET = V

; V

= 1.9 V;

= V

IH(AC)

or V

IL(AC)

DDD

dynamic operating current per MHz,
clock only

RESET = V

;

= V

IH(AC)

or V

IL(AC)

; CK and CK

switching at 50 % duty cycle.
I

= 0 mA; V

= 1.8 V

dynamic operating current per MHz,
per each data input

RESET = V

;

= V

IH(AC)

or V

IL(AC)

; CK and CK

switching at 50 % duty cycle. One
data input switching at half clock
frequency, 50 % duty cycle.
I

= 0 mA; V

= 1.8 V

input capacitance, data inputs

= V

REF

250 mV; V

= 1.8 V

2.5

3.5

input capacitance, CK and CK

ICR

= 0.9 V; V

= 600 mV;

= 1.8 V

input capacitance, RESET

= V

or GND; V

= 1.8 V

9397 750 13799

Product data sheet

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Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

[1]

This parameter is not necessarily production tested.

[2]

Data inputs must be active below a minimum time of t

ACT(max)

after RESET is taken HIGH.

[3]

Data and clock inputs must be held at valid levels (not floating) a minimum time of t

INACT(max)

after RESET is taken LOW.

[1]

Includes 350 ps of test-load transmission line delay.

[2]

This parameter is not necessarily production tested.

Table 9:

Timing requirements

Over recommended operating conditions, unless otherwise noted.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

clock

clock frequency

450

MHz

pulse duration, CK, CK HIGH or
LOW

ACT

differential inputs active time

[1] [2]

INACT

differential inputs inactive time

[1] [3]

setup time, Chip Select

DCS0, DCS1 valid before
clock switching

0.7

setup time, Data

Dn valid before clock
switching

0.5

setup time, PARIN

PARIN before CK and CK

0.5

hold time

input to remain valid after
clock switching

0.5

hold time, PARIN

PARIN after CK and CK

0.5

Table 10:

Switching characteristics

Over recommended operating conditions, unless otherwise noted.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

MAX

maximum input clock frequency

450

MHz

PDM

propagation delay

CK and CK to output

[1]

1.41

1.8

LOW-to-HIGH delay

CK and CK to PTYERR

1.2

HIGH-to-LOW delay

CK and CK to PTYERR

PLH

LOW-to-HIGH propagation delay

from RESET to PTYERR

PDMSS

propagation delay, simultaneous
switching

CK and CK to output

[1] [2]

2.0

PHL

propagation delay

RESET to output

Table 11:

Output edge rates

Over recommended operating conditions, unless otherwise noted.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

dV/dt_r

rising edge slew rate

V/ns

dV/dt_f

falling edge slew rate

V/ns

dV/dt_

absolute difference between dV/dt_r
and dV/dt_f

V/ns

9397 750 13799

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Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

11. Test information

11.1 Test circuit

All input pulses are supplied by generators having the following characteristics: Pulse
Repetition Rate (PRR)

10 MHz; Z

= 50

; input slew rate = 1 V/ns

20 %, unless

otherwise specified.

The outputs are measured one at a time with one transition per measurement.

(1) C

includes probe and jig capacitance.

Fig 8.

Load circuit

(1) I

tested with clock and data inputs held at V

or GND, and I

= 0 mA.

Fig 9.

Voltage and current waveforms; inputs active and inactive times

= 600 mV

= V

REF

+ 250 mV (AC voltage levels) for differential inputs. V

= V

for LVCMOS inputs.

= V

REF

250 mV (AC voltage levels) for differential inputs. V

= GND for LVCMOS inputs.

Fig 10. Voltage waveforms; pulse duration

= 100

= 1000

= 50

CK inputs

OUT

DUT

test point

002aaa371

test point

= 350 ps, 50

= 1000

= 30 pF

(1)

LVCMOS

RESET

10 %

(1)

INACT

ACT

90 %

0 V

002aaa372

ICR

input

002aaa373

9397 750 13799

Product data sheet

Rev. 02 -- 28 September 2004

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Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

= 600 mV

REF

= V

REF

+ 250 mV (AC voltage levels) for differential inputs. V

= V

for LVCMOS inputs.

= V

REF

250 mV (AC voltage levels) for differential inputs. V

= GND for LVCMOS inputs.

Fig 11. Voltage waveforms; setup and hold times

PLH

and t

PHL

are the same as t

Fig 12. Voltage waveforms; propagation delay times (clock to output)

PLH

and t

PHL

are the same as t

= V

REF

+ 250 mV (AC voltage levels) for differential inputs. V

= V

for LVCMOS inputs.

= V

REF

250 mV (AC voltage levels) for differential inputs. V

= GND for LVCMOS inputs.

Fig 13. Voltage waveforms; propagation delay times (reset to output)

input

REF

ICR

002aaa374

output

PLH

002aaa375

ICR

PHL

i(p-p)

PHL

002aaa376

LVCMOS

RESET

output

9397 750 13799

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Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

11.2 Output slew rate measurement

= 1.8 V

0.1 V.

All input pulses are supplied by generators having the following characteristics:
PRR

10 MHz; Z

= 50

; input slew rate = 1 V/ns

20 %, unless otherwise specified.

(1) C

includes probe and jig capacitance.

Fig 14. Load circuit, HIGH-to-LOW slew measurement

Fig 15. Voltage waveforms, HIGH-to-LOW slew rate measurement

(1) C

includes probe and jig capacitance.

Fig 16. Load circuit, LOW-to-HIGH slew measurement

Fig 17. Voltage waveforms, LOW-to-HIGH slew rate measurement

= 10 pF

(1)

OUT

DUT

test point

= 50

002aaa377

output

80 %

20 %

dv_f

dt_f

002aaa378

= 10 pF

(1)

OUT

DUT

test point

= 50

002aaa379

80 %

20 %

dv_r

dt_r

output

002aaa380

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Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

11.3 Error output load circuit and voltage measurement

= 1.8 V

0.1 V.

All input pulses are supplied by generators having the following characteristics:
PRR

10 MHz; Z

= 50

; input slew rate = 1 V/ns

20 %, unless otherwise specified.

(1) C

includes probe and jig capacitance.

Fig 18. Load circuit, error output measurements

Fig 19. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to

RESET input

Fig 20. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect

to clock inputs

= 10 pF

(1)

OUT

DUT

test point

= 1 k

002aaa500

PLH

0 V

0.15 V

0 V

output

waveform 2

RESET

002aaa501

LVCMOS

ICR

timing
inputs

output

waveform 1

i(p-p)

ICR

002aaa502

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Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

12. Package outline

Fig 22. Package outline SOT802-1 (TFBGA160)

UNIT

max.

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

1.2

0.35
0.25

0.85
0.75

0.45
0.35

13.1
12.9

0.65

7.15

11.05

0.08

0.1

0.15

DIMENSIONS (mm are the original dimensions)

SOT802-1

- - -

03-01-29

9.1
8.9

detail X

A2 A1

ball A1
index area

10 mm

scale

TFBGA160: plastic thin fine-pitch ball grid array package; 160 balls; body 9 x 13 x 0.8 mm

SOT802-1

y1 C

1/2e

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Product data sheet

Rev. 02 -- 28 September 2004

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Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

13. Soldering

13.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of
soldering ICs can be found in our

Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.

13.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)
vary between 100 seconds and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215

C to 270

C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

below 225

C (SnPb process) or below 245

C (Pb-free process)

for all BGA, HTSSON..T and SSOP..T packages

for packages with a thickness

2.5 mm

for packages with a thickness < 2.5 mm and a volume

350 mm

so called

thick/large packages.

below 240

C (SnPb process) or below 260

C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm

so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

13.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically
developed.

If wave soldering is used the following conditions must be observed for optimal results:

Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

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Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

For packages with leads on four sides, the footprint must be placed at a 45

angle to

the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250

or 265

C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.

13.4 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300

When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270

C and 320

13.5 Package related soldering information

[1]

For more detailed information on the BGA packages refer to the

(LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales office.

[2]

All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal or
external package cracks may occur due to vaporization of the moisture in them (the so called popcorn
effect). For details, refer to the Drypack information in the

Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3]

These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no
account be processed through more than one soldering cycle or subjected to infrared reflow soldering with
peak temperature exceeding 217

C measured in the atmosphere of the reflow oven. The package

body peak temperature must be kept as low as possible.

Table 12:

Suitability of surface mount IC packages for wave and reflow soldering methods

Package

[1]

Soldering method

Wave

Reflow

[2]

BGA, HTSSON..T

[3]

, LBGA, LFBGA, SQFP,

SSOP..T

[3]

, TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS

not suitable

[4]

suitable

PLCC

[5]

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

[5] [6]

suitable

SSOP, TSSOP, VSO, VSSOP

not recommended

[7]

suitable

CWQCCN..L

[8]

, PMFP

[9]

, WQCCN..L

[8]

not suitable

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Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

[4]

These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the
solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink
on the top side, the solder might be deposited on the heatsink surface.

[5]

If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6]

Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7]

Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger
than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8]

Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by
using a hot bar soldering process. The appropriate soldering profile can be provided on request.

[9]

Hot bar soldering or manual soldering is suitable for PMFP packages.

9397 750 13799

Product data sheet

Rev. 02 -- 28 September 2004

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Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

14. Revision history

Table 13:

Revision history

Document ID

Release date

Data sheet status

Change notice

Doc. number

Supersedes

SSTU32865_2

20040928

Product data sheet

9397 750 13799

SSTU32865-01

Modifications:

The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.

Section 1 "General description"

: acronym TFBGA defined.

Section 2 "Features"

: acronym SSTL defined.

Additional features added to

Section 2 "Features"

Section 6 "Pinning information"

change `MCL' to `m.c.l.' and `MCH' to `m.c.h.'

add descriptions for VDDL and VDDR in

Table 2 "Pin description"

added

Figure 2 "Pin configuration for TFBGA160"

added

Figure 3 "Ball mapping"

(replaces Table 2 "Ball mapping")

Table 3 "Function table (each flip-flop)"

and

Table 4 "Parity and standby function table"

moved to

Section 7.1 on page 8

Table 3 "Function table (each flip-flop)"

: add

Table note 1

and its reference at `Outputs'.

Table 4 "Parity and standby function table"

Table note 2

: change `This transition assumes ...' to `This condition assumes ...'.

Add

Table note 3

Section 7.3.4 "Power-up sequence"

: add `(HIGH)' after `... and will be held clear'.

Table 6 "Limiting values"

Symbol V

changed to V

; Symbol V

changed to V

Symbols ESD

HBM

and ESD

replaced with V

esd

(added model types under "Conditions")

Table 7 "Recommended operating conditions"

change V

(for data inputs) to V

IH(AC)

and V

IH(DC)

; condition changed to `data inputs (Dn)'

change V

(for data inputs) to V

IL(AC)

and V

IL(DC)

; condition changed to `data inputs (Dn)

Table note split into 2 notes; references added.

Table 8 "Characteristics"

change I

DDD

Parameter from "dynamic operating current ..." to "dynamic operating current per

MHz ..."; change Unit from "

A/MHz" to "

A".

change Typical value for I

DDD

(clock only) from TBD to 16

change Typical value for I

DDD

(per each data input) from TBD to 19

Table 9 "Timing requirements"

change symbol f

CLOCK

to f

clock

change f

clock

maximum value from 270 MHz to 450 MHz

change symbol t

to t

; under `Conditions', change `Chip Select' to `DCS0, DCS1'.

change symbol t

to t

Table 10 "Switching characteristics"

change f

MAX

minimum value from 270 MHz to 450 MHz

change t

PDM

maximum value from 2.15 ns to 1.8 ns

change t

PDMSS

maximum value from 2.35 ns to 2.0 ns

Section 11.1 "Test circuit"

: acronym PRR defined; titles for

Figure 12

and

Figure 13

modified.

SSTU32865-01

20040705

Product data

9397 750 10942

Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

9397 750 13799

Product data sheet

Rev. 02 -- 28 September 2004

28 of 29

15. Data sheet status

[1]

Please consult the most recently issued data sheet before initiating or completing a design.

[2]

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

16. Definitions

Short-form specification -- The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.

Application information -- Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.

17. Disclaimers

Life support -- These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status `Production'),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.

18. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com

Level

Data sheet status

[1]

Product status

[2] [3]

Definition

Objective data

Development

This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.

Date of release: 28 September 2004

Document number: 9397 750 13799

Published in the U.S.A.

Philips Semiconductors

SSTU32865

1.8 V DDR registered buffer with parity

19. Contents

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information . . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

Pinning information . . . . . . . . . . . . . . . . . . . . . . 4

6.1

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

Functional description . . . . . . . . . . . . . . . . . . . 8

7.1

Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.2

Functional information . . . . . . . . . . . . . . . . . . . 9

7.3

Functional differences to SSTU32864 . . . . . . 10

7.3.1

Chip Select (CS) gating of key inputs
(DCS0, DCS1, CSGATEEN). . . . . . . . . . . . . . 10

7.3.2

Parity error checking and reporting. . . . . . . . . 10

7.3.3

Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . 10

7.3.4

Power-up sequence . . . . . . . . . . . . . . . . . . . . 10

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15

Recommended operating conditions. . . . . . . 15

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 16

Test information . . . . . . . . . . . . . . . . . . . . . . . . 18

11.1

Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

11.2

Output slew rate measurement. . . . . . . . . . . . 20

11.3

Error output load circuit and voltage
measurement . . . . . . . . . . . . . . . . . . . . . . . . . 21

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

13.1

Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

13.2

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 24

13.3

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 24

13.4

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 25

13.5

Package related soldering information . . . . . . 25

Revision history . . . . . . . . . . . . . . . . . . . . . . . . 27

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 28

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Contact information . . . . . . . . . . . . . . . . . . . . 28

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SSTU32865EG

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SSTU32865EG