1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

FEATURES

3-wire serial interface for programming and status
reading

Suitable for MFM (Modified Frequency Modulation),
RLL 1,7 (Run Length Limited) and similar codes

Transfer rates with MFM code from
250 kbits/s to 4 Mbits/s

Transfer rates with RLL(1,7) code from
500 kbits/s to 12 Mbits/s

Programmable FIR (Finite Impulse-Response) filter
makes it possible to equalize complex and asymmetric
channel impulse responses

Programmable fixed and tracking qualification
thresholds provide reliable data recovery in read mode,
and reliable bad sector detection in verify mode

Read pulse output for floppy tape drives

Digital data synchronizer based on digital PLL with
maximum likelihood detector for a better error rate than
can be achieved with conventional analog circuits

Data verification can be used (with the maximum
likelihood detector switched off) to find bad sectors on
drives with conventional read electronics

Servo stripe detection for TR4, QIC3080 and similar
formats

Gap detector

2 programmable current sources

Peak-to-peak amplitude detector with lowpass filter for
servo burst reading

Fully digital PLL for clock and data recovery:

Fully programmable behaviour

No external components, no tolerance problems

Programmable window shift

Fast run-in capability

Ideal zero phase restart.

Parallel 8-bit input and output for product development
and production testing

Programmable WEQ (write equalization) circuit with
transfer rates of up to 2 Mbits/s for floppy tape drives
and up to 8 Mbits/s for drives with internal controllers.

GENERAL DESCRIPTION

The SZA1000 is a single chip digital equalizer for single
channel QIC (Quarter Inch Cartridge) systems with
MR (Magneto Resistive) heads. It can be used with
QIC 3010, QIC 3020, QIC 3080, QIC 3095, Travan 2, 3, 4
and 5, and similar formats.

It replaces a pulse detector, programmable filter and data
synchronizer, and adds a FIR filter to the conventional
analog solution. This makes it possible to equalize
yoke-type MR heads as well as SIG (Sensor In Gap)
MR heads.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

DDD1

; V

DDD2

digital supply voltage

4.5

5.0

5.5

DDA1

; V

DDA2

analog supply voltage

4.5

5.0

5.5

DDD1

; I

DDD2

digital supply current

= 24 MHz

DDA1

; I

DDA2

analog supply current

clk(CLKIN)

read circuit clock frequency

MHz

clk(WEQCLK)

WEQ circuit clock frequency

MHz

amb

ambient operating temperature

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

SZA1000H

QFP44

plastic quad flat package; 44 leads (lead length 1.3 mm)
body 10

1.75 mm

SOT307-2

1998

Feb

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

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BLOCK DIAGRAM

ndbook, full pagewidth

MGG582

XOSC/

CLK IN

I/O

MUX

WRITE

EQUALIZATION

SERIAL

INTERFACE

IDAC

LPF

15 kHz

DIFF

PLL

AMPL.

DETECTOR

DAC

MAXIMUM

LIKELIHOOD

DETECTOR

LPF

8 MHz

AMPL.

QUALIFIER

GAP

DETECTOR

STRIPE

DETECTOR

READ

PULSE

ADC

HPF

FIR

CLK

DIV

LPF

INTERPOL

38 1

CMPB

EYEA

CMPA

EYEB

39 44

8, 28,
34, 41

5, 26,
35, 42

VSSD1

VDDD1

VSSD2

VDDD2

VSSA1

VDDA1

VSSA2

VDDA2

11 to 18

SRD/RD

LTD

CLKIN

CLKOUT

RRC

GAP/STRIPE

SDIO

SCLK

SDEN

WEQEN

WEQCLK

WDIN

AUXBUS0/WDOUT

TEST

INB

INA

Vref

RESET

WGATE

WGX

AUXBUS1

AUXBUS7

PACLK

SZA1000

IO2

IO1

Rref

Fig.1 Block diagram.

1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

PINNING

SYMBOL

PIN

DESCRIPTION

IO1

programmable current source

IO2

programmable current source

WEQEN

write equalization circuit enable input

WGATE

write gate input; active LOW

DDD1

digital supply voltage

CLKIN

external clock or crystal oscillator input

CLKOUT

crystal oscillator output

SSD1

digital ground

WEQCLK

write equalization circuit clock input

WDIN

write equalization circuit data input

AUXBUS0/WDOUT

bit 0 auxiliary I/O bus or write equalization output to write amplifier

AUXBUS1

bit 1 auxiliary I/O bus

AUXBUS2

bit 2 auxiliary I/O bus

AUXBUS3

bit 3 auxiliary I/O bus

AUXBUS4

bit 4 auxiliary I/O bus

AUXBUS5

bit 5 auxiliary I/O bus

AUXBUS6

bit 6 auxiliary I/O bus

AUXBUS7

bit 7 auxiliary I/O bus

LTD

fast lock to data input; active LOW

read gate input

GAP/STRIPE

gap or stripe detector output

SDIO

serial interface data input and output

SDEN

serial interface enable input

SCLK

serial interface clock input

RRC

read reference clock output

DDD2

digital supply voltage

SRD/RD

synchronized read data or read data output

SSD2

digital ground

PACLK

pre-amp clock output

RESET

reset input; active LOW

TEST

test input; connect to ground

INA

analog signal from read amplifier; positive input

INB

analog signal from read amplifier; negative input

SSA1

analog ground

DDA1

analog supply voltage

WGX

extended write gate output for floppy tape drives; active LOW

ref

positive A/D reference voltage input

ref

connect external resistor

EYEA

differentiated signal; positive output

CMPA

comparator for read pulse; positive input

1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

FUNCTIONAL DESCRIPTION

Clock oscillator and divider

The clock source for the SZA1000 can be a crystal
connected between pins 6 and 7, or an external clock
signal connected to pin 6. This clock frequency is divided
by a number programmable between 1 and 8
(see Tables 27 and 28). The resulting frequency, f

, is

used as clock input to all on-chip circuits except the write
equalizer. The frequency of the PACLK output signal
(pin 29) is equal to f

ADC

The 8-bit ADC has a differential input. The total ADC
conversion range is 1.6 V (p-p; differential). The ADC
sample rate is equal to f

High-pass filter after the ADC

This is a first order filter with a cut-off frequency of
It removes the DC component of the signal.

Low-pass filter

This low-pass filter is an even symmetrical FIR (Finite
Impulse Response) filter. The number of taps depends on
the sample rate reduction factor R (see Tables 30 and 31).
The filter has 8 taps for R = 1 or 14 taps for R = 2 (see
Table 7). The middle taps have a fixed coefficient value of
+128, the coefficients of the other taps are programmable
in the range

128 to +127 (see Table 6).

FIR

This transversal filter has 6 taps with the sample rate equal
to f

(R = 1), or 11 taps with the sample rate equal to

(R = 2). Tap 10 has a fixed coefficient value of +64, the
coefficients of the other taps are programmable between

64 and +63 (see Table 2). The filter has 19 signal delay

sections. The position of each tap can be selected from a
subset of the 20 possible positions (see Tables 3 and 4).

Interpolator

If a sample rate of

has been selected for the FIR

(R = 2), it is increased once again to f

at the interpolator.

1608

-------------

Amplitude detector

This circuit has a separate rectifier and a positive and
negative peak detector.

Typical rise time (0 to 70%) for a normal MFM or

RLL 1,7 code input signal is

, typical decay time

(100 to 30%) is programmable between

and

(see Tables 10 and 11).

The output is an 8-bit number that can be polled via the
serial interface. In addition, the peak-to-peak value is
calculated and filtered by a first order low-pass filter with a

cut-off frequency of

Both the filtered and unfiltered amplitudes can be read via
the serial interface (see Table 44) or via the parallel output
bus.

Amplitude qualifier

A peak is considered valid if its amplitude is above a
qualification threshold. Separate qualification thresholds
are used for the positive and negative peaks. Each
threshold is the greater of:

a programmable level (QUAL_FIX_ POS and
QUAL_FIX_NEG; control register addresses 24 and 25)

a programmable fraction (

or 0;

see Tables 9 and 12) of the peak amplitude of the
incoming signal.

Gap detector

When the peak-to-peak amplitude of the measured signal
is below a preset limit (GAP_THRESH; control register
address 28), the gap detector output is HIGH, otherwise
LOW (GAP output on pin 21 must be selected; see
Table 22).

----

500

----------

400

----------

3217

-------------

1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

Stripe detector

This circuit is used to signal the stripes in QIC 3080,
QIC 3095 and TR4 servo formats (STRIPE output on
pin 21 must be selected; see Table 22). A frequency
detector counts the peaks above the qualification
threshold (see Table 29). An input signal containing
frequencies within

25% of the programmable nominal

frequency will be detected as a stripe. The microcontroller
can then poll the amplitude of the following burst via the
serial interface.

Differentiator

This function is realized by subtracting samples. The delay
between samples is programmable between 1 and 6
periods of f

, split into two parts to provide a balanced

delay between the differentiated and non-differentiated
signals (see Tables 24 to 26).

The PLL

This is a fully digital PLL (Phase Lock Loop) with a
programmable nominal frequency (see Tables 35 and 36),
zero phase restart, programmable window shift
(WIN_SHIFT; control register address 42) and a loop filter
with two separate programmable settings.

The PLL output reference clock is the RRC signal (pin 25;
see Table 34). The frequency of this signal is rounded in
time to f

. The PLL is switched to the nominal frequency if

RG (pin 20) is LOW, and makes a zero phase restart at the
first detected peak after RG goes HIGH.

The LTD input (pin 19) is used to select between the two
loop filter settings (see Tables 37 to 42). This allows for
fast lock-in during preamble, before switching to a lower
loop bandwidth for maximum data reliability (see Fig.3).

Fig.3 PLL timing diagram.

handbook, halfpage

MGG583

INPUT
SIGNALS

PLL
MODE

preamble

data

nominal
frequency

fast lock-in

normal read mode

zero phase restart

LTD

The maximum likelihood detector

This detector calculates the most likely position of the
peaks in the signal. It checks for (d,k) code constraints,
and for alternating peaks. If an error is detected, the `most
likely' correction is implemented.

Separate corrections can be enabled or disabled.
The SRD output of the maximum likelihood detector is
valid during the rising edge of the RRC signal (see Fig.4).

The maximum likelihood detector is used only to generate
the SRD signal, and not to generate the time continuous
RD pulse.

The DAC

This is an internal differential 8-bit DAC operating at f

The LPF after the DAC

This analog LPF filters the time quantized signal from the
DAC to retain a time continuous signal. This provides more
accurate timing of the detected zero crossings in the RD
pulse output.

The LPF is a second order active filter with a cut-off
frequency of 8 MHz.

The read pulse circuit

A peak in the equalized signal at the interpolator output
generates a read pulse. The peak is detected if a zero
crossing occurs in the filtered signal after the DAC while
the non-differentiated signal is above the qualification
threshold.

Uncommitted current sources

Two uncommitted 5-bit programmable current sink DACs
(0 to 2 mA) are available as IO1 and IO2 (see Table 20 for
programming). These could be used, for example, to drive
the tape hole detector circuit.

Fig.4 SRD/RRC timing.

handbook, halfpage

MGG584

SRD

RRC

1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

Parallel state bus

All internal digital signals can be monitored via an 8-bit
parallel bus. An external DAC or an evaluation tool such as
a phase error logger for TIA (Time Interval Analyzer),
drop-out and symmetry measurements can be connected
to this bus for evaluation purposes (see Table 34).

Write equalization

This circuit has an independent clock input WEQCLK at
pin 9.

Write equalization can be programmed to conform to a
number of formats including QIC 3010, QIC 3020,
QIC 3080, QIC 3095, QIC 5010, Travan 2, Travan 3 and
Travan 4.

This is achieved by programming the circuit to divide a
channel bit-cell into 2, 3 or 6 time slots (see Tables 13
and 14). The external WEQ clock frequency should be
selected such that an integer number of between 1 and 8
clock periods fits in a time slot (see Tables 18 and 19).

The width and position of the inserted write pulse can be
programmed (see Tables 15 to 17).

The write equalization circuit input and output signals can
be independently programmed to be in either WD or WDI
format (see Table 15).

For QIC 3010 or 3020, the recording signal is typically
generated by a circuit that uses a separate crystal.
An input buffer with variable delay is used to prevent errors
occurring in the recorded signal. This buffer is set to its
nominal position when writing begins.

Signals longer than a data block can be recorded during
formatting. To avoid overloading the time buffer, the circuit
can resynchronize automatically during gaps in the
QIC 3010 or 3020 format.

Serial interface

The serial interface uses 8-bit addresses and 8-bit data.
Its timing is shown in Fig.5. IC mode settings, filter
coefficients, scale factors and thresholds can be loaded
via the serial interface.

Measured signal amplitude, for example Burst level
measurement at QIC 3095 or AGC control by the
microcontroller, and the actual PLL frequency can be read
via the serial interface. To read data from the status
registers, hex address FF must be transmitted along with
the required data code. The IC will then respond with the
contents of the appropriate 8-bit status register
(see Table 44).

1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

CONTROL REGISTER

Control register settings

The control register is accessible through the serial interface and contains 46 8-bit entries as shown in Table 1.

Table 1

Control register

ADDRESS

NAME

DESCRIPTION

FIR_VAL0

FIR tap 0 coefficient value (see Table 2)

FIR_VAL1

FIR tap 1 coefficient value

FIR_VAL2

FIR tap 2 coefficient value

FIR_VAL3

FIR tap 3 coefficient value

FIR_VAL4

FIR tap 4 coefficient value

FIR_VAL5

FIR tap 5 coefficient value

FIR_VAL6

FIR tap 6 coefficient value

FIR_VAL7

FIR tap 7 coefficient value

FIR_VAL8

FIR tap 8 coefficient value

FIR_VAL9

FIR tap 9 coefficient value

FIR_SEL05

FIR tap positions (see Tables 3 and 4)

FIR_SEL16

FIR tap positions

FIR_SEL27

FIR tap positions

FIR_SEL38

FIR tap positions

FIR_SEL49

FIR tap positions

FIR_SEL10

FIR tap positions

FIR_SHIFT

FIR output scaling (see Table 5)

LPF_VAL1

LPF tap coefficient value (see Table 6)

LPF_VAL4

LPF tap coefficient value

LPF_VAL2

LPF tap coefficient value

LPF_VAL5

LPF tap coefficient value

LPF_VAL3

LPF tap coefficient value

LPF_VAL6

LPF tap coefficient value

LPF_SHIFT

LPF output scaling (see Table 8)

QUAL_FIX_POS

Amplitude qualifier positive fixed qualification threshold

QUAL_FIX_NEG

Amplitude qualifier negative fixed qualification threshold

QUAL_VAR_GAIN

Amplitude qualifier variable gain factors (see Tables 9 and 12)

QUAL_SLOPE_DEL

Amplitude detector slope qualification delay (see Table 10)

GAP_THRESH

Gap detector fixed threshold

WEQ_SET0

WEQ settings (see Tables 13 and 14)

WEQ_SET1

WEQ settings (see Tables 15, 16 and 17)

WEQ_CLK_DIV

WEQ clock divider (see Tables 18 and 19)

not used

IDAC1

IO1 DAC current (see Table 20)

IDAC2

IO2 DAC current (see Table 20)

1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

Control register functions

Control register functions are detailed in Tables 2 to 43.

FIR

FUNCTION

Addresses 0 to 9: FIR tap coefficient values

Table 2

Coefficient values: FIR_VAL0 to FIR_VAL9; note 1

Note

1. These are 7-bit coefficient values in two's complement notation; taps 5 to 9 are only used when R = 2; tap 10 has a

fixed coefficient value of +64.

Addresses 10 to 15: FIR tap position selection

Table 3

Tap position selection: FIR_SELnn; note 1

Note

1. See Table 4 for the value of FSn.n.

EQ MODE0

Mode setting for PACLK (pin 29) and GAP/STRIPE (pin 21)
(see Tables 21, 22 and 23)

DIFF

differentiator settings (see Tables 24, 25 and 26)

CLK_DIV

main clock divider (see Tables 27 and 28)

STRIPE_F

stripe detector nominal frequency (see Table 29)

EQ_MODE1

equalizer mode settings

PLL_FREQL

PLL nominal frequency bits 0 to 7

PLL_FREQH

PLL nominal frequency bits 8 to 10

WIN_SHIFT

PLL window shift

PLL_NI

PLL loop filter integrating gain and range

PLL_NP

PLL loop filter proportional gain

MLD_SET

maximum likelihood detector settings

FIR_VALn.6

FIR_VALn.5

FIR_VALn.4

FIR_VALn.3

FIR_VALn.2

FIR_VALn.1

FIR_VALn.0

ADDR.

NAME

TAPS

FIR_SEL05

0 and 5

FS0.2

FS0.1

FS0.0

FS5.2

FS5.1

FS5.0

FIR_SEL16

1 and 6

FS1.2

FS1.1

FS1.0

FS6.2

FS6.1

FS6.0

FIR_SEL27

2 and 7

FS2.2

FS2.1

FS2.0

FS7.2

FS7.1

FS7.0

FIR_SEL38

3 and 8

FS3.2

FS3.1

FS3.0

FS8.2

FS8.1

FS8.0

FIR_SEL49

4 and 9

FS4.2

FS4.1

FS4.0

FS9.2

FS9.1

FS9.0

FIR_SEL10

FS10.3 FS10.2 FS10.1 FS10.0

ADDRESS

NAME

DESCRIPTION

1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

Table 4

Translation table: FS selection bits (FSn.n from Table 3) to tap position

Address 16: FIR output scaling

Table 5

Output scaling: FIR_SHIFT

PASS FILTER FUNCTIONS

Addresses 17 to 22: LPF tap coefficient values

Table 6

Coefficient value: LPF_VAL1 to LPF_VAL6; notes 1 and 2

Notes

1. These are 8-bit coefficient values in two's complement notation; taps 4 to 6 are only used when R = 2.

2. See Table 7 for the values of LPF_VALn.n

FSn

TAP 0,5

TAP 1,6

TAP 2,7

TAP 3,8

TAP 4,9

TAP 10

FIR_SHIFT (BINARY)

FIR OUTPUT SCALING GAIN FACTOR

00000001

00000010

00000100

00001000

00010000

00100000

01000000

10000000

128

LPF_VALn.7

LPF_VALn.6

LPF_VALn.5

LPF_VALn.4

LPF_VALn.3

LPF_VALn.2

LPF_VALn.1

LPF_VALn.0

1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

Table 7

LPF tap positions

Address 23: LPF output scaling

Table 8

Output scaling: LPF_SHIFT

MPLITUDE QUALIFIER

DETECTOR FUNCTIONS

Address 24: QUAL_FIX_POS and Address 25: QUAL_FIX_NEG

QUAL_FIX_POS and QUAL_FIX_NEG contain the positive and negative fixed threshold (8-bit signed) values.

Address 26: Variable gain factors

Table 9

Gain factors: QUAL_VAR_GAIN; note 1

Note

1. GP and GN set the factors of the measured amplitude that are to be used as variable qualifier thresholds: GP for the

positive peaks and GN for the negative peaks.

TAP POSITION

COEFFICIENT VALUES R = 1

COEFFICIENT VALUES R = 2

LPF_VAL3

LPF_VAL6

LPF_VAL2

LPF_VAL5

LPF_VAL1

LPF_VAL4

+128

LPF_VAL3

+128

LPF_VAL2

LPF_VAL1

LPF_VAL2

+128

LPF_VAL3

+128

LPF_VAL1

LPF_VAL2

LPF_VAL3

LPF_VAL4

LPF_VAL5

LPF_VAL6

LPF_SHIFT (BINARY)

LPF OUTPUT SCALING GAIN FACTOR

00000001

00000010

00000100

00001000

00010000

00100000

01000000

10000000

128

GP.2

GP.1

GP.0

GN.2

GN.1

GN.0

1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

Address 27: Amplitude detector slope qualification delay

Table 10 Qualification delay: QUAL_SLOPE_DEL; notes 1 and 2

Notes

1. DEL is the programmable compensation delay, in cycles of f

, between the qualifier and the analog zero crossing of

the read pulse circuit; DEL is a 2-bit unsigned value

2. SL selects the decay time of the amplitude detectors.

DEL.1

DEL.0

SL.1

SL.0

Table 11 Amplitude detector decay time

DECAY TIME

500

----------

500

----------

1000

-------------

2000

-------------

4000

-------------

Table 12 Variable qualifier threshold

GP, GN

VARIABLE THRESHOLD

4, 5, 6, 7

AP DETECTOR FUNCTIONS

Address 28: Fixed threshold: GAP_THRESH

Fixed threshold for the gap detector; 8-bit signed value.

RITE

QUALIZATION

(WEQ)

FUNCTIONS

Address 29: WEQ settings

Table 13 Time slots: WEQ_SET0; see Table 14

Table 14 Time slots in channel bit cell

NUMBER OF TIME SLOTS

1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

O/P

SIGNAL FUNCTION

PINS

AND

Address 35: O/P Select pins 21 and 29

Table 21 Output signal select: EQ MODE 0; see Tables 22 and 23

PA.1

PA.0

GAP.1

GAP.0

Table 22 Output signal: pin 21

Notes

1. GAP, STRIPE or QUAL may be selected to detect

gaps, stripes or valid signal peaks. All are active HIGH.

2. See also Table 34.

3. The RD output (read pulse): falling edge active.

GAP

OUTPUT SIGNAL ON PIN 21

GAP

(1)

STRIPE

QUAL

(2)

(3)

Table 23 Output signal: pin 29

OUTPUT SIGNAL ON PIN 29

- PACLK on

1 - PACLK off

0 - PACLK off

IFFERENTIATOR FUNCTIONS

Address 36: Differentiator settings

Table 24 DIFF; note 1

Note

1. DL1 and DL2 are programmable delays for the differentiator; DS is the gain factor of the differentiated signal.

DL2.1

DL2.0

DL1.1

DL1.0

Table 25 Differentiator delay; notes 1 and 2

Notes

1. DL1 and DL2 are added to provide a maximum delay

of 6

cycles.

2. It is advisable to have DL1 and DL2 equal to avoid

adding unwanted delay in the differentiator.

DLn

DELAY IN f

CYCLES

Table 26 Differentiator gain factor

OUTPUT SCALING GAIN FACTOR

1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

LOCK FUNCTIONS

Address 37: Main clock divider

Table 27 Clock divider: CLK_DIV; note 1

Note

1. CD selects the main clock division factor. The CLKIN frequency (pin 6) divided by this factor gives the IC's operating

frequency f

(apart from the WEQ circuit).

CD.2

CD.1

CD.0

Table 28 Clock division factor

CLOCK DIVISION

TRIPE DETECTOR FUNCTIONS

Address 38: Stripe detector nominal frequency

Table 29 Qualification threshold: STRIPE_F; note 1

Note

1. SF is an unsigned 5-bit value used to determine the detection threshold for the stripe detector. The nominal detection

frequency is

AUXBUS,

PINS

AND

27,

SAMPLE RATE REDUCTION AND STAND

BY FUNCTIONS

Address 39: Equalizer mode settings

Table 30 EQ_MODE 1; note 1, see also Tables 31 to 34

Note

1. R1 selects the filter sample rate reduction factor; STBY1 and STBY2 are the DAC and ADC power on/off switches;

ST selects output signal modes for pins 25 and 27.

SF.4

SF.3

SF.2

SF.1

SF.0

STBY2

ST.3

ST.2

ST.1

ST.0

STBY1

(

)

----------------------------------

1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

Table 31 FIR/LPF Sample Rate

Reduction Factor: R

Table 32 DAC power

STBY1

D/A POWER

off

Table 33 ADC power

STBY2

A/D POWER

off

Table 34 Mode settings: pins 25, 27 and AUXBUS

Notes

1. QUAL is a test signal (active HIGH) used to detect valid signal peaks (see also Table 22).

2. When COMP is selected, pin 25 is switched to the output of the read pulse circuit comparator for test purposes.

PLL

FUNCTIONS

Addresses 40 and 41: PLL nominal frequency

Table 35 PLL_FREQL (address 40)

Table 36 PLL_FREQH (address 41); note 1

Note

1. The nominal PLL frequency is

IC MODE

PIN 27

PIN 25

AUXBUS

PLL off

QUAL

(1)

bit 0: WDOUT, bits 1 to 7 high-Z

PLL off

COMP

(2)

bit 0: WDOUT, bits 1 to 7 high-Z

PLL on

SRD

RRC

bit 0: WDOUT, bits 1 to 7 high-Z

ADC test

SRD

RRC

ADC output

DAC test

COMP

DAC output

one shot test

PLL off, AD bypass

QUAL

8-bit input to HPF

PLL off, AD bypass

COMP

8-bit input to HPF

PLL on, AD bypass

SRD

RRC

8-bit input to HPF

PLL on, LPF output

SRD

RRC

LPF output after scaling

PLL on, FIR output

SRD

RRC

FIR output after scaling and interpolator

PLL on, PLL phase output

SRD

RRC

PLL phase error output

PLL on, PLL frequency output

SRD

RRC

PLL frequency output

PLL on, peak-to-peak level output

SRD

RRC

bits 7 to 1: LEVEL_ABS; bit 0:WDOUT

PLL on, filtered level output

SRD

RRC

bits 7 to 1: LEVEL_FIL; bit 0:WDOUT

PLL on, differentiator output

SRD

RRC

differentiator output after scaling

PF.7

PF.6

PF.5

PF.4

PF.3

PF.2

PF.1

PF.0

PF.10

PF.9

PF.8

2048

-------------

1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

Table 42 Proportional gain factor KP

AXIMUM LIKELIHOOD DETECTOR FUNCTIONS

Address 45: Settings

Table 43 Address 45: MLD_SET

Notes

1. Check for k constraint: k is the maximum number of channel bit-cells allowed without a transition. For MFM code:

k = 3 (ks = 4), for RLL(1,7) code: k = 7 (ks = 8).

2. Check for d = 1 constraint: d is the minimum number of channel bit-cells without transitions that must come between

two bit cells with transitions. d = 1 for both MFM and RLL(1,7) codes

3. Check partial response constraints; delete incorrect peaks.

4. Check partial response constraints; add missing peaks.

5. ks = k + 1.

TATUS REGISTER

The status register contains 5 status bytes. The contents of the status bytes can be read via the serial interface.

Table 44 Status bytes; notes 1 to 4

Notes

1. The levels are measured behind the re-sampling block (interpolator) (see Fig.1).

2. Actual PLL frequency is an 8-bit unsigned number:

3. LEVEL_FIL can be used for reading of the burst levels, or in an AGC loop (with the TZA1000 preamplifier).

4. LEVEL_POS, LEVEL_NEG, LEVEL_ABS and LEVEL_FIL are 8-bit numbers in two's complement format.

en_k

(1)

en_d

(2)

PR1

(3)

PR0

(4)

ks3

(5)

ks2

(5)

ks1

(5)

ks0

(5)

ADDRESS

DATA

NAME

DESCRIPTION

255

FREQ

actual frequency of PLL

255

LEVEL_POS

positive peaks in measured level

255

LEVEL_NEG

negative peaks in measured level

255

LEVEL_ABS

measured peak-to-peak level

255

LEVEL_FIL

low-pass filtered LEVEL_ABS

FREQ

256

------------------

1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. Equivalent to discharging a 100 pF capacitor through a 1.5 k

series resistance.

2. Equivalent to discharging a 200 pF capacitor through a 25

series resistance and a 2.5

H series inductance.

THERMAL CHARACTERISTICS

QUALITY SPECIFICATION

In accordance with

"SNW-FQ-611-E".

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

DDD1

digital supply voltage

0.3

+5.5

DDD2

digital supply voltage

0.3

+5.5

DDA1

analog supply voltage

0.3

+5.5

DDA2

analog supply voltage

0.3

+5.5

input voltage

0.3

+ 0.3 V

input current on supply pins

+50

I(n)

input current on remaining pins

+10

tot

maximum total power dissipation

+1100

amb

ambient temperature

+85

junction temperature

+125

stg

storage temperature

+150

ES(HB)

electrostatic handling: human body model

note 1

3000

+3000

ES(MM)

electrostatic handling: machine model

note 2

300

+300

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th(j-a)

thermal resistance from junction to ambient

in free air

K/W

1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

CHARACTERISTICS

DDD1

= V

DDD2

= V

DDA1

= V

DDA2

= 5 V

5%; f

= f

clk(CLKIN)

= 24 MHz; V

ref

= 2 V

5%; R

ref

= 10 k

, unless otherwise

specified

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

DDD1

digital supply voltage

4.5

5.0

5.5

DDD2

digital supply voltage

4.5

5.0

5.5

DDA1

analog supply voltage

4.5

5.0

5.5

DDA2

analog supply voltage

4.5

5.0

5.5

DDD1

; I

DDD2

digital supply current

r = 2, no WEQ

DDA1

; I

DDA2

analog supply current

STBY1 = 0;
STBY2 = 1;
see Table 30

STBY 1= 1;
STBY2 = 0

clk(CLKIN)

read circuit clock frequency

MHz

clk(WEQCLK)

WEQ circuit clock frequency

N6 = 0;
see Table 14;
(3080; 3095)

MHz

LOW-level input voltage

0.3V

HIGH-level input voltage

0.7V

LOW-level output voltage

4 mA

0.5

HIGH-level output voltage

= +4 mA

0.5

input capacitance

I/O pins high-Z;
note 1

Analog section

ref

reference voltage (pin 37)

1.8

2.0

2.2

ref

reference current (pin 37)

1.0

1.7

2.1

cnv(A/D)

A/D conversion range

1.6

CM(A/D)

A/D common mode voltage

2.5

i(A/D)

A/D input resistance

2.3

3.3

4.4

i(A/D)

A/D input capacitance

I(32)

DC input current (INA)

0.42

0.6

I(33)

DC input current (INB)

0.13

0.2

voltage on pin 38 (R

ref

)

2.0

O(1)

output current on pin 1 (IO1)

IDAC1 = 0;
see Table 20

0.0

0.05

IDAC1 = 31

1.40

1.95

2.60

O(2)

output current on pin 2 (IO2)

IDAC2 = 0;
see Table 20

0.0

0.05

IDAC2 = 31

1.40

1.95

2.60

o(dif)

D/A differential output range
(peak-to-peak)

note 2

1.5

1.72

1.8

CM(D/A)

D/A common mode voltage

note 2

1.0

1.16

1.4

1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

3dB(cutoff)(LPF)

3dB cut-off frequency,

analog LPF (DAC filter)

note 2

MHz

CM(COMP)

comparator common mode
voltage

note 3

1.0

1.16

1.4

i(COMP)

comparator input resistance

note 4

IO(COMP)

comparator offset voltage

note 4

Serial interface

clk(SIO)

serial i/f clock

MHz

su(D-CLK)

set-up time: data-to-clock

h(D-CLK)

hold time: data-to-clock

note 5

+ 10

d(1)

delay clock: new data

+ 10

d(2)

delay clock: old data

su(EN-CLK)

set-up time: enable-to-clock

+ 10

h(EN-CLK)

hold time: enable-to-clock

+ 10

Digital read section

CLKINH

CLKIN HIGH time

CLKINL

CLKIN LOW time

RDL

RD LOW time

+ 10

su(SRD-RRC)

set-up time: SRD-to-RRC

note 6

CLKINL

0.2C

o(L)(SRD)

CLKINL

+ 2

0.2C

o(L)(RRC)

h(SRD-RRC)

hold time: SRD-to-RRC

note 6

CLKINH

0.2C

o(L)(RRC)

RRCL

RRC LOW time

note 6

CLKINL

0.2C

o(L)(RRC)

CLKINL

su(AUX-CLKIN)

input set-up time:
AUXBUS-to-CLKIN (pin 6)

h(AUX-CLKIN)

input hold time:
AUXBUS-to-CLKIN (pin 6)

PACLKH

PACLK HIGH time

note 7

CLKINH

0.2C

o(L)(PACLK)

CLKINH

PACLKL

PACLK LOW time

note 7

CLKINL

0.2C

o(L)(PACLK)

CLKINL

d(AUX-PACLK)

delay:
AUXBUS-to-PACLK (pin 29)

note 8

10 +
0.2C

o(L)(AUX)

d(PACLK-AUX)

delay: PACLK to AUXBUS

notes 7 and 8

5 +
0.2C

o(L)(PACLK)

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

Notes

1. Pins 3, 4, 6, 9 to 20, 22, 23, 24, 30 and 31.

2. Measured at pins 39 and 44 with a 10 M

/15 pF load.

3. Measured at pins 40 and 43.

4. Differential pins 40 and 43.

6. C

o(L)(SRD)

is the external load (pF), at SRD (pin 27) for C

o(L)(SRD)

< 50 pF.

o(L)(RRC)

is the external load (pF), at RRC (pin 25) for C

o(L)(RRC)

< 50 pF.

7. C

o(L)(PACLK)

is the external load (pF), at PACLK (pin 29) for C

o(L)(PACLK)

< 50 pF.

8. C

o(L)(AUX)

is the external load (pF), at AUX0 to AUX7 (pins 11 to 18) for C

o(L)(AUX)

< 50 pF.

9. C

o(L)(WDOUT)

is the external load (pF), at WDOUT (pin 11) for C

o(L)(WDOUT)

< 50 pF.

Write equalization section

clk(WEQ)

WEQ clock frequency

N2 = 1 or N3 = 1;
see Table 14

MHz

N6 =1;
see Table 14

MHz

WEQL

WEQ LOW time

WEQH

WEQ HIGH time

su(WD-WEQCLK)

setup time:
WDIN-to-WEQCLK

N2 = 1 or N3 = 1;
see Table 14

h(WD-WEQCLK)

hold time: WD-to-WEQCLK

N2 = 1 or N3 = 1;
see Table 14

IL(WDIN)

WDIN input LOW time (WDI
mode)

WDI_I = 0;
see Table 15

OL(WDOUT)

WDOUT output LOW time
(WDI mode)

note 9

WEQH

0.2

o(L)(WDOUT)

WEQH

o(WDIN-WEQCLK)

frequency offset
WDIN-WEQCLK

N6 = 1;
see Table 14

0.5

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

----

1998

Feb

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

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TIMING DIAGRAMS

Serial interface

ll pagewidth

MGG656

3-STATE

WRITE SETTINGS

SDEN

SCLK

SDIO

3-STATE

READ STATUS

SDEN

SCLK

SDIO

ADDRESS AND DATA FROM MICROCONTROLLER

DATA OUT FROM DEVICE

th(EN-CLK)

tsu(D-CLK)

th(D-CLK)

tsu(EN-CLK)

th(EN-CLK)

tsu(EN-CLK)

th(EN-CLK)

tsu(D-CLK)

th(D-CLK)

tsu(EN-CLK)

th(EN-CLK)

tsu(EN-CLK)

td(1)

td(2)

Fig.8 Serial I/O showing set-up, hold and delay timing.

1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

"Quality

Reference Handbook" (order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250

Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.

If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

The footprint must be at an angle of 45

to the board

direction and must incorporate solder thieves
downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

1998 Feb 16

Philips Semiconductors

Product specification

QIC digital equalizer

SZA1000

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors a worldwide company

SCA57

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

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under patent- or other industrial or intellectual property rights.

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Printed in The Netherlands

545102/00/01/pp32

Date of release: 1998 Feb 16

Document order number:

9397 750 01122

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