Document Outline
- FEATURES
- GENERAL DESCRIPTION
- ORDERING INFORMATION
- QUICK REFERENCE DATA
- BLOCK DIAGRAM
- PINNING
- FUNCTIONAL DESCRIPTION
- LIMITING VALUES
- THERMAL CHARACTERISTICS
- CHARACTERISTICS
- APPLICATION INFORMATION
- PACKAGE OUTLINES
- SOLDERING
- DEFINITIONS
- LIFE SUPPORT APPLICATIONS
DATA SHEET
Preliminary specification
Supersedes data of TDA1310; TDA1310T July 1993
File under Integrated Circuits, IC01
May 1994
INTEGRATED CIRCUITS
Philips Semiconductors
TDA1310A
Stereo Continuous Calibration DAC
(CC-DAC)
May 1994
2
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
FEATURES
Space saving package DIL8 or SO8
Low power consumption
Wide dynamic range (16-bit resolution)
Continuous Calibration (CC) concept
Easy application:
Single 3 to 5 V supply rail
Output current and bias current are proportional to
the supply voltage
Fast settling time permits 2
, 4
and 8
oversampling
(serial input) or double speed operation at 4
oversampling
Internal bias current ensures maximum dynamic range
Wide operating temperature range (-40 t +85
C)
Compatible with most current Japanese input formats:
Time multiplexed
Two's complement
TTL
No zero-crossing distortion.
GENERAL DESCRIPTION
The TDA1310A is a device of a new generation of
Digital-to-Analog Converters (DACs) which embodies the
innovative technique of Continuous Calibration. The
largest bit-currents are repeatedly generated by one single
current reference source. This duplication is based upon
an internal charge storage principle having an accuracy
insensitive to ageing, temperature and process variations.
The TDA1310A is fabricated in a 1.0
m CMOS process
and features an extremely low power dissipation, small
package size and easy application. Furthermore, the
accuracy of the intrinsic high coarse-current combined
with the implemented symmetrical offset decoding method
precludes zero-crossing distortion and ensures high
quality audio reproduction. Therefore, the CC-DAC is
eminently suitable for use in (portable) digital audio
equipment.
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
PINS
PIN POSITION
MATERIAL
CODE
TDA1310A
8
DIL8
plastic
SOT97DE
TDA1310AT
8
SO8
plastic
SOT96AG
May 1994
3
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DD
supply voltage
3
5.0
5.5
V
I
DD
supply current
V
DD
= 5 V at code 0000H
-
3.0
4.0
mA
I
FS
full scale output current
V
DD
= 5 V
0.9
1.0
1.1
mA
V
DD
= 3 V
-
0.6
-
mA
(THD+N)/S
total harmonic distortion
plus noise-to-signal ratio
at 0 dB signal level
-
-
65
-
61
dB
-
0.05
0.08
%
at
-
60 dB signal level
-
-
30
-
24
dB
-
3
6
%
at
-
60 dB signal level;
A-weighted
-
-
33
-
dB
-
2.2
-
%
at
-
60 dB signal level;
A-weighted;
R3 = R4 = 11 k
;
(see Fig.1); I
FS
= 2 mA
-
1.7
-
%
S/N
signal-to-noise ratio at
bipolar zero
A-weighted at code 0000H
86
92
-
dB
A-weighted; I
FS
= 2 mA;
R3 = R4 = 11 k
; see Fig.1
-
95
-
dB
t
CS
current settling time to
1 LSB
-
0.2
-
s
BR
input bit rate at data input
-
-
18.4
Mbits/s
f
clk
clock frequency at clock
input BCK
-
-
18.4
MHz
TC
FS
full scale temperature
coefficient at analog
outputs (I
OL
; I
OR
)
-
400
10
-
6
-
T
amb
operating ambient
temperature
-
40
-
+85
C
P
tot
total power dissipation
V
DD
= 5 V at code 0000H
-
15
20
mW
V
DD
= 3 V at code 0000H
-
6.0
-
mW
May 1994
4
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
BLOCK DIAGRAM
Fig.1 Block diagram.
May 1994
5
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
PINNING
SYMBOL
PIN
DESCRIPTION
BCK
1
bit clock input
WS
2
word select input
DATA
3
data input
GND
4
ground
V
DD
5
supply voltage
I
OL
6
left channel output
I
ref
7
reference input
I
OR
8
right channel output
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
The basic operation of the continuous calibration DAC is
illustrated in Fig.3. The figure shows the calibration and
operation cycle. During calibration of the MOS current
source (Fig.3a) transistor M1 is connected as a diode by
applying a reference current. The voltage V
gs
on the
intrinsic gate-source capacitance C
gs
of M1 is then
determined by the transistor characteristics. After
calibration of the drain current to the reference value I
ref
,
the switch S1 is opened and S2 is switched to the other
position (Fig.3b). The gate-to-source voltage V
gs
of M1 is
not changed because the charge on C
gs
is preserved.
Therefore, the drain current of M1 will still be equal to I
ref
and this exact duplicate of I
ref
is now available at the OUT
terminal.
The 32 current sources and the spare current source of the
TDA1310A are continuously calibrated (see Fig.1). The
spare current source is included to allow continuous
converter operation. The output of one calibrated source is
connected to an 11-bit binary current divider consisting of
2048 transistors. A symmetrical offset decoding principle
is incorporated and arranges the bit switching in such a
way that the zero-crossing is performed only by switching
the LSB currents.
The TDA1310A (CC-DAC) accepts serial input data
formats of 16-bit word length. Left and right data words are
time multiplexed. The most significant bit (bit 1) must
always be first. The input data format is shown in
Figs 4 and 5.
With a HIGH level on the word select input (WS), data is
placed in the left input register, with a LOW level on the
WS input, data is placed in the right input register
(see Fig.1). The data in the input registers are
simultaneously latched in the output registers which
control the bit switches.
An internal bias current I
bias
is added to the full scale
output current I
FS
in order to achieve the maximum
dynamic range at the outputs OP1 and OP2 in Fig.1.
The reference input current I
ref
controls with gain G
FS
, the
current I
FS
which is a sink current and with gain G
bias
the
I
bias
which is a source current
(1)
.
The current I
ref
is proportional to V
DD
so the I
FS
and the I
bias
will be proportional to V
DD
as well
(2)
because G
FS
and G
bias
are constant.
The reference voltage V
ref
in Fig.1 is
2
/
3
V
DD
. In this way
maximum dynamic range is achieved over the entire
power supply voltage range.
The tolerance of the reference input current in Fig.1
depends on the tolerance of the resistors R3, R4
and R
ref
(3)
.
(1) I
FS
= G
FS
x I
ref
and I
bias
= G
bias
x I
ref
(2)
(3)
V
DD1
V
DD2
-------------
I
FS1
I
FS2
----------
I
bias1
I
bias2
--------------
=
=
I
ref
I
ref
V
DD
R3
R3
R4
R4
R
ref
R
ref
+
+
+
+
+
-------------------------------------------------------------------------------------------------
=
May 1994
6
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
Calibration principle
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Notes
1. Human body model; C = 100 pF; R = 1500
; 3 zaps positive and negative.
2. Machine model; C = 200 pF; L = 0.5
H; R = 10
; 3 zaps positive and negative.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DD
supply voltage
-
6
V
T
stg
storage temperature
-
55
+150
C
T
xtal
maximum crystal temperature
-
+150
C
T
amb
operating ambient temperature
-
40
+85
C
V
es
electrostatic handling
note 1
-
2000
+2000
V
note 2
-
200
+200
V
SYMBOL
PARAMETER
VALUE
UNIT
R
th j-a
thermal resistance from junction to ambient in free air
DIL8
100
K/W
SO8
210
K/W
Fig.3 Calibration principle.
a. Calibration.
b. Operation.
a.
b.
May 1994
7
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
CHARACTERISTICS
V
DD
= 5 V; T
amb
= 25
C; measured in Fig.1; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
V
DD
supply voltage
3.0
5.0
5.5
V
I
DD
supply current
at code 0000H
-
3.0
4.0
mA
SVRR
supply voltage ripple rejection
note 1
-
30
-
dB
Digital inputs; pins WS, BCK and DATA
|
I
IL
|
input leakage current LOW
V
I
= 0 V
-
-
10
A
|
I
IH
|
input leakage current HIGH
V
I
= 5 V
-
-
10
A
f
clk
clock frequency
-
-
18.4
MHz
BR
bit rate data input
-
-
18.4
Mbits/s
f
WS
word select input frequency
-
-
384
kHz
Timing (see Fig.4)
t
r
rise time
-
-
12
ns
t
f
fall time
-
-
12
ns
t
CY
bit clock cycle time
54
-
-
ns
t
BCKH
bit clock pulse width HIGH
15
-
-
ns
t
BCKL
bit clock pulse width LOW
15
-
-
ns
t
SU;DAT
data set-up time
12
-
-
ns
t
HD:DAT
data hold time to bit clock
2
-
-
ns
t
HD:WS
word select hold time
2
-
-
ns
t
SU;WS
word select set-up time
12
-
-
ns
Analog input; pin I
ref
R
ref
reference resistor
see Fig.1
7.4
11.0
14.6
k
Analog outputs; pins I
OL
and I
OR
RES
resolution
-
-
16
bits
V
DCC
DC output voltage compliance
2.0
-
V
DD
-
1
V
I
FS
full-scale current
0.9
1.0
1.1
mA
TC
FS
full-scale temperature
coefficient
-
400
10
-
6
-
I
bias
bias current
643
714
785
A
G
FS
reference input current to full
scale output current gain
11.9
13.2
14.5
G
bias
reference input current to bias
current gain
8.48
9.42
10.36
May 1994
8
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
Notes
1. V
ripple
= 1% of supply voltage; f
ripple
= 100 Hz.
2. Measured with 1 kHz sine wave generated at sampling rate of 192 kHz.
(THD+N)/S
total harmonic distortion plus
noise-to-signal ratio
at 0 dB signal level;
note 2
-
-
65
-
61
dB
-
0.05
0.08
%
at
-
60 dB signal level;
note 2
-
-
30
-
24
dB
-
3
6
%
at
-
60 dB signal level;
A-weighted; note 2
-
-
33
-
dB
-
2.2
-
%
at
-
60 dB signal level;
A-weighted; note 2;
R3 = R4 = 11 k
;
see Fig.1; I
FS
= 2 mA
-
1.7
-
%
at 0 dB signal level;
f = 20 Hz to 20 kHz
-
-
65
-
61
dB
-
0.05
0.08
%
t
cs
current settling time to
1 LSB
-
0.2
-
s
cs
channel separation
86
95
-
dB
|
I
O
|
unbalance between outputs
I
OL
and I
OR
note 1
-
0.2
0.3
dB
|
t
d
|
time delay between outputs
I
OL
and I
OR
-
0.2
-
s
S/N
signal-to-noise ratio at bipolar
zero
A-weighted at code
0000H
86
92
-
dB
A-weighted; I
FS
= 2 mA;
R3 = R4 = 11 k
;
see Fig.1
-
95
-
dB
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
May 1994
9
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
Fig.4 Timing and input signals.
Fig.5 Format of input signals.
May 1994
10
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
APPLICATION INFORMATION
Remark: the graphs are constructed from average measurement values of a small amount of engineering samples,
therefore no guarantee for typical values is implied.
Fig.6
Total harmonic distortion as a function
of supply voltage (4f
s
).
Measured with a 1 kHz sinewave generated at a
sample frequency (f
s
) = 192 kHz.
(1) Measured within the specified operation supply voltage range
(3 to 5.5 V).
(2) Measured outside the specified operating supply voltage range
(2 to 3 V and 5.5 to 6 V).
Fig.7
Total harmonic distortion as a function
of signal level (4f
s
).
Measured with a 1 kHz sinewave generated at a
sample frequency (f
s
) = 192 kHz.
May 1994
11
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
Fig.8 Total harmonic distortion as a function of frequency (4f
s
).
(1) Measured including all distortion plus noise at a signal level of
-
60 dB.
(2) Measured including all distortion plus noise at a signal level of 0 dB.
May 1994
12
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
PACKAGE OUTLINES
handbook, full pagewidth
8.25
7.80
0.38 max
10.0
8.3
7.62
MSA252 - 1
6.48
6.20
1.73 max
5
8
4
1
1.15
max
0.53
max
0.254
M
3.2
max 4.2
max
3.60
3.05
9.8
9.2
2.54
(3x)
0.51
min
seating plane
Fig.9 Plastic DIL, 8-pin (DIL8).
Dimensions in mm.
May 1994
13
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
Fig.10 Plastic SO, 8-pin (SO8).
Dimensions in mm.
andbook, full pagewidth
pin 1
index
0.7
0.3
0.49
0.36
1.27
0.25 M
(8x)
1
4
5
0.1 S
S
5.0
4.8
4.0
3.8
6.2
5.8
A
8
MBC180 - 1
0.25
0.19
0.7
0.6
1.75
1.35
1.45
1.25
detail A
1.0
0.5
0.25
0.10
0 to 8
o
May 1994
14
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
SOLDERING
Plastic dual in-line packages
B
Y DIP OR WAVE
The maximum permissible temperature of the solder is
260
C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.
R
EPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron below the seating plane
(or not more than 2 mm above it). If its temperature is
below 300
C, it must not be in contact for more than 10 s;
if between 300 and 400
C, for not more than 5 s.
Plastic small-outline packages
B
Y WAVE
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Maximum permissible solder temperature is 260
C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150
C within 6 s.
Typical dwell time is 4 s at 250
C.
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
B
Y SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250
C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45
C.
R
EPAIRING SOLDERED JOINTS
(
BY HAND
-
HELD SOLDERING
IRON OR PULSE
-
HEATED SOLDER TOOL
)
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300
C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320
C. (Pulse-heated soldering is not recommended
for SO packages.)
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
May 1994
15
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1310A
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Semiconductors
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Apartado 300, 2795 LINDA-A-VELHA,
Tel. (01)14163160/4163333, Fax. (01)14163174/4163366.
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. (65)350 2000, Fax. (65)251 6500
South Africa: S.A. PHILIPS Pty Ltd., Components Division,
195-215 Main Road Martindale, 2092 JOHANNESBURG,
P.O. Box 7430 Johannesburg 2000,
Tel. (011)470-5911, Fax. (011)470-5494.
Spain: Balmes 22, 08007 BARCELONA,
Tel. (03)301 6312, Fax. (03)301 42 43
Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,
Tel. (0)8-632 2000, Fax. (0)8-632 2745
Switzerland: Allmendstrasse 140, CH-8027 ZRICH,
Tel. (01)488 2211, Fax. (01)481 77 30
Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West
Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978,
TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382.
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong,
Bangkok 10260, THAILAND,
Tel. (662)398-0141, Fax. (662)398-3319.
Turkey: Talatpasa Cad. No. 5, 80640 GLTEPE/ISTANBUL,
Tel. (0 212)279 2770, Fax. (0212)269 3094
United Kingdom: Philips Semiconductors Limited, P.O. Box 65,
Philips House, Torrington Place, LONDON, WC1E 7HD,
Tel. (071)436 41 44, Fax. (071)323 03 42
United States: INTEGRATED CIRCUITS:
811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. (800)234-7381, Fax. (708)296-8556
DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd.,
P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404,
Tel. (800)447-3762 and (407)881-3200, Fax. (407)881-3300
Uruguay: Coronel Mora 433, MONTEVIDEO,
Tel. (02)70-4044, Fax. (02)92 0601
For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BAF-1,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-724825
SCD31
Philips Electronics N.V. 1994
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
Printed in The Netherlands
513061/1500/02/pp16
Date of release: May 1994
Document order number:
9397 733 00011
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