1997 Jun 05

Philips Semiconductors

Product specification

Horizontal and vertical deflection controller
for VGA/XGA and multi-frequency monitors

TDA4850

FEATURES

VGA operation fully implemented including
alignment-free vertical and E/W amplitude pre-settings

4th VGA mode easy applicable (XGA, Super VGA)

Multi-frequency operation externally selectable

All adjustments DC-controllable

Alignment-free oscillators

Sync separators for video or horizontal and vertical TTL
sync levels regardless of polarity

Horizontal oscillator with PLL1 for sync and PLL2 for
flyback

Constant vertical and E/W amplitude in multi-frequency
operation

DC-coupling to vertical power amplifier (TDA486X or
TDA8351)

Internal supply voltage stabilization with excellent ripple
rejection to ensure stable geometrical adjustments.

GENERAL DESCRIPTION

The TDA4850 provides economical solutions in VGA/XGA
and multi-frequency monitors. The IC incorporates the
complete horizontal and vertical small signal processing.
VGA-dependent mode detection and settings are
performed on chip. In conjunction with TDA486X or
TDA8351 (vertical output circuits) both ICs offer an
extremely advanced system solution.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

supply voltage (pin 1)

9.2

supply current

i sync

AC-coupled composite video signal with negative-going sync
(peak-to-peak value; pin 9)

sync slicing level

120

DC-coupled TTL-compatible horizontal sync signal
(peak value; pin 9)

1.7

slicing level

1.2

1.4

1.6

DC-coupled TTL-compatible vertical sync signal
(peak value; pin 10)

1.7

slicing level

1.2

1.4

1.6

o V

vertical differential output current (peak-to-peak value;
pins 5 and 6)

o H

horizontal sink output current on pin 3

amb

operating ambient temperature

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA4850

DIP20

plastic dual in-line package; 20 leads (300 mil)

SOT146-1

1997 Jun 05

Philips Semiconductors

Product specification

Horizontal and vertical deflection controller
for VGA/XGA and multi-frequency monitors

TDA4850

BLOCK DIAGRAM

handbook, full pagewidth

MEH165

HORIZONTAL

SYNC

SEPARATOR

(TTL VIDEO SYNC)

AUTOMATIC

POLARITY

CORRECTION

HOS

DC-coupled

(TTL level)

vertical sync

(TTL level)

mode

detector

disable

4th mode

AC-coupled

(video)

PLL1

HORIZONTAL

OSCILLATOR

HORIZONTAL

OUTPUT

PLL2

horizontal

flyback

SUPPLY AND

REFERENCE

VOLTAGE

PARABOLA

ADJUSTMENT

AND OUTPUT

VERTICAL

AMPLITUDE

ADJUSTMENT

AND OUTPUT

VERTICAL

OSCILLATOR

AMPLITUDE

CONTROL

VERTICAL

SYNC

INTEGRATOR

CLAMPING AND

BLANKING

GENERATOR

VGA/MULTI-

FREQUENCY

SWITCH

VGA MODE

DETECTOR

AND OUTPUT

AUTOMATIC

POLARITY

CORRECTION

VERTICAL

SYNC

SEPARATOR

(9.2 to 16 V)

E/W drive

horizontal drive

parabola

amplitude

differential vertical output

V supply

H supply

VOS

clamping/

blanking

pulse

VOS

vertical amplitude

TDA4850

Fig.1 Block diagram.

1997 Jun 05

Philips Semiconductors

Product specification

Horizontal and vertical deflection controller
for VGA/XGA and multi-frequency monitors

TDA4850

PINNING

SYMBOL

PIN

DESCRIPTION

positive supply voltage

FLB

horizontal flyback input

HOR

horizontal output

GND

ground (0 V)

VERT1

vertical output 1;
negative-going sawtooth

VERT2

vertical output 2;
positive-going sawtooth

MODE

4th mode output and mode detector
disable input

CLBL

clamping/blanking pulse output

HVS

horizontal sync/video input

vertical sync input

E/W output (parabola to driver stage)

capacitor for amplitude control

vertical amplitude adjustment input

E/W amplitude adjustment input
(parabola)

VOS

vertical oscillator resistor

VOS

vertical oscillator capacitor

PLL1

PLL1 phase

HOS

horizontal oscillator resistor

HOS

horizontal oscillator capacitor

PLL2

PLL2 phase

Fig.2 Pin configuration.

handbook, halfpage

FLB

HOR

GND

VERT1

VERT2

MODE

CLBL

HVS

PLL2

CHOS

RHOS

PLL1

RVOS

REW

CVOS

RVA

CVA

TDA4850

MEH168

1997 Jun 05

Philips Semiconductors

Product specification

Horizontal and vertical deflection controller
for VGA/XGA and multi-frequency monitors

TDA4850

FUNCTIONAL DESCRIPTION

Horizontal sync separator and polarity correction

An AC-coupled video signal or a DC-coupled TTL sync
signal (H only or composite sync) is input on pin 9. Video
signals are clamped with top sync on 1.28 V, and are
sliced at 1.4 V. This results in a fixed absolute slicing level
of 120 mV related to top sync.

DC-coupled TTL sync signals are also sliced at 1.4 V,
however with the clamping circuit in current limitation.
The polarity of the separated sync is detected by internal
integration of the signal, then the polarity is corrected.

The polarity information is fed to the VGA mode detector.
The corrected sync is input signal for the vertical sync
integrator and the PLL1 stage.

Vertical sync separator, polarity correction and
vertical sync integrator

DC-coupled vertical TTL sync signals may be applied to
pin 10. They are sliced at 1.4 V. The polarity of the
separated sync is detected by internal integration, then
polarity is corrected. The polarity information is fed to the
VGA mode detector. If pin 10 is not used, it must be
connected to ground.

The separated V

i(sync)

signal from pin 10, or the integrated

composite sync signal from pin 9 (TTL or video) triggers
directly the vertical oscillator.

VGA mode detector and mode output

The three standard VGA modes and a 4th not fixed mode
are decoded by the polarities of the horizontal and the
vertical sync input signals. An external resistor (from V

pin 7) is necessary to match this function. In all three VGA
modes the correct amplitudes are activated. The presence
of the 4th mode is indicated by HIGH on pin 7. This signal
can be used externally to switch any horizontal or vertical
parameters.

VGA mode detector input

For multi-frequency operation the voltage on pin 7 must be
externally forced to a level of <50 mV. Vertical amplitude
pre-settings for VGA are then inhibited. The delay time
between vertical trigger pulse and the start of vertical
deflection changes from 575 to 300

s (575

s is needed

for VGA). The vertical amplitude then remains constant in
a frequency range from 50 to 110 Hz.

Clamping and blanking generator

A combined clamping and blanking pulse is available on
pin 8 (suitable for the video preamplifier TDA4880).
The lower level of 2.1 V can be the blanking signal derived
from line flyback, or the vertical blanking pulse from the
internal vertical oscillator.

Vertical blanking equals to the delay between vertical sync
and start of vertical scan. By this, an optimum blanking is
achieved for VGA/XGA as well as for multi-frequency
operation (selectable via pin 7).

The upper level of 3.9 V is the horizontal clamping pulse
with internally fixed pulse width of 1

s. A mono flop, which

is triggered by the trailing edge of the horizontal sync
pulse, generates this pulse.

PLL1 phase detector

The phase detector is a standard one using switched
current sources. The middle of the sync is compared with
a fixed point of the oscillator sawtooth voltage. The PLL
filter is connected to pin 17.

Horizontal oscillator

This oscillator is a relaxation type oscillator. Its frequency
is determined mainly by the capacitor on pin 19.
A frequency range of one octave is achieved by the current
on pin 18. The

1 control voltage from pin 17 is fed via a

buffer amplifier and an attenuator to the current reference
pin 18 to achieve a high DC loop gain. Therefore, changes
in frequency will not affect the phase relationship between
horizontal sync pulses and line flyback pulses.

PLL2 phase detector

This phase detector is similar to the PLL1 phase detector.
Line flyback signals (pin 2) are compared with a fixed point
of the oscillator sawtooth voltage. Delays in the horizontal
deflection circuit are compensated by adjusting the phase
relationship between horizontal sync and horizontal output
pulses.

A certain amount of phase adjustments is possible by
injecting a DC current from an external source into the
PLL2 filter capacitor on pin 20.

1997 Jun 05

Philips Semiconductors

Product specification

Horizontal and vertical deflection controller
for VGA/XGA and multi-frequency monitors

TDA4850

Horizontal driver

This open-collector output stage (pin 3) can directly drive
an external driver transistor. The saturation voltage is
300 mV at 20 mA. To protect the line deflection transistor,
the horizontal output stage does not conduct at V

< 6.4 V

(pin 1).

Vertical oscillator and amplitude control

This stage is designed for fast stabilization of the vertical
amplitude after changes in sync conditions.
The free-running frequency f

is determined by the values

of R

VOS

and C

VOS

. The recommended values should be

altered marginally only to preserve the excellent linearity
and noise performance. The vertical drive currents I

and

are in relation to the value of R

VOS

. Therefore, the

oscillator frequency must be determined only by C

VOS

pin 16.

10.8

VOS

----------------------------------------------------

To achieve a stabilized amplitude the free-running
frequency f

(without adjustment) must be lower than the

lowest occurring sync frequency. The contributions shown
in Table 1 can be assumed.

Table 1

Calculation of f

total spread

Result for 50 to 110 Hz application:

CONTRIBUTING ELEMENTS

Minimum frequency offset between f

and

the lowest trigger frequency

Spread of IC

Spread of R (22 k

)

Spread of C (0.1

Total

50 Hz

1.19

---------------

42 Hz

Table 2

VGA modes

MODE

HORIZONTAL/VERTICAL

SYNC POLARITY

HORIZONTAL

FREQUENCY

(kHz)

VERTICAL

FREQUENCY

(Hz)

NUMBER OF

ACTIVE LINES

MODE

OUTPUT PIN 7

31.45

350

LOW

31.45

400

LOW

31.45

480

LOW

+/+

fixed by external circuitry

HIGH

1997 Jun 05

Philips Semiconductors

Product specification

Horizontal and vertical deflection controller
for VGA/XGA and multi-frequency monitors

TDA4850

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. Equivalent to discharging a 200 pF capacitor through a 0

series resistor.

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

supply voltage (pin 1)

0.5

+16

3,7

voltage on pins 3 and 7

0.5

+16

voltage on pin 8

0.5

voltage on pins 5, 6, 9, 10, 13,
14 and 18

0.5

+6.5

current on pin 2

current on pin 3

100

current on pin 7

current on pin 8

amb

operating ambient temperature

junction temperature

150

stg

storage temperature

+150

esd

electrostatic handling for all pins

note 1

300

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th(j-a)

thermal resistance from junction to ambient

in free air

K/W

1997 Jun 05

Philips Semiconductors

Product specification

Horizontal and vertical deflection controller
for VGA/XGA and multi-frequency monitors

TDA4850

CHARACTERISTICS

= 12 V; T

amb

= 25

C; measurements taken in Fig.6; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

supply voltage (pin 1)

9.2

supply current

Internal reference voltage

ref

internal reference voltage

6.0

6.25

6.5

temperature coefficient

amb

= 20 to 100

PSRR

power supply ripple rejection

f = 1 kHz sine wave

f = 1 MHz sine wave

supply voltage (pin 1) to ensure all internal
reference voltages

9.2

Composite sync input (AC-coupled; V

= 5 V)

i sync

sync amplitude of video input signal (pin 9)

sync on green;
R

= 50

300

top sync clamping level

1.1

1.32

1.5

slicing level above top sync level

120

150

allowed source resistance for 7% duty cycle V

i sync

> 200 mV

1.5

differential input resistance

during sync

charging current of coupling capacitor

> 1.5 V

1.7

2.6

3.4

int

vertical sync integration time to generate
sync pulse

Horizontal sync input (DC-coupled, TTL-compatible)

i sync

sync input signal (peak value; pin 9)

1.7

slicing level

1.2

1.4

1.6

minimum pulse width

700

, t

rise time and fall time

500

input current

= 0.8 V

200

= 5.5 V

Automatic horizontal polarity switch (H-sync on pin 9)

p H

horizontal sync pulse width related to t

(duty cycle for automatic polarity correction)

delay time for changing sync polarity

0.3

1.8

Vertical sync input (DC-coupled, TTL-compatible; V-sync on pin 10)

i sync

sync input signal (peak value; pin 10)

1.7

slicing level

1.2

1.4

1.6

input current

0 < V

< 5.5 V

p V

maximum vertical sync pulse width for
automatic vertical polarity switch

300

1997 Jun 05

Philips Semiconductors

Product specification

Horizontal and vertical deflection controller
for VGA/XGA and multi-frequency monitors

TDA4850

Horizontal mode detector output (VGA mode)

output saturation voltage LOW
(for modes 1, 2 and 3)

= 6 mA

0.275

0.33

output voltage HIGH

mode 4

load current to force VGA mode-dependent
vertical and parabola amplitudes

modes 1, 2 and 3

output current

mode 4

VGA/multi-frequency mode switch

input voltage LOW to force
multi-frequency mode

Horizontal comparator PLL1

upper control voltage limitation

5.0

lower control voltage limitation

1.2

control current

see Fig.3

300

Horizontal oscillator

osc

centre frequency

= 12 k

(pin 18);

= 2.2 nF (pin 19)

31.45

kHz

osc

deviation of centre frequency

3.0

temperature coefficient

150

relative holding/catching range

6.5

7.3

external oscillator resistor

voltage at reference current input (pin 18)

PLL1 and PLL2 locked;
V

ref

= 6.25 V

3.125

control voltage

205

Horizontal PLL2; see Fig.3

upper clamping level of flyback input

= 6 mA

5.5

lower clamping level of flyback input

1 mA

0.75

H-flyback slicing level

3.0

input current

H-scan; V

< 0.9 V

0.5

H-flyback; V

> 1.8 V

0.2

delay between middle of sync and middle of
H-flyback related to t

3.2

upper control voltage limitation

4.6

lower control voltage limitation

1.6

control current

200

t/t

PLL2 control range related to t

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1997 Jun 05

Philips Semiconductors

Product specification

Horizontal and vertical deflection controller
for VGA/XGA and multi-frequency monitors

TDA4850

Horizontal output (open-collector); see Fig.3

output voltage LOW

= 20 mA

0.3

= 60 mA

0.8

duty cycle

threshold to activate too low supply voltage
protection

horizontal output off

5.3

horizontal output on

5.6

Horizontal clamping/blanking generator output; see Fig.3

output voltage LOW

H and V scanning

0.9

blanking output voltage

internal V blanking

1.8

2.1

2.4

external H blanking

1.8

2.1

2.4

clamping output voltage

H-sync on pin 9

3.5

3.9

4.3

internal sink current for all output levels

H and V scanning

2.3

2.9

3.5

clamping pulse start

with end of H-sync

clp

clamping pulse width

0.8

1.0

1.2

steepness of rise and fall times

ns/V

Vertical oscillator (V

ref

= 6.25 V)

vertical free-running frequency

= 22 k

;

= 0.1

43.3

nominal vertical sync range

no f

adjustment

110

voltage on pin 15

= 22 k

2.8

3.0

3.2

delay between sync pulse and start of
vertical scan

measured on pin 8

in VGA/XGA mode, activated by an
external resistor on pin 7

500

575

650

in multi-frequency mode

< 50 mV

240

300

360

control current for amplitude control

200

capacitor for amplitude control

0.33

Vertical differential output; see Fig.4

differential output current between
pins 5 and 6 (peak-to-peak value)

mode 3; I

135

= 22 k

0.9

1.0

1.1

maximum offset current error

= 1 mA

2.5

maximum linearity error

1.5

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1997 Jun 05

Philips Semiconductors

Product specification

Horizontal and vertical deflection controller
for VGA/XGA and multi-frequency monitors

TDA4850

Notes to the Characteristics

t relative to value of mode 3.

2. Parabola amplitude tracks with mode-dependent vertical amplitude but not with vertical amplitude adjustment.

Tracking can be achieved by a resistor from vertical amplitude potentiometer to pin 14.

Vertical amplitude adjustment (in percent of output signal)

input voltage

5.0

adjustment current

o max

(100%)

110

120

135

o min

(typically 58%)

VGA mode-dependent pre-settings
activated by an external resistor on pin 7

note 1; see Table 2

mode 1

116.1

116.8

117.5

mode 2

102.0

102.2

102.5

mode 3

100

mode 4

100

multi-frequency operation (VGA operation
disabled)

< 50 mV

100

E/W output; note 2

bottom output signal during mid-scan
(pin 11)

internally stabilized

1.05

1.2

1.35

top output signal during flyback

4.1

4.35

4.6

temperature coefficient of output signal

250

E/W amplitude adjustment (parabola); see Fig.4

input voltage (pin 14)

5.0

adjustment current

100% parabola

110

120

135

typically 28% parabola

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1997 Jun 05

Philips Semiconductors

Product specification

Horizontal and vertical deflection controller
for VGA/XGA and multi-frequency monitors

TDA4850

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

Soldering by dipping or by wave

The maximum permissible temperature of the solder is
260

C; solder at this temperature must not be in contact

with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg max

). If the

printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

Repairing soldered joints

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300

C it may remain in

contact for up to 10 seconds. If the bit temperature is
between 300 and 400

C, contact may be up to 5 seconds.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors a worldwide company

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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
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Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381

Middle East: see Italy

Printed in The Netherlands

547047/1200/03/pp20

Date of release: 1997 Jun 05

Document order number:

9397 750 02184

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA4850