1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

FEATURES

Concept features

Full Horizontal (H) plus Vertical (V) autosync capability

Completely DC controllable for analog and digital
concepts

Excellent geometry control functions (e.g. automatic
correction of East-West (EW) parabola during
adjustment of vertical size and vertical shift)

Flexible Switched Mode Power Supply (SMPS) function
block for feedback and feed forward converters

Horizontal focus parabola with amplitude control

X-ray protection

Start-up and switch-off sequence for safe operation of
all power components

Very good vertical linearity

Internal supply voltage stabilization

SDIP32 package.

Synchronization inputs

Can handle all sync signals (Horizontal, Vertical,
Composite and Sync-on-video)

Combined output for video clamping, vertical blanking
and protection blanking.

Horizontal section

Extremely low jitter

Frequency locked loop for smooth catching of line
frequency

Simple frequency preset of f

min

and f

max

by external

resistors

DC controllable wide range linear picture position

Soft start for horizontal driver.

Vertical section

Vertical amplitude independent of frequency

Automatic correction of picture height for VGA350 and
VGA400 modes

DC controllable picture height, picture position and
S-correction

Differential current outputs for DC coupling to vertical
booster.

EW section

Output for DC adjustable EW parabola with smoothed
top

DC controllable picture width and trapezium correction

Optional tracking of EW parabola with line frequency

Prepared for additional DC controls of vertical linearity,
EW-corner, EW pin balance, EW parallelogram, vertical
focus by extended application.

GENERAL DESCRIPTION

The TDA4855 is a high performance and efficient solution
for autosync monitors. The concept is fully DC controllable
and can be used in applications with a microcontroller and
stand-alone in rock bottom solutions.

The TDA4855 provides synchronization processing, H + V
synchronization with full autosync capability, and very
short settling times after mode changes. External power
components are given a great deal of protection. The IC
generates the drive waveforms for DC-coupled vertical
boosters such as TDA486X and TDA8351.

The TDA4855 provides extended functions e.g. as a
flexible SMPS block and an extensive set of geometry
control facilities, providing excellent picture quality.

Together with the Philips TDA488X video processor family
a very advanced system solution is offered.

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

BLOCK DIAGRAM

handbook, full pagewidth

VERTICAL

SYNC

INPUT

POLARITY

CORRECTION

VERTICAL

OSCILLATOR

AGC

VERTICAL POSITION

VERTICAL SIZE

VERTICAL

OUTPUT STAGE

S-CORRECTION

SUPPLY

AND

REFERENCE

VERTICAL SYNC

INTEGRATOR

VGA

PRESETS

PARABOLA

VIDEO CLAMPING PULSE

VERTICAL BLANKING

FOCUS

PLL1

PLL2

SYNC INPUT

POLARITY

CORRECTION

HORIZONTAL

OSCILLATOR

FREQUENCY DETECTOR

COINCIDENCE DETECTOR

X-RAY

PROTECTION

HORIZONTAL

OUTPUT

STAGE

CONTROL

APPLICATION

39 k

27 k

220

47 nF

1.5

220 k

39 k

220 k

39 k

220 k

39 k

220 k

39 k

220 k

100

VPOS

VAMP

VSCOR

100

VCAP

VAGC

VREF

VCAP

VAGC

VOUT1

VOUT2

parabola

horizontal

size

EWDRV

XRAY

BDRV

BSENS

BOP

BIN

trapeziun

EWPAR

EWWID

EWTRP

HDRV

HFLB

12 nF

10 nF

HREF

HPLL2

HCAP

HREF

HBUF

(1)

(3)

(2)

HPLL1

HBUF

HPOS

HSYNC

(TTL level)

FOCUS

HFLB

CLBL

VSYNC

(TTL level)

9.2 to 16 V

SGND

PGND

(video)

H-focus

parabola

clamping

blanking

TDA4855

HORIZONTAL/

COMPOSITE

MBG550

Fig.1 Block diagram and application circuit.

(1)

See calculation of f

range.

(2)

See note

3 of Chapter

"Characteristics".

(3)

See Figs

and

13.

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

PINNING

SYMBOL PIN

DESCRIPTION

HFLB

horizontal flyback input

XRAY

X-ray protection input

BOP

B+ control OTA output;
comparator input

BSENS

B+ control comparator input/output

BIN

B+ control OTA input

BDRV

B+ control driver output

HDRV

horizontal driver output

PGND

power ground

supply voltage

FOCUS

horizontal focus parabola input/output

EWDRV

EW parabola output

VOUT2

vertical output 2 (ascending sawtooth)

VOUT1

vertical output 1 (descending
sawtooth)

VSYNC

vertical synchronization input/output
(TTL level)

HSYNC

horizontal/composite synchronization
input (TTL level or sync-on-video)

CLBL

video clamping pulse/vertical blanking
and protection output

VPOS

vertical shift input

VAMP

vertical size input

VSCOR

vertical S-correction input

EWTRP

EW trapezium correction input

EWPAR

EW parabola amplitude input

VAGC

external capacitor for vertical
amplitude control

VREF

external resistor for vertical oscillator

VCAP

external capacitor for vertical oscillator

SGND

signal ground

HPLL1

external filter for PLL1

HBUF

buffered f/v voltage output

HREF

reference current for horizontal
oscillator

HCAP

external capacitor for horizontal
oscillator

HPOS

horizontal shift input

HPLL2

external filter for PLL2/soft start

EWWID

horizontal size input

Fig.2 Pin configuration.

handbook, halfpage

TDA4855

MBG549

HFLB

XRAY

BOP

BSENS

BIN

BDRV

HDRV

PGND

VCC

FOCUS

EWDRV

VOUT2

VOUT1

VSYNC

HSYNC

CLBL

EWWID

HPLL2

HPOS

HCAP

HREF

HBUF

HPLL1

SGND

VCAP

VREF

VAGC

EWPAR

EWTRP

VSCOR

VAMP

VPOS

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

FUNCTIONAL DESCRIPTION

Horizontal sync separator and polarity correction

HSYNC (pin 15) is the input for horizontal synchronization
signals, which can be DC-coupled TTL signals (horizontal
or composite sync) and AC-coupled negative-going video
sync signals. Video syncs are clamped to 1.28 V and
sliced at 1.4 V. This results in a fixed absolute slicing level
of 120 mV related to sync top.

For DC-coupled TTL signals the input clamping current is
limited. The slicing level for TTL signals is 1.4 V.

The separated sync signal (either video or TTL) is
integrated on an internal capacitor to detect and normalize
the sync polarity.

Normalized horizontal sync pulses are used as input
signals for the vertical sync integrator, the PLL1 phase
detector and the frequency-locked loop.

Vertical sync integrator

Normalized composite sync signals from HSYNC are
integrated on an internal capacitor in order to extract
vertical sync pulses. The integration time is dependent on
the horizontal oscillator reference current at HREF
(pin 28). The integrator output directly triggers the vertical
oscillator. This signal is available at VSYNC (normally
vertical sync input; pin 14), which is used as an output in
this mode.

Vertical sync slicer and polarity correction

Vertical sync signals (TTL) applied to VSYNC (pin 14) are
sliced at 1.4 V. The output signal of the sync slicer is
integrated on an internal capacitor to detect and normalize
the sync polarity.

If a composite sync signal is detected at HSYNC, VSYNC
is used as output for the integrated vertical sync (e.g. for
power saving applications).

Video clamping/vertical blanking generator

The video clamping/vertical blanking signal at CLBL
(pin 16) is a two-level sandcastle pulse which is especially
suitable for video ICs such as the TDA488X family, but
also for direct applications in video output stages.

The upper level is the video clamping pulse, which is
triggered by the trailing edge of the horizontal sync pulse.
The width of the video clamping pulse is determined by an
internal monoflop.

The lower level of the sandcastle pulse is the vertical
blanking pulse, which is derived directly from the internal
oscillator waveform. It is started by the vertical sync and
stopped with the start of the vertical scan. This results in
optimum vertical blanking.

Blanking will be activated continuously, if one of the
following conditions is true:

No horizontal flyback pulses at HFLB (pin 1)

X-ray protection is activated

Soft start of horizontal drive (voltage at HPLL2 (pin 31)
is low)

Supply voltage at V

(pin 9) is low (see Fig.14)

PLL1 is unlocked while frequency-locked loop is in
search mode.

Blanking will not be activated if the horizontal sync
frequency is below the valid range or there are no sync
pulses available.

VGA mode detector

The polarities of horizontal and vertical sync are internally
detected in order to provide an automatic adjustment of
vertical size for VGA350 and VGA400 modes.
These automatic VGA presets are activated only if the
current ratio I

HBUF

HREF

exceeds a fixed value

(see Chapter "Characteristics"). Thus it is possible to
disable this function for a part of the frequency range or
even completely.

Table 1

VGA modes

MODE

HORIZONTAL/VERTICAL SYNC

POLARITY

VGA350

VGA400

VGA480

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

Frequency-locked loop

The frequency-locked loop can lock the horizontal
oscillator over a wide frequency range. This is achieved by
a combined search and PLL operation. The frequency
range is preset by two external resistors and the

recommended maximum ratio is

Larger ranges are possible by extended applications.

Without a horizontal sync signal the oscillator will be
free-running at f

min

. Any change of sync conditions is

detected by the internal coincidence detector. A deviation
of more than 4% between horizontal sync and oscillator
frequency switches the horizontal section into search
mode. This means that PLL1 control currents are switched
off immediately. Then the internal frequency detector
starts tuning the oscillator. Very small DC currents at
HPLL1 (pin 26) are used to perform this tuning with a well
defined change rate. When coincidence between
horizontal sync and oscillator frequency is detected, the
search mode is replaced by a normal PLL operation.
This operation ensures a smooth tuning and avoids fast
changes of horizontal frequency during catching.

In this concept it is not allowed to load HPLL1.
The frequency dependent voltage at this pin is fed
internally to HBUF (pin 27) via a sample-and-hold and
buffer stage. The sample-and-hold stage removes all
disturbances caused by horizontal sync or composite
vertical sync from the buffered voltage. An external
resistor from HBUF to HREF defines the frequency range.

See also hints for locking procedure in note 3 of
Chapter "Characteristics".

PLL1 phase detector

The phase detector is a standard type using switched
current sources. It compares the middle of horizontal sync
with a fixed point on the oscillator sawtooth voltage.
The PLL1 loop filter is connected to HPLL1 (pin 26).

Horizontal oscillator

The horizontal oscillator is of the relaxation type and
requires a capacitor of 10 nF at HCAP (pin 29).
For optimum jitter performance the value of 10 nF must not
be changed.

The maximum oscillator frequency is determined by a
resistor from HREF to ground. A resistor from HREF to
HBUF defines the frequency range.

min

max

-----------

3.5

--------

The reference current at HREF also defines the integration
time constant of the vertical sync integration.

Calculation of line frequency range

First the oscillator frequencies f

min

and f

max

have to be

calculated. This is achieved by adding the spread of the
relevant components to the highest and lowest sync
frequencies f

S(min)

and f

S(max)

. The oscillator is driven by

the difference of the currents in R

HREF

and R

HBUF

. At the

highest oscillator frequency R

HBUF

does not contribute to

the spread. The spread will increase towards lower
frequencies due to the contribution of R

HBUF

. It is also

dependent on the ratio

The following example is a 31.45 to 64 kHz application:

Table 2

Calculation of total spread

Thus the typical frequency range of the oscillator in this
example is:

The resistors R

HREF

and R

HBUF

can be calculated with the

following formulae:

Where:

spread of:

for f

max

for f

min

HCAP

HREF

, R

HBUF

(2.3

Total

8.69%

S max

(

)

S min

(

)

-------------------

S max

(

)

S min

(

)

-------------------

64 kHz

31.45 kHz

---------------------------

2.04

max

S max

(

)

1.06

67.84 kHz

min

S min

(

)

1.087

------------------

28.93 kHz

HREF

kHz

max

kHz

[

]

--------------------------------------

1.091 k

HBUF

HREF

1.19

---------------------------------------------

2.26 k

max

min

-----------

2.35

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

The spread of f

min

increases with the frequency

ratio

For higher ratios this spread can be reduced by using
resistors with less tolerances.

PLL2 phase detector

The PLL2 phase detector is similar to the PLL1 detector
and compares the line flyback pulse at HFLB (pin 1) with
the oscillator sawtooth voltage. The PLL2 detector thus
compensates for the delay in the external horizontal
deflection circuit by adjusting the phase of the HDRV
(pin 7) output pulse.

The phase between horizontal flyback and horizontal sync
can be controlled at HPOS (pin 30).

If HPLL2 is pulled to ground, horizontal output pulses,
vertical output currents and B+ control driver pulses are
inhibited. This means, HDRV (pin 7), BDRV (pin 6)
VOUT1 (pin 13) and VOUT2 (pin 12) are floating in this
state. PLL2 and the frequency-locked loop are disabled,
and CLBL (pin 16) provides a continuous blanking signal.

This option can be used for soft start, protection and
power-down modes. When the HPLL2 voltage is released
again, an automatic soft start sequence will be performed
(see Fig.15).

The soft start timing is determined by the filter capacitor at
HPLL2 (pin 31), which is charged with an constant current
during soft start. In the beginning the horizontal driver
stage generates very small output pulses. The width of
these pulses increases with the voltage at HPLL2 until the
final duty factor is reached. At this point BDRV (pin 6),
VOUT1 (pin 13) and VOUT2 (pin 12) are re-enabled.
The voltage at HPLL2 continues to rise until PLL2 enters
its normal operating range. The internal charge current is
now disabled. Finally PLL2 and the frequency-locked loop
are enabled, and the continuous blanking at CLBL is
removed.

Horizontal phase adjustment

HPOS (pin 30) provides a linear adjustment of the relative
phase between the horizontal sync and oscillator
sawtooth. Once adjusted, the relative phase remains
constant over the whole frequency range.

Application hint: HPOS is a current input, which provides
an internal reference voltage while I

HPOS

is in the specified

adjustment current range. By grounding HPOS the
symmetrical control range is forced to its centre value,

S max

(

)

S min

(

)

-------------------

therefore the phase between horizontal sync and
horizontal drive pulse is only determined by PLL2.

Output stage for line drive pulses

An open collector output stage allows direct drive of an
inverting driver transistor because of a low saturation
voltage of 0.3 V at 20 mA. To protect the line deflection
transistor, the output stage is disabled (floating) for low
supply voltage at V

(see Fig.14).

The duty factor of line drive pulses is slightly dependent on
the actual line frequency. This ensures optimum drive
conditions over the whole frequency range.

X-ray protection

The x-ray protection input XRAY (pin 2) provides a voltage
detector with a precise threshold. If the input voltage at
XRAY exceeds this threshold for a certain time, an internal
latch switches the IC into protection mode. In this mode
several pins are forced into defined states:

Horizontal output stage (HDRV) is floating

B+ control driver stage (BDRV) is floating

Vertical output stages (VOUT1 and VOUT2) are floating

CLBL provides a continuous blanking signal

The capacitor connected to HPLL2 (pin 31) is
discharged.

To reset the latch and return to normal operation, V

has

to be temporarily switched off.

Vertical oscillator and amplitude control

This stage is designed for fast stabilization of vertical
amplitude after changes in sync frequency conditions.
The free-running frequency f

osc(V)

is determined by the

resistor R

VREF

connected to pin 23 and the capacitor

VCAP

connected to pin 24. The value of R

VREF

is not only

optimized for noise and linearity performance in the whole
vertical and EW section, but also influences several
internal references. Therefore the value of R

VREF

must not

be changed. Capacitor C

VCAP

should be used to select the

free-running frequency of the vertical oscillator in
accordance with the following formula:

osc V

( )

10.8

VREF

VCAP

-----------------------------------------------------------

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

To achieve a stabilized amplitude the free-running
frequency f

osc(V)

, without adjustment, should be at least

10% lower than the minimum trigger frequency.
The contributions shown in Table 3 can be assumed.

Table 3

Calculation of f

osc(V)

total spread

Result for 50 to 110 Hz application:

Application hint: VAGC (pin 22) has a high input
impedance during scan, thus the pin must not be loaded
externally. Otherwise non-linearities in the vertical output
currents may occur due to the changing charge current
during scan.

Application hint: The full vertical sync range of 1 : 2.5 can
be made usable by incorporating an adjustment of the
free-running frequency. Also the complete sync range can
be shifted to higher frequencies (e.g. 70 to 160 Hz) by
reducing the value of C

VCAP

Adjustment of vertical size, vertical shift and
S-correction

VPOS (pin 17) is the input for the DC adjustable vertical
picture shift. This pin provides a phase shift at the
sawtooth output VOUT1 and VOUT2 (pins 13 and 12) and
the EW drive output EWDRV (pin 11) in such a way, that
the whole picture moves vertically while maintaining the
correct geometry.

The amplitude of the differential output currents at VOUT1
and VOUT2 can be adjusted via input VAMP (pin 18).
This can be a combination of a DC adjustment and a
dynamic waveform modulation.

VSCOR (pin 19) is used to adjust the amount of vertical
S-correction in the output signal.

The adjustments for vertical size and vertical shift also
affect the waveforms of the EW parabola and the vertical
S-correction. The result of this interaction is that no

Contributing elements:

Minimum frequency offset between f

osc(V)

and lowest trigger frequency

10%

Spread of IC

Spread of R

VREF

Spread of C

VCAP

Total

19%

osc V

( )

50 Hz

1.19

---------------

42 Hz

readjustment of these parameters is necessary after an
adjustment of vertical picture size or position.

Application hint: VPOS is a current input, which provides
an internal reference voltage while I

VPOS

is in the specified

adjustment current range. By grounding VPOS (pin 17) the
symmetrical control range is forced to its centre value.

Application hint: VSCOR is a current input at 5 V.
Superimposed on this level is a very small positive-going
vertical sawtooth, intended to modulate an external
long-tailed transistor pair. This enables further optional DC
controls of functions which are not directly accessible such
as vertical tilt or vertical linearity (see Fig.17).

EW parabola (including horizontal size and trapezium
correction)

EWDRV (pin 11) provides a complete EW drive waveform.
EW parabola amplitude, DC shift (horizontal size) and
trapezium correction can be controlled via separate DC
inputs.

EWPAR (pin 21) is used to adjust the parabola amplitude.
This can be a combination of a DC adjustment and a
dynamic waveform modulation.

The EW parabola amplitude also tracks with vertical
picture size. The parabola waveform itself tracks with the
adjustment for vertical picture shift (VPOS).
Additional effort has been taken to generate a smooth
waveform at the top of the parabola. This is to avoid ringing
in the horizontal output stage.

EWWID (pin 32) offers two modes of operation:

1. Mode 1

Horizontal size is DC controlled via EWWID (pin 32)
and causes a DC shift at the EWDRV output. Also the
complete waveform is multiplied internally by a signal
proportional to the line frequency (which is detected
via the current at HREF (pin 28). This mode is to be
used for driving EW modulator stages which require a
voltage proportional to the line frequency.

2. Mode 2

EWWID (pin 32) is grounded. Then EWDRV is no
longer multiplied by the line frequency. The DC
adjustment for horizontal size must be added to the
input of the B+ control amplifier BIN (pin 5). This mode
is to be used for driving EW modulators which require
a voltage independent of the line frequency.

EWTRP (pin 20) is used to adjust the amount of trapezium
correction in the EW drive waveform.

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

Application hint: EWTRP (pin 20) is a current input at
5 V. Superimposed on this level is a very small vertical
parabola with positive tips, intended to modulate an
external long-tailed transistor pair. This enables further
optional DC controls of functions which are not directly
accessible such as EW-corner, vertical focus or EW pin
balance (see Fig.17).

Application hint: By grounding EWTRP (pin 20) the
symmetrical control range is forced to its centre value.

Dynamic focus section

This section generates a horizontal parabola waveform for
dynamic focus applications. The amplitude of this parabola
is internally stabilized, thus it is independent from the line
frequency.

FOCUS (pin 10) is designed as a current sink.
The peak-to-peak amplitude of the output current can be
adjusted by forcing the voltage at pin 10 to a value
between 1 and 4 V.

B+ control function block

The B+ control function block of the ASDC consists of an
Operational Transconductance Amplifier (OTA), a voltage
comparator, a flip-flop and a discharge circuit.
This configuration allows easy applications for different
B+ control concepts.

ENERAL DESCRIPTION

The non-inverting input of the OTA is connected internally
to a high precision reference voltage. The inverting input is
connected to BIN (pin 5). An internal clamping circuit limits
the maximum positive output voltage of the OTA.
The output itself is connected to BOP (pin 3) and to the
inverting input of the voltage comparator.
The non-inverting input of the voltage comparator can be
accessed via BSENS (pin 4).

B+ drive pulses are generated by an internal flip-flop and
fed to BDRV (pin 6) via an open collector output stage.
This flip-flop will be set at the rising edge of the signal at
HDRV (pin 7). The falling edge of the output signal at
BDRV has a defined delay of t

d(BDRV)

to the rising edge of

the HDRV pulse. When the voltage at BSENS exceeds the
voltage at BOP, the voltage comparator output resets the
flip-flop, and therefore the open collector stage at BDRV is
floating again.

An internal discharge circuit allows a well defined
discharge of capacitors at BSENS. BDRV is active at a low
level output voltage (see Figs 12 and 13), thus it requires
an external inverting driver stage.

The B+ function block can be used for B+ deflection
modulators in either of two modes:

Feedback mode (see Fig.12)

In this application the OTA is used as an error amplifier
with a limited output voltage range. The flip-flop will be
set at the rising edge of the signal at HDRV. A reset will
be generated when the voltage at BSENS taken from
the current sense resistor exceeds the voltage at BOP.

If no reset is generated within a line period, the rising
edge of the next HDRV pulse forces the flip-flop to reset.
The flip-flop is set immediately after the voltage at
BSENS has dropped below the threshold voltage
V

RESTART(BSENS)

Feed forward mode (see Fig.13)

This application uses an external RC combination at
BSENS to provide a pulse width which is independent
from the horizontal frequency. The capacitor is charged
via an external resistor and discharged by the internal
discharge circuit. For normal operation the discharge
circuit is activated when the flip-flop is reset by the
internal voltage comparator. Now the capacitor will be
discharged with a constant current until the internally
controlled stop level V

STOP(BSENS)

is reached. This level

will be maintained until the rising edge of the next HDRV
pulse sets the flip-flop again and disables the discharge
circuit.

If no reset is generated within a line period, the rising
edge of the next HDRV pulse automatically starts the
discharge sequence and resets the flip-flop (Fig.13).
When the voltage at BSENS reaches the threshold
voltage V

RESTART(BSENS)

, the discharge circuit will be

disabled automatically and the flip-flop will be set
immediately. This behaviour allows a definition of the
maximum duty cycle of the B+ control drive pulse by the
relationship of charge current to discharge current.

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

Supply voltage stabilizer, references and protection

The ASDC provides an internal supply voltage stabilizer
for excellent stabilization of all internal references.
An internal gap reference especially designed for
low-noise is the reference for the internal horizontal and
vertical supply voltages. All internal reference currents and
drive current for the vertical output stage are derived from
this voltage via external resistors.

A special protection mode has been implemented in order
to protect the deflection stages and the picture tube during
start-up, shut-down and fault conditions. This protection
mode can be activated as shown in Table 4.

Table 4

Activation of protection mode

When protection mode is active, several pins of the ASDC
are forced into a defined state:

HDRV (horizontal driver output) is floating

BDRV (B+ control driver output) is floating

VOUT1 and VOUT2 (vertical outputs) are floating

CLBL provides a continuous blanking signal

The capacitor at HPLL2 is discharged.

If the protection mode is activated via the supply voltage at
pin 9, all these actions will be performed in a well defined
sequence (see Fig.14). For activation via X-ray protection
or HPLL2 all actions will occur simultaneously.

ACTIVATION

RESET

Low supply voltage at pin 9

increase supply voltage

X-ray protection XRAY (pin 2)
triggered

remove supply voltage

HPLL2 (pin 31) pulled to
ground

release pin 31

The return to normal operation is performed in accordance
with the start-up sequence in Fig.14a, if the reset was
caused by the supply voltage at pin 9. The first action with
increasing supply voltage is the activation of continuous
blanking at CLBL. When the threshold for activation of
HDRV is passed, an internal current begins to charge the
external capacitor at HPLL2 and a PLL2 soft start
sequence is performed (see Fig.15). In the beginning of
this phase the horizontal driver stage generates very small
output pulses. The width of these pulses increases with the
voltage at HPLL2 until the final duty cycle is reached.
Then the PLL2 voltage passes the threshold for activation
of BDRV, VOUT1 and VOUT2.

For activation of these pins not only the PLL2 voltage, but
also the supply voltage must have passed the appropriate
threshold. A last pair of thresholds has to be passed by
PLL2 voltage and supply voltage before the continuous
blanking is finally removed, and the operation of PLL2 and
frequency-locked loop is enabled.

A return to the normal operation by releasing the voltage
at HPLL2 will lead to a slightly different sequence. Here the
activation of all functions is influenced only by the voltage
at HPLL2 (see Fig.15).

Application hint: Internal discharge of the capacitor at
HPLL2 will only be performed, if the protection mode was
activated via the supply voltage or X-ray protection.

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); all voltages measured with respect to ground.

Note

1. Machine model: 200 pF, 25

, 2.5

H; human body model: 100 pF, 1500

, 7.5

THERMAL CHARACTERISTICS

QUALITY SPECIFICATION

In accordance with

"URF-4-2-59/601"; EMC emission/immunity test in accordance with "DIS 1000 4.6" (IEC 801.6)

Note

1. Tests are performed with application reference board. Tests with other boards will have different results.

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

supply voltage

0.5

+16

I(n)

input voltages

BIN

0.5

+6.0

HSYNC, VPOS, VAMP, VSCOR, VREF, HREF and HPOS

0.5

+6.5

XRAY

0.5

+8.0

O(n)

output voltages

VOUT1 and VOUT2

0.5

+6.5

BDRV and HDRV

0.5

+16

I/O(n)

input/output voltages

BOP and BSENS

0.5

+6.0

FOCUS and VSYNC

0.5

+6.5

HDRV

horizontal driver output current

100

HFLB

horizontal flyback input current

+10

CLBL

video clamping pulse/vertical blanking output current

BOP

B+ control OTA output current

BDRV

B+ control driver output current

EWDRV

EW driver output current

amb

operating ambient temperature

junction temperature

150

stg

storage temperature

+150

esd

electrostatic discharge for all pins (note 1)

machine model

400

+400

human body model

3000

+3000

SYMBOL

PARAMETER

VALUE

UNIT

th j-a

thermal resistance from junction to ambient in free air

K/W

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

EMC

emission test

note 1

1.5

immunity test

note 1

2.0

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

CHARACTERISTICS

= 12 V; T

amb

= 25

C; peripheral components in accordance with Fig.1; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Horizontal sync separator

NPUT CHARACTERISTICS FOR DC

COUPLED

TTL

SIGNALS

[HSYNC (

15)]

DC(HSYNC)

sync input signal voltage

1.7

slicing voltage level

1.2

1.4

1.6

r(HSYNC)

rise time of sync pulse

500

f(HSYNC)

fall time of sync pulse

500

W(HSYNC)

minimum width of sync pulse

0.7

DC(HSYNC)

input current

HSYNC

= 0.8 V

200

HSYNC

= 5.5 V

NPUT CHARACTERISTICS FOR

AC-

COUPLED VIDEO SIGNALS

(

SYNC

VIDEO

NEGATIVE SYNC POLARITY

)

AC(HSYNC)

sync amplitude of video input
signal voltage

300

slicing voltage level
(measured from top sync)

source resistance
R

= 50

120

150

clamp(HSYNC)

top sync clamping voltage level

1.1

1.28

1.5

C(HSYNC)

charge current for coupling
capacitor

HSYNC

clamp(HSYNC)

1.7

2.4

3.4

HSYNC(min)

minimum width of sync pulse

0.7

S(max)

maximum source resistance

duty factor = 7%

1500

diff(HSYNC)

differential input resistance

during sync

Automatic polarity correction for horizontal sync

horizontal sync pulse width
related to t

45 kHz

P(H)

delay time for changing polarity

0.3

1.8

Vertical sync integrator

int(V)

integration time for generation
of a vertical trigger pulse

= 31.45 kHz;

HREF

= 1.052 mA

= 64 kHz;

HREF

= 2.141 mA

3.9

5.7

6.5

= 100 kHz;

HREF

= 3.345 mA

2.5

3.8

4.5

Vertical sync slicer (DC-coupled, TTL compatible) [VSYNC (pin 14)]

VSYNC

sync input signal voltage

1.7

slicing voltage level

1.2

1.4

1.6

VSYNC

input current

0 V

SYNC

5.5 V

P H

( )

-------------

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

ERTICAL SYNC OUTPUT AT

VSYNC (

14)

DURING COMPOSITE SYNC AT

HSYNC (

15)

VSYNC

output current

during internal vertical
sync

0.7

1.0

1.35

VSYNC

internal clamping voltage level

during internal vertical
sync

4.4

4.8

5.2

steepness of slopes

300

ns/mA

Automatic polarity correction for vertical sync

VSYNC(max)

maximum width of vertical sync
pulse

300

d(VPOL)

delay for changing polarity

0.3

1.8

Video clamping/vertical blanking output [CLBL (pin 16)]

clamp(CLBL)

width of video clamping pulse

measured at V

CLBL

= 3 V

0.6

0.7

0.8

clamp(CLBL)

top voltage level of video
clamping pulse

4.32

4.75

5.23

d(clamp)

delay between trailing edge of
horizontal sync and start of
video clamping pulse

clamping pulse triggered
on trailing edge of
horizontal sync

130

clamp(max)

maximum duration of video
clamping pulse referenced to
end of horizontal sync

measured at V

CLBL

= 3 V

1.0

clamp

temperature coefficient of
V

clamp(CLBL)

mV/K

steepness of slopes for
clamping pulse

= 1 M

; C

= 20 pF

ns/V

blank(CLBL)

top voltage level of vertical
blanking pulse

notes 1 and 2

1.7

1.9

2.1

blank(CLBL)

width of vertical blanking pulse

VGA presets active

500

575

650

VGA presets disabled

240

300

360

blank

temperature coefficient of
V

blank(CLBL)

mV/K

scan(CLBL)

output voltage during vertical
scan

CLBL

= 0

0.59

0.63

0.67

scan

temperature coefficient of
V

scan(CLBL)

mV/K

sink(CLBL)

internal sink current

2.4

load(CLBL)

external load current

3.0

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

PLL1 phase comparator and frequency-locked loop [HPLL1 (pin 26) and HBUF (pin 27)]

HSYNC(max)

maximum width of horizontal
sync pulse (referenced to line
period)

45 kHz; note 3

lock(HPLL1)

total lock-in time of PLL1

HPLL1

control voltage

notes 4 and 5

HBUF

buffered f/v voltage at HBUF
(pin 27)

H(min)

; note 6

5.6

H(max)

; note 6

2.5

load(HBUF)

maximum load current

4.0

DJUSTMENT OF HORIZONTAL PICTURE POSITION

HPOS

horizontal shift adjustment
range (referenced to horizontal
period)

HSHIFT

= 0

10.5

HSHIFT

135

+10.5

HPOS

input current

HPOS = +10.5%

110

120

135

HPOS =

10.5%

ref(HPOS)

reference voltage at input

note 7

5.1

off(HPOS)

picture shift is centred if HPOS
(pin 30) is forced to ground

0.1

Horizontal oscillator [HCAP (pin 29) and HREF (pin 28)]

H(0)

free-running frequency without
PLL1 action (for testing only)

HBUF

;

HREF

= 2.4 k

;

HCAP

= 10 nF; note 5

30.53

31.45

32.39

kHz

H(0)

spread of free-running
frequency (excluding spread of
external components)

3.0

temperature coefficient of
free-running frequency

100

+100

H(max)

maximum oscillator frequency

130

kHz

HREF

voltage at input for reference
current

2.43

2.55

2.68

PLL2 phase detector [HFLB (pin 1) and HPLL2 (pin 31)]

PLL2

PLL2 control (advance of
horizontal drive with respect to
middle of horizontal flyback)

maximum advance

minimum advance

d(HFLB)

delay between middle of
horizontal sync and middle of
horizontal flyback

HPOS (pin 30) grounded

200

PROT(HPLL2)

maximum voltage for PLL2
protection mode/soft start

4.4

charge(HPLL2)

charge current for external
capacitor during soft start

HPLL2

3.7 V

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

ORIZONTAL FLYBACK INPUT

[HFLB (

1)]

HFLB

positive clamping level

HFLB

= 5 mA

5.5

negative clamping level

HFLB

1 mA

0.75

HFLB

positive clamping current

negative clamping current

HFLB

slicing level

2.8

Output stage for line driver pulses [HDRV (pin 7)]

PEN COLLECTOR OUTPUT STAGE

HDRV

saturation voltage

HDRV

= 20 mA

0.3

HDRV

= 60 mA

0.8

leakage(HDRV)

output leakage current

HDRV

= 16 V

UTOMATIC VARIATION OF DUTY FACTOR

HDRV(OFF)

relative t

OFF

time of HDRV

output; measured at
V

HDRV

= 3 V; HDRV duty factor

is determined by the relation
I

HREF

VREF

HDRV

= 20 mA;

= 31.45 kHz; see Fig.9

HDRV

= 20 mA;

= 57 kHz; see Fig.9

46.3

47.7

HDRV

= 20 mA;

= 90 kHz; see Fig.9

46.6

49.4

X-ray protection [XRAY (pin 2)]

XRAY

slicing voltage level

6.14

6.38

6.64

W(XRAY)

minimum width of trigger pulse

I(XRAY)

input resistance at XRAY
(pin 2)

XRAY

6.38 V + V

500

XRAY

6.38 V + V

RESET(VCC)

supply voltage for reset of
X-ray latch

5.6

Vertical oscillator (oscillator frequency in application without adjustment of free-running frequency f

v(o)

)

free-running frequency

VREF

= 22 k

;

VCAP

= 100 nF

43.3

v(o)

vertical frequency catching
range

constant amplitude;
notes 8, 9 and 10

110

VREF

voltage at reference input for
vertical oscillator

3.0

d(scan)

delay between trigger pulse
and start of ramp at VCAP
(pin 24) (width of vertical
blanking pulse)

VGA presets active

500

575

650

VGA presets disabled

240

300

360

VAGC

control currents of amplitude
control

120

200

300

VAGC

external capacitor at VAGC
(pin 22)

150

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

Differential vertical current outputs

DJUSTMENT OF VERTICAL SIZE

(see Figs 3 to 8) [VAMP (

18)]

VAMP

vertical size adjustment range
(referenced to nominal vertical
size)

VAMP

= 0; note 11

VAMP

135

A; note 11

100

VAMP

input current for maximum
amplitude (100%)

110

120

135

input current for minimum
amplitude (60%)

ref(VAMP)

reference voltage at input

5.0

RESETS FOR

VGA

MODE DEPENDENT VERTICAL SIZE

HBUF

HREF

minimum current ratio
I

HBUF

HREF

for enable of VGA

presets

note 12

2.25

2.5

2.75

VAMP

variation of vertical size for
detected VGA modes
(reference for all amplitude
settings is VGA480 mode)

VGA350

116.8

VGA400

102.2

VGA480

100.0

DJUSTMENT OF VERTICAL SHIFT

(see Figs 3 to 8) [VPOS (

17)]

VPOS

vertical shift adjustment range
(referenced to 100% vertical
size)

VPOS

135

A; note 11

11.5

VPOS

= 0; note 11

+11.5

VPOS

input current for maximum
shift-up

110

120

135

input current for maximum
shift-down

ref(VPOS)

reference voltage at input

5.0

off(VPOS)

vertical shift is centred if VPOS
(pin 17) is forced to ground

0.1

DJUSTMENT OF VERTICAL S

CORRECTION

(see Figs 3 to 8) [VSCOR (

19)]

VSCOR

vertical S-correction
adjustment range

VSCOR

= 0; note 11

VSCOR

135

note 11

VSCOR

input current for maximum
S-correction

110

120

135

input current for minimum
S-correction

VSCOR

symmetry error of S-correction

maximum

VSCOR

0.7

ref(VSCOR)

reference voltage at input

5.0

SAWM(p-p)

voltage amplitude of
superimposed logarithmic
sawtooth (peak-to-peak value)

note 13

145

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

Vertical output stage [VOUT1 (pin 13) and VOUT2 (pin 12)]

VOUT(nom)

nominal differential output
current (peak-to-peak value)
(

VOUT

= I

VOUT1

VOUT2

)

nominal settings; note 11

0.76

0.85

0.94

VOUT(max)

maximum differential output
current (peak value)
(

VOUT

= I

VOUT1

VOUT2

)

0.54

0.6

0.66

VOUT1

, V

VOUT2

allowed voltage at outputs

4.2

V(offset)

maximum offset error of vertical
output currents

nominal settings; note 11

2.5

V(lin)

maximum linearity error of
vertical output currents

nominal settings; note 11

1.5

EW drive output

DRIVE OUTPUT STAGE

[EWDRV (

11)]

EWDRV

bottom output voltage
(internally stabilized)

PAR(EWDRV)

= 0;

DC(EWDRV)

= 0;

EWTRP centred

1.05

1.2

1.35

maximum output voltage

note 14

7.0

EWDRV

output load current

2.0

EWDRV

temperature coefficient of
output signal

600

DJUSTMENT OF

PARABOLA AMPLITUDE

(see Figs 3 to 8) [EWPAR (

21)]

PAR(EWDRV)

parabola amplitude

EWPAR

= 0; note 11

0.05

EWPAR

135

note 11

EWPAR

input current for maximum
amplitude

110

120

135

input current for minimum
amplitude

ref(EWPAR)

reference voltage at input

5.0

DJUSTMENT OF HORIZONTAL SIZE

(see Figs 3 to 8) [EWWID (

32)]

DC(EWDRV)

EW parabola DC voltage shift

EWWID

135

note 11

0.1

EWWID

= 0; note 11

4.2

EWWID

input current for maximum DC
shift

input current for minimum DC
shift

110

120

135

ref(EWWID)

reference voltage at input

5.0

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

DJUSTMENT OF TRAPEZIUM CORRECTION

(see Figs 3 to 8) [EWTRP (

20)]

TRP(EWDRV)

trapezium correction voltage

EWTRP

= 0; note 11

0.5

EWTRP

135

note 11

+0.5

EWTRP

input current for maximum
positive trapezium correction

110

120

135

input current for maximum
negative trapezium correction

ref(EWTRP)

reference voltage at input

5.0

off(EWTRP)

trapezium correction is centred
if EWTRP (pin 20) is forced to
ground

0.1

PARM(p-p)

amplitude of superimposed
logarithmic parabola
(peak-to-peak value)

note 15

145

RACKING OF

EWDRV

OUTPUT SIGNAL WITH

PROPORTIONAL VOLTAGE

H(MULTI)

range for tracking

kHz

PAR(EWDRV)

parabola amplitude at EWDRV
(pin 11)

HREF

= 1.052 mA;

= 31.45 kHz; note 16

1.3

1.45

1.6

HREF

= 2.341 mA;

= 70 kHz; note 16

2.7

3.0

3.3

function disabled; note 16

2.7

3.0

3.3

EWDRV

linearity error of f

tracking

EWWID

voltage range to inhibit tracking

0.1

Focus section [FOCUS (pin 10)]

FOCUS(p-p)

amplitude of horizontal
parabola (peak-to-peak value)

FOCUS

= 1 V

0.03

FOCUS

= 4 V

FOCUS(min)

input voltage for minimum
horizontal parabola amplitude

0.9

1.0

1.1

FOCUS(max)

input voltage for maximum
horizontal parabola amplitude

3.65

4.0

4.4

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

B+ control section (see Figs 12 and 13)

RANSCONDUCTANCE AMPLIFIER

[BIN (

AND

BOP (

3)]

BIN

input voltage

5.25

BIN(max)

maximum input current

ref(int)

reference voltage at internal
non-inverting input of OTA

2.37

2.5

2.58

BOP(min)

minimum output voltage

0.4

BOP(max)

maximum output voltage

BOP

1 mA

5.3

5.6

BOP(max)

maximum output current

500

transconductance of OTA

note 17

open

open-loop gain

note 18

BOP

minimum value of capacitor at
BOP (pin 3)

4.7

OLTAGE COMPARATOR

[BSENS (

4)]

BSENS

voltage range of positive
comparator input

BOP

voltage range of negative
comparator input

BSENS

maximum leakage current

discharge disabled

PEN COLLECTOR OUTPUT STAGE

[BDRV (

6)]

BDRV(max)

maximum output current

leakage(BDRV)

output leakage current

BDRV

= 16 V

sat(BDRV)

saturation voltage

BDRV

20 mA

300

off(min)

minimum off-time

250

d(BDRV)

delay between BDRV pulse
and HDRV pulse

measured at
V

HDRV

, V

BDRV

= 3 V

500

BSENS

DISCHARGE CIRCUIT

STOP(BSENS)

discharge stop level

capacitive load;
I

BSENS

= 0.5 mA

0.85

1.0

1.15

DISC(BSENS)

discharge current

BSENS

2.5 V

4.5

7.5

RESTART(BSENS)

threshold voltage for restart

fault condition

1.2

1.3

1.4

BSENS

minimum value of capacitor at
BSENS (pin 4)

Internal reference, supply voltage and protection

STAB(VCC)

external supply voltage for
complete stabilization of all
internal references

9.2

VCC

supply current

PSRR

power supply rejection ratio of
internal supply voltage

f = 1 kHz

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

Notes to the characteristics

1. For duration of vertical blanking pulse see characteristics of "Vertical oscillator (oscillator frequency in application

without adjustment of free-running frequency fv(o))".

2. Continuous blanking at CLBL (pin 16) will be activated, if one of the following conditions is true:

a) No horizontal flyback pulses at HFLB (pin 1) within a line

b) X-ray protection is triggered

c) Voltage at HPLL2 (pin 31) is low (for soft start of horizontal drive)

d) Supply voltage at V

(pin 9) is low

e) PLL1 unlocked while frequency-locked loop is in search mode.

3. To ensure safe locking of the horizontal oscillator, one of the following procedures is required:

a) Search mode starts always from f

min

. Then the PLL1 filter components are a 3.3 nF capacitor from pin 26 to

ground in parallel with an 8.2 k

resistor in series with a 47 nF capacitor.

b) Search mode starts either from f

min

or f

max

with HPOS in middle position (I

HPOS

= 60

A). Then the PLL1 filter

components are a 1.5 nF capacitor from pin 26 to ground in parallel with a 27 k

resistor in series with a 47 nF

capacitor.

c) After locking is achieved, HPOS can be operated in the normal way.

4. Loading of HPLL1 (pin 26) is not allowed.

5. Oscillator frequency is f

min

when no sync input signal is present (no continuous blanking at pin 16).

6. Voltage at HPLL1 (pin 26) is fed to HBUF (pin 27) via a buffer. Disturbances caused by horizontal sync are removed

by an internal sample-and-hold circuit.

7. Input resistance at HPOS (pin 30):

8. Full vertical sync range with constant amplitude (f

V(min)

: f

V(max)

= 1 : 2.5) can be made usable by choosing an

application with adjustment of free-running frequency.

9. If higher vertical frequencies are required, sync range can be shifted by using a smaller capacitor at VCAP (pin 24).

10. Value of resistor at VREF (pin 23) may not be changed.

11. All vertical and EW adjustments are specified at nominal vertical settings, which means:

VAMP = 100% (I

VAMP

= 135

VSCOR = 0 (pin 19 open-circuit)

VPOS centred (pin 17 forced to ground)

d) VGA presets disabled (current ratio I

HBUF

: I

HREF

2.25)

e) f

= 70 kHz.

12. VGA presets are enabled below the horizontal frequency at which the current ratio I

HBUF

: I

HREF

exceeds the

specified value.

13. The superimposed logarithmic sawtooth at VSCOR (pin 19) tracks with internal VGA settings and with VPOS, but

not with VAMP settings. The superimposed waveform is described by

with `d' being the modulation

depth of a sawtooth from

to +

. A linear sawtooth with the same modulation depth can be recovered in an

external long-tailed pair (see Fig.17).

14. The output signal at EWDRV (pin 11) may consist of parabola + DC shift + trapezium correction. These adjustments

have to be carried out in a correct relationship to each other in order to avoid clipping due to the limited output voltage
range at EWDRV.

HPOS

------

HPOS

---------------

-------

-------------

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

15. The superimposed logarithmic parabola at EWTRP (pin 20) tracks with internal VGA settings and with VPOS, but

not with VAMP settings (see Fig.17).

16. If f

tracking is enabled, the amplitude of the complete EWDRV output signal (parabola + DC shift + trapezium) will

be changed proportional to I

HREF

. The EWDRV low level of 1.2 V remains fixed.

17. First pole of transconductance amplifier is 5 MHz without external capacitor (will become the second pole, if the OTA

operates as an integrator).

18. Open-loop gain is

at f = 0 with no resistive load and C

BOP

= 4.7 nF (from BOP (pin 3) to GND).

BOP

BIN

--------------

Vertical and EW adjustments

Fig.3 I

VOUT1

and I

VOUT2

as functions of time.

(1)

is the maximum amplitude setting at VAMP (pin 18);

VGA presets disabled, VPOS centred and VSCOR = 0%.

VAMP

--------

100%

handbook, halfpage

IVOUT1

IVOUT2

(1)

MBG590

Fig.4 V

EWDRV

as a function of time.

EWPAR = 0 to V

PAR(EWDRV)

handbook, halfpage

VEWDRV

VPAR(EWDRV)

MBG591

1996 Jul 18

Philips Semiconductors

Preliminary specification

Autosync Deflection Controller (ASDC)

TDA4855

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

Soldering by dipping or by wave

The maximum permissible temperature of the solder is
260

C; solder at this temperature must not be in contact

with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg max

). If the

printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

Repairing soldered joints

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300

C it may remain in

contact for up to 10 seconds. If the bit temperature is
between 300 and 400

C, contact may be up to 5 seconds.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Internet: http://www.semiconductors.philips.com/ps/

(1)

TDA4855_1 June 26, 1996 11:51 am

Philips Semiconductors a worldwide company

SCA50

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Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 83749, Fax. +31 40 27 88399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811

Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341

Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327

Portugal: see Spain

Romania: see Italy

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 926 5361, Fax. +7 095 564 8323

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494

South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 829 1849

Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 632 2000, Fax. +46 8 632 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 481 7730

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,
Chung Hsiao West Road, Sec. 1, P.O. Box 22978,
TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707

Ukraine: PHILIPS UKRAINE, 2A Akademika Koroleva str., Office 165,
252148 KIEV, Tel. +380 44 476 0297/1642, Fax. +380 44 476 6991

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 708 296 8556

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 825 344, Fax.+381 11 635 777

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101, Fax. +43 1 60 101 1210

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773

Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 708 296 8556

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700

Colombia: see South America

Czech Republic: see Austria

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 1949

Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 615 800, Fax. +358 615 80920

France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 52 60, Fax. +49 40 23 536 300

Greece: No. 15, 25th March Street, GR 17778 TAVROS,
Tel. +30 1 4894 339/911, Fax. +30 1 4814 240

Hungary: see Austria

India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722

Indonesia: see Singapore

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,
Tel. +972 3 645 0444, Fax. +972 3 648 1007

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +1 800 234 7381, Fax. +1 708 296 8556

Middle East: see Italy

Printed in The Netherlands

537021/51/01/pp44

Date of release: 1996 Jul 18

Document order number:

9397 750 00973

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