2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

FEATURES

Concept features

Full horizontal plus vertical autosync capability

Extended horizontal frequency range from
15 to 130 kHz

Comprehensive set of I

C-bus driven geometry

adjustments and functions, including standby mode

Very good vertical linearity

Moire cancellation

Start-up and switch-off sequence for safe operation of
all power components

X-ray protection

Flexible switched mode B+ supply function block for
feedback and feed forward converter

Internally stabilized voltage reference

Drive signal for focus amplifier with vertical parabola
waveforms

DC controllable inputs for Extremely High Tension
(EHT) compensation

SDIP32 package.

Synchronization

Can handle all sync signals (horizontal, vertical,
composite and sync-on-video)

Output for video clamping (leading/trailing edge
selectable by I

C-bus), vertical blanking and protection

blanking

Output for fast unlock status of horizontal
synchronization and blanking on grid 1 of picture tube.

Horizontal section

C-bus controllable wide range linear picture position,

pin unbalance and parallelogram correction via
horizontal phase

Frequency-locked loop for smooth catching of horizontal
frequency

Simple frequency preset of f

min

and f

max

by external

resistors

Low jitter

Soft start for horizontal and B+ control drive signals.

Vertical section

C-bus controllable vertical picture size, picture

position, linearity (S-correction) and linearity balance

Output for I

C-bus controllable vertical sawtooth and

parabola (for pin unbalance and parallelogram)

Vertical picture size independent of frequency

Differential current outputs for DC coupling to vertical
booster

50 to 160 Hz vertical autosync range.

East-West (EW) section

C-bus controllable output for horizontal pincushion,

horizontal size, corner and trapezium correction

Optional tracking of EW drive waveform with line
frequency selectable by I

C-bus.

Focus section

C-bus controllable output for vertical parabola

Vertical parabola is independent of frequency and tracks
with vertical adjustments.

GENERAL DESCRIPTION

The TDA4857PS is a high performance and efficient
solution for autosync monitors. All functions are
controllable by the I

C-bus.

The TDA4857PS provides synchronization processing,
horizontal and vertical synchronization with full autosync
capability and very short settling times after mode
changes. External power components are given a great
deal of protection. The IC generates the drive waveforms
for DC-coupled vertical boosters such as the TDA486x
and TDA835x.

The TDA4857PS provides extended functions e.g. as a
flexible B+ control, an extensive set of geometry control
facilities and an output for vertical focus signals.

Together with the I

C-bus driven Philips TDA488x video

processor family, a very advanced system solution is
offered.

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

supply voltage

9.2

supply current

CC(stb)

supply current during standby mode

VSIZE

vertical size

100

VGA

VGA overscan for vertical size

16.8

VPOS

vertical position

11.5

VLIN

vertical linearity (S-correction)

VLINBAL

vertical linearity balance

2.5

HSIZE

horizontal size voltage

0.13

3.6

HPIN

horizontal pincushion voltage (EW parabola)

0.04

1.42

HEHT

horizontal size modulation voltage

0.02

0.69

HTRAP

horizontal trapezium correction voltage

0.33

HCOR

horizontal corner correction voltage

0.64

+0.08

HPOS

horizontal position

HPARAL

horizontal parallelogram

HPINBAL

EW pin unbalance

amb

ambient temperature

+70

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA4857PS

SDIP32

plastic shrink dual in-line package; 32 leads (400 mil)

SOT232-1

2000

Jan

Philips Semiconductors

Product specification

C-b

us autosync deflection controller f

PC monitors

TD
A4857PS

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VERTICAL

SYNC INPUT

AND POLARITY

CORRECTION

VERTICAL

SYNC

INTEGRATOR

VERTICAL

OSCILLATOR

AND AGC

EW-OUTPUT

HORIZONTAL PINCUSHION

HORIZONTAL CORNER

HORIZONTAL TRAPEZIUM

HORIZONTAL SIZE

VERTICAL LINEARITY

BALANCE

HORIZONTAL SIZE

AND

VERTICAL SIZE

EHT COMPENSATION

OUTPUT

ASYMMETRIC

EW-CORRECTION

C-BUS

RECEIVER

HUNLOCK

OUTPUT

VERTICAL POSITION

VERTICAL SIZE, VOVSCN

VIDEO CLAMPING

AND

VERTICAL BLANK

SUPPLY

AND

REFERENCE

HORIZONTAL

OSCILLATOR

PLL1 AND

HORIZONTAL

POSITION

PLL2, PARALLELOGRAM,

PIN UNBALANCE AND

SOFT START

COINCIDENCE DETECTOR

FREQUENCY DETECTOR

C-BUS REGISTERS

PROTECTION

AND SOFT START

X-RAY

PROTECTION

HORIZONTAL

OUTPUT

STAGE

CONTROL

3.3 k

100 nF

8.2

150

(1%)

X-RAY

10 nF

RHBUF

(2%)

RHREF

(1%)

(1)

CONTROL

APPLICATION

(2)

(TTL level)

MHB658

9.2 to 16 V

(video)

clamping

blanking

100

(5%)

VOUT2

VOUT1

ASCOR

FOCUS

BDRV

BSENS

BOP

BIN

8 HDRV

8.2 nF

TDA4857PS

H/C SYNC INPUT

AND POLARITY

CORRECTION

VERTICAL OUTPUT

FOCUS

VERTICAL

SDA

SCL

HSYNC

SGND

PGND

CLBL

VSYNC

VCC

EWDRV

VSMOD

VAGC

VCAP

VREF

HSMOD

7 V

1.2 V

EHT compensation

via horizontal size

EHT compensation

via vertical size

HFLB

HPLL2

HCAP

HREF

HBUF

HPLL1

XSEL

XRAY

HUNLOCK

Fig.1 Block diagram and application circuit.

(1) For the calculation of f

range see Section "Calculation of line frequency range".

(2) See Figs 21 and 22.

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

PINNING

SYMBOL

PIN

DESCRIPTION

HFLB

horizontal flyback input

XRAY

X-ray protection input

BOP

B+ control OTA output

BSENS

B+ control comparator input

BIN

B+ control OTA input

BDRV

B+ control driver output

PGND

power ground

HDRV

horizontal driver output

XSEL

select input for X-ray reset

supply voltage

EWDRV

EW waveform output

VOUT2

vertical output 2 (ascending sawtooth)

VOUT1

vertical output 1 (descending sawtooth)

VSYNC

vertical synchronization input

HSYNC

horizontal/composite synchronization input

CLBL

video clamping pulse/vertical blanking output

HUNLOCK

horizontal synchronization unlock/protection/vertical blanking output

SCL

C-bus clock input

SDA

C-bus data input/output

ASCOR

output for asymmetric EW corrections

VSMOD

input for EHT compensation (via vertical size)

VAGC

external capacitor for vertical amplitude control

VREF

external resistor for vertical oscillator

VCAP

external capacitor for vertical oscillator

SGND

signal ground

HPLL1

external filter for PLL1

HBUF

buffered f/v voltage output

HREF

reference current for horizontal oscillator

HCAP

external capacitor for horizontal oscillator

HPLL2

external filter for PLL2/soft start

HSMOD

input for EHT compensation (via horizontal size)

FOCUS

output for vertical focus

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

FUNCTIONAL DESCRIPTION

Horizontal sync separator and polarity correction

HSYNC (pin 15) is the input for horizontal synchronization
signals, which can be DC-coupled TTL signals (horizontal
or composite sync) and AC-coupled negative-going video
sync signals. Video syncs are clamped to 1.28 V and
sliced at 1.4 V. This results in a fixed absolute slicing level
of 120 mV related to top sync.

For DC-coupled TTL signals the input clamping current is
limited. The slicing level for TTL signals is 1.4 V.

The separated sync signal (either video or TTL) is
integrated on an internal capacitor to detect and normalize
the sync polarity.

Normalized horizontal sync pulses are used as input
signals for the vertical sync integrator, the PLL1 phase
detector and the frequency-locked loop.

Vertical sync integrator

Normalized composite sync signals from HSYNC are
integrated on an internal capacitor in order to extract
vertical sync pulses. The integration time is dependent on
the horizontal oscillator reference current at HREF
(pin 28). The integrator output directly triggers the vertical
oscillator.

Vertical sync slicer and polarity correction

Vertical sync signals (TTL) applied to VSYNC (pin 14) are
sliced at 1.4 V. The output signal of the sync slicer is
integrated on an internal capacitor to detect and normalize
the sync polarity. The output signals of vertical sync
integrator and sync normalizer are disjuncted before they
are fed to the vertical oscillator.

Video clamping/vertical blanking generator

The video clamping/vertical blanking signal at CLBL
(pin 16) is a two-level sandcastle pulse which is especially
suitable for video ICs such as the TDA488x family, but also
for direct applications in video output stages.

The upper level is the video clamping pulse, which is
triggered by the horizontal sync pulse. Either the leading or
trailing edge can be selected by setting control bit CLAMP
via the I

C-bus. The width of the video clamping pulse is

determined by an internal single-shot multivibrator.

The lower level of the sandcastle pulse is the vertical
blanking pulse, which is derived directly from the internal
oscillator waveform. It is started by the vertical sync and
stopped with the start of the vertical scan. This results in
optimum vertical blanking. Two different vertical blanking
times are accessible, by control bit VBLK, via the I

C-bus.

Blanking will be activated continuously if one of the
following conditions is true:

Soft start of horizontal and B+ drive [voltage at HPLL2
(pin 30) pulled down externally or by the I

C-bus]

PLL1 is unlocked while frequency-locked loop is in
search mode or if horizontal sync pulses are absent

No horizontal flyback pulses at HFLB (pin 1)

X-ray protection is activated

Supply voltage at V

(pin 10) is low (see Fig.23).

Horizontal unlock blanking can be switched off, by control
bit BLKDIS, via the I

C-bus while vertical blanking and

protection blanking is maintained.

handbook, halfpage

TDA4857PS

HFLB

XRAY

BOP

BSENS

BIN

BDRV

PGND

HDRV

XSEL

VCC

EWDRV

VOUT2

VOUT1

VSYNC

FOCUS

HSMOD

HPLL2

HCAP

HBUF

HPLL1

HREF

SGND

VCAP

VREF

VAGC

VSMOD

ASCOR

SDA

HSYNC

CLBL

MHB656

SCL

HUNLOCK

Fig.2 Pin configuration.

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

Frequency-locked loop

The frequency-locked loop can lock the horizontal
oscillator over a wide frequency range. This is achieved by
a combined search and PLL operation. The frequency
range is preset by two external resistors and the

recommended maximum ratio is

This can, for instance, be a range from 15.625 to 90 kHz
with all tolerances included.

Without a horizontal sync signal the oscillator will be
free-running at f

min

. Any change of sync conditions is

detected by the internal coincidence detector. A deviation
of more than 4% between horizontal sync and oscillator
frequency will switch the horizontal section into search
mode. This means that PLL1 control currents are switched
off immediately.

The internal frequency detector then starts tuning the
oscillator. Very small DC currents at HPLL1 (pin 26) are
used to perform this tuning with a well defined change rate.
When coincidence between horizontal sync and oscillator
frequency is detected, the search mode is first replaced by
a soft-lock mode which lasts for the first part of the next
vertical period. The soft-lock mode is then replaced by a
normal PLL operation. This operation ensures smooth
tuning and avoids fast changes of horizontal frequency
during catching.

In this concept it is not allowed to load HPLL1.
The frequency dependent voltage at this pin is fed
internally to HBUF (pin 27) via a sample-and-hold and
buffer stage. The sample-and-hold stage removes all
disturbances caused by horizontal sync or composite
vertical sync from the buffered voltage. An external
resistor connected between pins HBUF and HREF defines
the frequency range.

Out-of-lock indication (pin HUNLOCK)

Pin HUNLOCK is floating during search mode if no sync
pulses are applied, or if a protection condition is true.
All this can be detected by the microcontroller if a pull-up
resistor is connected to its own supply voltage.

For an additional fast vertical blanking at grid 1 of the
picture tube a 1 V signal referenced to ground is available
at this output. The continuous protection blanking
(see Section "Video clamping/vertical blanking generator")
is also available at this pin. Horizontal unlock blanking can
be switched off, by control bit BLKDIS via the I

C-bus,

while vertical blanking is maintained.

Horizontal oscillator

The horizontal oscillator is of the relaxation type and
requires a capacitor of 10 nF to be connected at HCAP
(pin 29). For optimum jitter performance the value of 10 nF
must not be changed.

The minimum oscillator frequency is determined by a
resistor connected between pin HREF and ground.
A resistor connected between pins HREF and HBUF
defines the frequency range.

The reference current at pin HREF also defines the
integration time constant of the vertical sync integration.

Calculation of line frequency range

The oscillator frequencies f

min

and f

max

must first be

calculated. This is achieved by adding the spread of the
relevant components to the highest and lowest sync
frequencies f

sync(min)

and f

sync(max)

. The oscillator is driven

by the currents in R

HREF

and R

HBUF

The following example is a 31.45 to 90 kHz application:

Table 1

Calculation of total spread

Thus the typical frequency range of the oscillator in this
example is:

The TV mode is centred around f

min

with a control range of

10%. Activation of the TV mode is only allowed between

15.625 and 35 kHz.

The resistors R

HREF

and R

HBUFpar

can be calculated using

the following formulae:

max

min

----------

6.5

--------

spread of

for f

max

for f

min

HCAP

HREF

, R

HBUF

Total

max

sync max

(

)

1.07

96.3 kHz

min

sync min

(

)

1.09

-----------------------

28.9 kHz

HREF

kHz

min

0.0012

min

kHz

[

]

-----------------------------------------------------------------

2.61 k

HBUFpar

kHz

max

0.0012

max

kHz

[

]

--------------------------------------------------------------------

726

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

The resistor R

HBUFpar

is calculated as the value of R

HREF

and R

HBUF

in parallel. The formulae for R

HBUF

also takes

into account the voltage swing across this resistor

PLL1 phase detector

The phase detector is a standard type using switched
current sources, which are independent of the horizontal
frequency. It compares the middle of the horizontal sync
with a fixed point on the oscillator sawtooth voltage.
The PLL1 loop filter is connected to HPLL1 (pin 26).

See also Section "Horizontal position adjustment and
corrections".

Horizontal position adjustment and corrections

A linear adjustment of the relative phase between the
horizontal sync and the oscillator sawtooth (in PLL1 loop)
is achieved via register HPOS. Once adjusted, the relative
phase remains constant over the whole frequency range.

Correction of pin unbalance and parallelogram is achieved
by modulating the phase between the oscillator sawtooth
and horizontal flyback (in loop PLL2) via registers
HPARAL and HPINBAL. If those asymmetric EW
corrections are performed in the deflection stage, both
registers can be disconnected from the horizontal phase
via control bit ACD. This does not change the output at
pin ASCOR.

Horizontal moire cancellation

To achieve a cancellation of horizontal moire (also known
as `video moire'), the horizontal frequency is
divided-by-two to achieve a modulation of the horizontal
phase via PLL2. The amplitude is controlled by register
HMOIRE. To avoid a visible structure on screen the
polarity changes with half of the vertical frequency. Control
bit MOD disables the moire cancellation function.

PLL2 phase detector

The PLL2 phase detector is similar to the PLL1 detector
and compares the line flyback pulse at HFLB (pin 1) with
the oscillator sawtooth voltage. The control currents are
independent of the horizontal frequency. The PLL2
detector thus compensates for the delay in the external
horizontal deflection circuit by adjusting the phase of the
HDRV (pin 8) output pulse.

For the TDA4857PS external modulation of the PLL2
phase is not allowed, because this would disturb the start
advance of the horizontal focus parabola.

Soft start and standby

If HPLL2 is pulled to ground by resetting the register
SOFTST, the horizontal output pulses, vertical output
currents and B+ control driver pulses will be inhibited. This
means that HDRV (pin 8), BDRV (pin 6), VOUT1 (pin 13)
and VOUT2 (pin 12) are floating in this state. If HPLL2 is
pulled to ground by an external DC current, vertical output
currents stay active while HDRV (pin 8) and BDRV (pin 6)
are in floating state. In both cases the PLL2 and the
frequency-locked loop are disabled, CLBL (pin 16)
provides a continuous blanking signal and HUNLOCK
(pin 17) is floating.

This option can be used for soft start, protection and
power-down modes. When the HPLL2 pin is released
again, an automatic soft start sequence on the horizontal
drive as well as on the B+ drive output will be performed
(see Figs 24 and 25).

A soft start can only be performed if the supply voltage for
the IC is a minimum of 8.6 V.

The soft start timing is determined by the filter capacitor at
HPLL2 (pin 30), which is charged with a constant current
during soft start. If the voltage at pin 30 (HPLL2) reaches
1.1 V, the vertical output currents are enabled. At 1.7 V the
horizontal driver stage generates very small output pulses.
The width of these pulses increases with the voltage at
HPLL2 until the final duty cycle is reached. The voltage at
HPLL2 increases further and performs a soft start at BDRV
(pin 6) as well. The voltage at HPLL2 continues to rise until
HPLL2 enters its normal operating range. The internal
charge current is now disabled. Finally PLL2 and the
frequency-locked loop are activated. If both functions
reach normal operation, HUNLOCK (pin 17) switches from
the floating status to normal vertical blanking, and
continuous blanking at CLBL (pin 16) is removed.

Output stage for line drive pulses [HDRV (pin 8)]

An open-collector output stage allows direct drive of an
inverting driver transistor because of a low saturation
voltage of 0.3 V at 20 mA. To protect the line deflection
transistor, the output stage is disabled (floating) for a low
supply voltage at V

(see Fig.23).

The duty cycle of line drive pulses is slightly dependent on
the actual horizontal frequency. This ensures optimum
drive conditions over the whole frequency range.

HBUF

HREF

HBUFpar

HREF

HBUFpar

----------------------------------------------

0.8

805

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

X-ray protection

The X-ray protection input XRAY (pin 2) provides a voltage
detector with a precise threshold. If the input voltage at
XRAY exceeds this threshold level for a certain time then
control bit SOFTST is reset, which switches the IC into
protection mode. In this mode several pins are forced into
defined states:

HUNLOCK (pin 17) is floating

The capacitor connected to HPLL2 (pin 30) is
discharged

Horizontal output stage (HDRV) is floating

B+ control driver stage (BDRV) is floating

Vertical output stages (VOUT1 and VOUT2) are floating

CLBL provides a continuous blanking signal.

There are two different methods of restarting the IC:

1. XSEL (pin 9) is open-circuit or connected to ground.

The control bit SOFTST must be set to logic 1 via the
I

C-bus. The IC then returns to normal operation via

soft start.

2. XSEL (pin 9) is connected to V

via an external

resistor. The supply voltage of the IC must be switched
off for a certain period of time before the IC can be
restarted again using the standard power-on
procedure.

Vertical oscillator and amplitude control

This stage is designed for fast stabilization of vertical size
after changes in sync frequency conditions.

The free-running frequency f

fr(V)

is determined by the

resistor R

VREF

connected to pin 23 and the capacitor

VCAP

connected to pin 24. The value of R

VREF

is not only

optimized for noise and linearity performance in the whole
vertical and EW section, but also influences several
internal references. Therefore the value of R

VREF

must not

be changed.

Capacitor C

VCAP

should be used to select the free-running

frequency of the vertical oscillator in accordance with the

following formula:

To achieve a stabilized amplitude the free-running
frequency f

fr(V)

, without adjustment, should be at least 10%

lower than the minimum trigger frequency.
The contributions shown in Table 2 can be assumed.

Table 2

Calculation of f

fr(V)

total spread

Result for 50 to 160 Hz application:

The AGC of the vertical oscillator can be disabled by
setting control bit AGCDIS via the I

C-bus. A precise

external current has to be injected into VCAP (pin 24) to
obtain the correct vertical size. This special application
mode can be used when the vertical sync pulses are
serrated (shifted); this condition is found in some display
modes, e.g. when using a 100 Hz upconverter for video
signals.

Application hint: VAGC (pin 22) has a high input
impedance during scan. Therefore, the pin must not be
loaded externally otherwise non-linearities in the vertical
output currents may occur due to the changing charge
current during scan.

Adjustment of vertical size, VGA overscan and EHT
compensation

The amplitude of the differential output currents at VOUT1
and VOUT2 can be adjusted via register VSIZE. Register
VOVSCN can activate a +17% step in vertical size for the
VGA350 mode.

VSMOD (pin 21) can be used for a DC controlled EHT
compensation of vertical size by correcting the differential
output currents at VOUT1 and VOUT2. The EW
waveforms, vertical focus, pin unbalance and
parallelogram corrections are not affected by VSMOD.

The adjustments for vertical size and vertical position also
affect the waveforms of the horizontal pincushion, vertical
linearity (S-correction), vertical linearity balance, focus
parabola, pin unbalance and parallelogram correction.
The result of this interaction is that no re-adjustment of
these parameters is necessary after an adjustment of
vertical picture size or position.

fr V

( )

10.8

VREF

VCAP

-----------------------------------------------------------

Contributing elements

Minimum frequency offset between f

fr(V)

and

lowest trigger frequency

10%

Spread of IC

Spread of R

VREF

Spread of C

VCAP

Total

19%

fr V

( )

50 Hz

1.19

---------------

42 Hz

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

Adjustment of vertical position, vertical linearity and
vertical linearity balance

Register VPOS provides a DC shift at the sawtooth
outputs VOUT1 and VOUT2 (pins 13 and 12) and the EW
drive output EWDRV (pin 11) in such a way that the whole
picture moves vertically while maintaining the correct
geometry.

Register VLIN is used to adjust the amount of vertical
S-correction in the output signal. This function can be
switched off by control bit VSC.

Register VLINBAL is used to correct the unbalance of the
vertical S-correction in the output signal. This function can
be switched off by control bit VLC.

Adjustment of vertical moire cancellation

To achieve a cancellation of vertical moire (also known as
`scan moire') the vertical picture position can be modulated
by half the vertical frequency. The amplitude of the
modulation is controlled by register VMOIRE and can be
switched off via control bit MOD.

Horizontal pincushion (including horizontal size,
corner correction and trapezium correction)

EWDRV (pin 11) provides a complete EW drive waveform.
The components horizontal pincushion, horizontal size,
corner correction and trapezium correction are controlled
by the registers HPIN, HSIZE, HCOR and HTRAP.
HTRAP can be set to zero by control bit VPC.

The pincushion (EW parabola) amplitude, corner and
trapezium correction track with the vertical picture size
(VSIZE) and also with the adjustment for vertical picture
position (VPOS). The corner correction does not track with
the horizontal pincushion (HPIN).

Further the horizontal pincushion amplitude, corner and
trapezium correction track with the horizontal picture size,
which is adjusted via register HSIZE and the analog
modulation input HSMOD.

If the DC component in the EWDRV output signal is
increased via HSIZE or I

HSMOD

, the pincushion, corner and

trapezium component of the EWDRV output will be

reduced by a factor of

The value 14.4 V is a virtual voltage for calculation only.
The output pin can not reach this value, but the gain (and
DC bias) of the external application should be such that the
horizontal deflection is reduced to zero when EWDRV
reaches 14.4 V.

HSMOD can be used for a DC controlled EHT
compensation by correcting horizontal size, horizontal
pincushion, corner and trapezium. The control range at
this pin tracks with the actual value of HSIZE. For an
increasing DC component V

HSIZE

in the EWDRV output

signal, the DC component V

HEHT

caused by I

HSMOD

will be

reduced by a factor of

as shown in the previous

equation.

The whole EWDRV voltage is calculated as follows:
V

EWDRV

= 1.2 V + [V

HSIZE

+ V

HEHT

f(HSIZE) + (V

HPIN

HCOR

+ V

HTRAP

)

g(HSIZE, HSMOD)]

h(I

HREF

)

Where:

Two different modes of operation can be chosen for the
EW output waveform via control bit FHMULT:

1. Mode 1

Horizontal size is controlled via register HSIZE and
causes a DC shift at the EWDRV output. The complete
waveform is also multiplied internally by a signal
proportional to the line frequency [which is detected
via the current at HREF (pin 28)]. This mode is to be
used for driving EW diode modulator stages which
require a voltage proportional to the line frequency.

2. Mode 2

The EW drive waveform does not track with the line
frequency. This mode is to be used for driving EW
modulators which require a voltage independent of the
line frequency.

HSIZE

HEHT

HSIZE

14.4 V

-----------------

14.4

-------------------------------------------------------------------------

HSIZE

14.4 V

-----------------

HEHT

HSMOD

120

--------------------

0.69

f(HSIZE)

HSIZE

14.4 V

-----------------

g(HSIZE, HSMOD)

HSIZE

HEHT

HSIZE

14.4 V

-----------------

14.4 V

--------------------------------------------------------------------------

h I

HREF

(

)

HREF

70kHz

--------------------------------

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

Output stage for asymmetric correction waveforms
[ASCOR (pin 20)]

This output is designed as a voltage output for
superimposed waveforms of vertical parabola and
sawtooth. The amplitude and polarity of both signals can
be changed via registers HPARAL and HPINBAL.

Application hint: The TDA4857PS offers two possibilities
to control registers HPINBAL and HPARAL.

1. Control bit ACD = 1

The two registers now control the horizontal phase by
means of internal modulation of the PLL2 horizontal
phase control. The ASCOR output (pin 20) can be left
unused, but it will always provide an output signal
because the ASCOR output stage is not influenced by
the control bit ACD.

2. Control bit ACD = 0

The internal modulation via PLL2 is disconnected.
In order to obtain the required effect on the screen, pin
ASCOR must now be fed to the DC amplifier which
controls the DC shift of the horizontal deflection. This
option is useful for applications which already use a
DC shift transformer.

If the tube does not need HPINBAL and HPARAL, then pin
ASCOR can be used for other purposes, i.e. for a simple
dynamic convergence.

Dynamic focus section [FOCUS (pin 32)]

This section generates a complete drive signal for dynamic
focus applications. The amplitude of the vertical parabola
is independent of frequency and tracks with all vertical
adjustments. The amplitude can be adjusted via register
VFOCUS. FOCUS (pin 32) is designed as a voltage output
for the vertical parabola.

B+ control function block

The B+ control function block of the TDA4857PS consists
of an Operational Transconductance Amplifier (OTA), a
voltage comparator, a flip-flop and a discharge circuit. This
configuration allows easy applications for different B+
control concepts. See also Application Note AN96052:

"B+

converter Topologies for Horizontal Deflection and EHT
with TDA4855/58".

ENERAL DESCRIPTION

The non-inverting input of the OTA is connected internally
to a high precision reference voltage. The inverting input is
connected to BIN (pin 5). An internal clamping circuit limits
the maximum positive output voltage of the OTA.
The output itself is connected to BOP (pin 3) and to the
inverting input of the voltage comparator.
The non-inverting input of the voltage comparator can be
accessed via BSENS (pin 4).

B+ drive pulses are generated by an internal flip-flop and
fed to BDRV (pin 6) via an open-collector output stage.
This flip-flop is set at the rising edge of the signal at HDRV
(pin 8). The falling edge of the output signal at BDRV has
a defined delay of t

d(BDRV)

to the rising edge of the HDRV

pulse (see Fig.21). When the voltage at BSENS exceeds
the voltage at BOP, the voltage comparator output resets
the flip-flop and, therefore, the open-collector stage at
BDRV is floating again.

An internal discharge circuit allows a well defined
discharge of capacitors at BSENS. BDRV is active at a
LOW-level output voltage (see Figs 21 and 22), thus it
requires an external inverting driver stage.

The B+ function block can be used for B+ deflection
modulators in many different ways. Two popular
application combinations are as follows:

Boost converter in feedback mode (see Fig.21)

In this application the OTA is used as an error amplifier
with a limited output voltage range. The flip-flop is set on
the rising edge of the signal at HDRV. A reset will be
generated when the voltage at BSENS, taken from the
current sense resistor, exceeds the voltage at BOP.

If no reset is generated within a line period. The rising
edge of the next HDRV pulse forces the flip-flop to reset.
The flip-flop is set immediately after the voltage at
BSENS has dropped below the threshold voltage
V

RESTART(BSENS)

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

Buck converter in feed forward mode (see Fig.22)

This application uses an external RC combination at
BSENS to provide a pulse width which is independent
from the horizontal frequency. The capacitor is charged
via an external resistor and discharged by the internal
discharge circuit. For normal operation the discharge
circuit is activated when the flip-flop is reset by the
internal voltage comparator. The capacitor will now be
discharged with a constant current until the internally
controlled stop level V

STOP(BSENS)

is reached. This level

will be maintained until the rising edge of the next HDRV
pulse sets the flip-flop again and disables the discharge
circuit.

If no reset is generated within a line period, the rising
edge of the next HDRV pulse automatically starts the
discharge sequence and resets the flip-flop. When the
voltage at BSENS reaches the threshold voltage
V

RESTART(BSENS)

, the discharge circuit will be disabled

automatically and the flip-flop will be set immediately.
This behaviour allows a definition of the maximum duty
cycle of the B+ control drive pulse by the relationship of
charge current to discharge current.

Supply voltage stabilizer, references, start-up
procedures and protection functions

The TDA4857PS incorporates an internal supply voltage
stabilizer to provide excellent stabilization for all internal
references. An internal gap reference, especially designed
for low-noise, is the reference for the internal horizontal
and vertical supply voltages. All internal reference currents
and drive current for the vertical output stage are derived
from this voltage via external resistors.

If either the supply voltage is below 8.3 V or no data from
the I

C-bus has been received after power-up, the internal

soft start and protection functions do not allow any of those
outputs [HDRV, BDRV, VOUT1, VOUT2 and HUNLOCK
(see Fig.23)] to be active.

For supply voltages below 8.3 V the internal I

C-bus will

not generate an acknowledge and the IC is in standby
mode. This is because the internal protection circuit has
generated a reset signal for the soft start register SOFTST.
Above 8.3 V data is accepted and all registers can be
loaded. If register SOFTST has received a set from the
I

C-bus, the internal soft start procedure is released, which

activates all mentioned outputs.

If during normal operation the supply voltage has dropped
below 8.1 V, the protection mode is activated and
HUNLOCK (pin 17) changes to the protection status and is
floating. This can be detected by the microcontroller.

This protection mode has been implemented in order to
protect the deflection stages and the picture tube during
start-up, shut-down and fault conditions. This protection
mode can be activated as shown in Table 3.

Table 3

Activation of protection mode

When the protection mode is active, several pins of the
TDA4857PS are forced into a defined state:

HDRV (horizontal driver output) is floating

BDRV (B+ control driver output) is floating

HUNLOCK (indicates, that the frequency-to-voltage
converter is out of lock) is floating (HIGH via external
pull-up resistor)

CLBL provides a continuous blanking signal

VOUT1 and VOUT2 (vertical outputs) are floating

The capacitor at HPLL2 is discharged.

If the soft start procedure is activated via the I

C-bus, all of

these actions will be performed in a well defined sequence
(see Figs 23 and 24).

ACTIVATION

RESET

Low supply voltage at
pin 10

increase supply voltage;
reload registers;
soft start via I

C-bus

Power dip, below 8.1 V

reload registers;
soft start via I

C-bus

X-ray protection (pin 2)
triggered, XSEL (pin 9) is
open-circuit or connected
to ground

reload registers;
soft start via I

C-bus

X-ray protection (pin 2)
triggered, XSEL (pin 9)
connected to V

via an

external resistor

switch V

off and on

again, reload registers;
soft start via I

C-bus

HPLL2 (pin 30) externally
pulled to ground

release pin 30

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); all voltages measured with respect to ground.

Notes

1. Machine model: 200 pF; 0.75

H; 10

2. Human body model: 100 pF; 7.5

H; 1500

THERMAL CHARACTERISTICS

QUALITY SPECIFICATION
In accordance with

"URF-4-2-59/601"; EMC emission/immunity test in accordance with "DIS 1000 4.6" (IEC 801.6).

Note

1. Tests are performed with application reference board. Tests with other boards will have different results.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

supply voltage

0.5

+16

i(n)

input voltage for pins:

BIN

0.5

+6.0

HSYNC, VSYNC, VREF, HREF, VSMOD and HSMOD

0.5

+6.5

SDA and SCL

0.5

+8.0

XRAY

0.5

+8.0

o(n)

output voltage for pins:

VOUT2, VOUT1 and HUNLOCK

0.5

+6.5

BDRV and HDRV

0.5

+16

I/O(n)

input/output voltages at pins BOP and BSENS

0.5

+6.0

o(HDRV)

horizontal driver output current

100

i(HFLB)

horizontal flyback input current

+10

o(CLBL)

video clamping pulse/vertical blanking output current

o(BOP)

B+ control OTA output current

o(BDRV)

B+ control driver output current

o(EWDRV)

EW driver output current

o(FOCUS)

focus driver output current

amb

ambient temperature

+70

junction temperature

150

stg

storage temperature

+150

ESD

electrostatic discharge for all pins

note 1

150

+150

note 2

2000

+2000

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th(j-a)

thermal resistance from junction to ambient

in free air

K/W

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

EMC

emission test

note 1

1.5

immunity test

note 1

2.0

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

CHARACTERISTICS
V

= 12 V; T

amb

= 25

C; peripheral components in accordance with Fig.1; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Horizontal sync separator

NPUT CHARACTERISTICS FOR

DC-

COUPLED

TTL

SIGNALS

HSYNC

i(HSYNC)

sync input signal voltage

1.7

HSYNC(sl)

slicing voltage level

1.2

1.4

1.6

r(HSYNC)

rise time of sync pulse

500

f(HSYNC)

fall time of sync pulse

500

W(HSYNC)(min)

minimum width of sync pulse

0.7

i(HSYNC)

input current

HSYNC

= 0.8 V

200

HSYNC

= 5.5 V

NPUT CHARACTERISTICS FOR

AC-

COUPLED VIDEO SIGNALS

(

SYNC

VIDEO

NEGATIVE SYNC POLARITY

)

HSYNC

sync amplitude of video input
signal voltage

source

= 50

300

HSYNC(sl)

slicing voltage level
(measured from top sync)

source

= 50

120

150

clamp(HSYNC)

top sync clamping voltage level R

source

= 50

1.1

1.28

1.5

ch(HSYNC)

charge current for coupling
capacitor

HSYNC

> V

clamp(HSYNC)

1.7

2.4

3.4

W(HSYNC)(min)

minimum width of sync pulse

0.7

source(max)

maximum source resistance

duty cycle = 7%

1500

i(diff)(HSYNC)

differential input resistance

during sync

Automatic polarity correction for horizontal sync

horizontal sync pulse width
related to line period

d(HPOL)

delay time for changing polarity

0.3

1.8

Vertical sync integrator

int(V)

integration time for generation
of a vertical trigger pulse

= 15.625 kHz;

HREF

= 0.52 mA

= 31.45 kHz;

HREF

= 1.052 mA

= 64 kHz;

HREF

= 2.141 mA

3.9

5.7

6.5

= 100 kHz;

HREF

= 3.345 mA

2.5

3.8

4.5

Vertical sync slicer (DC-coupled, TTL compatible): pin VSYNC

i(VSYNC)

sync input signal voltage

1.7

VSYNC(sl)

slicing voltage level

1.2

1.4

1.6

i(VSYNC)

input current

0 V < V

SYNC

< 5.5 V

P H

( )

------------

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

Automatic polarity correction for vertical sync

W(VSYNC)(max)

maximum width of vertical sync
pulse

400

d(VPOL)

delay time for changing polarity

0.45

1.8

Video clamping/vertical blanking output: pin CLBL

clamp(CLBL)

width of video clamping pulse

measured at V

CLBL

= 3 V

0.6

0.7

0.8

clamp(CLBL)

top voltage level of video
clamping pulse

4.32

4.75

5.23

clamp

temperature coefficient of
V

clamp(CLBL)

mV/K

STPS

clamp

steepness of slopes for
clamping pulse

= 1 M

; C

= 20 pF

ns/V

d(HSYNCt-CLBL)

delay between trailing edge of
horizontal sync and start of
video clamping pulse

clamping pulse triggered
on trailing edge of
horizontal sync;
control bit CLAMP = 0;
measured at V

CLBL

= 3 V

130

clamp1(max)

maximum duration of video
clamping pulse referenced to
end of horizontal sync

1.0

d(HSYNCl-CLBL)

delay between leading edge of
horizontal sync and start of
video clamping pulse

clamping pulse triggered
on leading edge of
horizontal sync;
control bit CLAMP = 1;
measured at V

CLBL

= 3 V

300

clamp2(max)

maximum duration of video
clamping pulse referenced to
end of horizontal sync

0.15

blank(CLBL)

top voltage level of vertical
blanking pulse

notes 1 and 2

1.7

1.9

2.1

blank(CLBL)

width of vertical blanking pulse
at pins CLBL and HUNLOCK

control bit VBLK = 0

220

260

300

control bit VBLK = 1

305

350

395

blank

temperature coefficient of
V

blank(CLBL)

mV/K

scan(CLBL)

output voltage during vertical
scan

CLBL

= 0

0.59

0.63

0.67

scan

temperature coefficient of
V

scan(CLBL)

mV/K

sink(CLBL)

internal sink current

2.4

L(CLBL)

external load current

3.0

Horizontal oscillator: pins HCAP and HREF

fr(H)

free-running frequency without
PLL1 action (for testing only)

HBUF

;

HREF

= 2.4 k

;

HCAP

= 10 nF; note 3

30.53

31.45

32.39

kHz

fr(H)

spread of free-running
frequency (excluding spread of
external components)

3.0

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2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

temperature coefficient of
free-running frequency

100

+100

H(max)

maximum oscillator frequency

130

kHz

HREF

voltage at input for reference
current

2.43

2.55

2.68

Unlock blanking detection: pin HUNLOCK

scan(HUNLOCK)

low level voltage of HUNLOCK

saturation voltage in case
of locked PLL1; internal
sink current = 1 mA

250

blank(HUNLOCK)

blanking level of HUNLOCK

external load current = 0

0.9

1.1

blank

temperature coefficient of
V

blank(HUNLOCK)

0.9

mV/K

sink

temperature coefficient of
I

sink(HUNLOCK)

0.15

%/K

sink(int)

internal sink current

for blanking pulses;
PLL1 locked

1.4

2.0

2.6

L(max)

maximum external load current V

HUNLOCK

= 1 V

leakage current

HUNLOCK

= 5 V in case of

unlocked PLL1 and/or
protection active

PLL1 phase comparator and frequency-locked loop: pins HPLL1 and HBUF

W(HSYNC)(max)

maximum width of horizontal
sync pulse (referenced to line
period)

lock(HPLL1)

total lock-in time of PLL1

ctrl(HPLL1)

control currents

notes 4 and 5

locked mode, level 1

locked mode, level 2

145

HBUF

buffered f/v voltage at HBUF
(pin 27)

minimum horizontal
frequency

2.5

maximum horizontal
frequency

0.5

Phase adjustments and corrections via PLL1 and PLL2

HPOS

horizontal position (referenced
to horizontal period)

HPINBAL

horizontal pin unbalance
correction via HPLL2
(referenced to horizontal
period)

0.8

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2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

HPARAL

horizontal parallelogram
correction (referenced to
horizontal period)

0.8

HMOIRE

relative modulation of
horizontal position by 0.5f

;

phase alternates with 0.5f

0.05

HMOIRE

off

moire cancellation off

control bit MOD = 1

PLL2 phase detector: pins HFLB and HPLL2

PLL2

PLL2 control (advance of
horizontal drive with respect to
middle of horizontal flyback)

maximum advance;
register HPINBAL = 07;
register HPARAL = 07

minimum advance;
register HPINBAL = 07;
register HPARAL = 07

ctrl(PLL2)

PLL2 control current

PLL2

relative sensitivity of PLL2
phase shift related to
horizontal period

mV/%

PROT(PLL2)(max)

maximum voltage for PLL2
protection mode/soft start

4.4

ch(PLL2)

charge current for external
capacitor during soft start

HPLL2

< 3.7 V

ORIZONTAL FLYBACK INPUT

HFLB

pos(HFLB)

positive clamping voltage

HFLB

= 5 mA

5.5

neg(HFLB)

negative clamping voltage

HFLB

1 mA

0.75

pos(HFLB)

positive clamping current

neg(HFLB)

negative clamping current

sl(HFLB)

slicing level

2.8

Output stage for line driver pulses: pin HDRV

PEN

COLLECTOR OUTPUT STAGE

sat(HDRV)

saturation voltage

HDRV

= 20 mA

0.3

HDRV

= 60 mA

0.8

LO(HDRV)

output leakage current

HDRV

= 16 V

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2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

UTOMATIC VARIATION OF DUTY CYCLE

; see Fig.14

HDRV(OFF)

relative t

OFF

time of HDRV

output; measured at
V

HDRV

= 3 V; HDRV duty cycle

is modulated by the relation
I

HREF

VREF

HDRV

= 20 mA;

= 31.45 kHz

HDRV

= 20 mA;

= 58 kHz

45.5

48.5

51.5

HDRV

= 20 mA;

= 110 kHz

X-ray protection: pins XRAY and XSEL

XRAY(sl)

slicing voltage level for latch

6.22

6.39

6.56

W(XRAY)(min)

minimum width of trigger pulse

i(XRAY)

input resistance at pin 2

XRAY

< 6.38 V + V

500

XRAY

> 6.38 V + V

standby mode

XRAY

rst

reset of X-ray latch

pin 9 open-circuit or
connected to GND

set control bit SOFTST via
the I

C-bus

pin 9 connected to V

via

XSEL

switch off V

then

re-apply V

CC(XRAY)(min)

minimum supply voltage for
correct function of the X-ray
latch

pin 9 connected to V

via

XSEL

CC(XRAY)(max)

maximum supply voltage for
reset of the X-ray latch

pin 9 connected to V

via

XSEL

external resistor at pin 9

no reset via I

C-bus

130

Vertical oscillator [oscillator frequency in application without adjustment of free-running frequency f

fr(V)

]

fr(V)

free-running frequency

VREF

= 22 k

;

VCAP

= 100 nF

43.3

cr(V)

vertical frequency catching
range

constant amplitude; note 7 50

160

VREF

voltage at reference input for
vertical oscillator

3.0

d(scan)

delay between trigger pulse
and start of ramp at VCAP
(pin 24) (width of vertical
blanking pulse)

control bit VBLK = 0

220

260

300

control bit VBLK = 1

305

350

395

VAGC

amplitude control current

control bit AGCDIS = 0

120

200

300

control bit AGCDIS = 1

VAGC

external capacitor at VAGC
(pin 22)

150

220

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2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

Differential vertical current outputs

DJUSTMENT OF VERTICAL SIZE INCLUDING

VGA

AND

EHT

COMPENSATION

; see Fig.3

VSIZE

vertical size without VGA
overscan (referenced to
nominal vertical size)

100

VSIZE

VGA

vertical size with VGA
overscan (referenced to
nominal vertical size)

115.9

116.8

117.7

VSMOD

EHT

EHT compensation on vertical
size via VSMOD (pin 21)
(referenced to 100% vertical
size)

VSMOD

= 0

VSMOD

120

i(VSMOD)

input current (pin 21)

VSMOD = 0

VSMOD =

120

i(VSMOD)

input resistance

300

500

ref(VSMOD)

reference voltage at input

5.0

ro(VSMOD)

roll-off frequency (

3 dB)

VSMOD

+ 15

A (RMS)

MHz

DJUSTMENT OF VERTICAL POSITION

; see Fig.4

VPOS

vertical position (referenced to
100% vertical size)

11.5

DJUSTMENT OF VERTICAL LINEARITY

; see Fig.5

VLIN

vertical linearity (S-correction)

VLIN

symmetry error of S-correction

maximum VLIN

0.7

DJUSTMENT OF VERTICAL LINEARITY BALANCE

; see Fig.6

VLINBAL

vertical linearity balance
(referenced to 100% vertical
size)

3.3

2.5

1.7

2.5

3.3

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2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

VMOIRE

modulation of vertical picture
position by

vertical

frequency (related to 100%
vertical size)

0.08

moire cancellation off

control bit MOD = 1

Vertical output stage: pins VOUT1 and VOUT2; see Fig.27

VOUT(nom)(p-p)

nominal differential output
current (peak-to-peak value)

VOUT

= I

VOUT1

VOUT2

;

nominal settings; note 8

0.76

0.85

0.94

o(VOUT)(max)

maximum output current at
pins VOUT1 and VOUT2

control bit VOVSCN = 1

0.54

0.6

0.66

VOUT

allowed voltage at outputs

4.2

os(vert)(max)

maximum offset error of
vertical output currents

nominal settings; note 8

2.5

lin(vert)(max)

maximum linearity error of
vertical output currents

nominal settings; note 8

1.5

EW drive output

DRIVE OUTPUT STAGE

EWDRV; see Figs 7 to 10

const(EWDRV)

bottom output voltage at pin
EWDRV (internally stabilized)

1.05

1.2

1.35

o(EWDRV)(max)

maximum output voltage

note 9

7.0

L(EWDRV

)

load current

EWDRV

temperature coefficient of
output signal

600

HPIN(EWDRV)

horizontal pincushion voltage

0.04

1.42

HCOR(EWDRV)

horizontal corner correction
voltage

0.08

0.64

HTRAP(EWDRV)

horizontal trapezium correction
voltage

0.33

HSIZE(EWDRV)

horizontal size voltage

0.13

3.6

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2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

HEHT(EWDRV)

EHT compensation on
horizontal size via HSMOD
(pin 31)

HSMOD

= 0; note 8

0.69

HSMOD

120

A; note 8

0.02

i(HSMOD)

input current (pin 31)

HEHT

= 0.02 V

HEHT

= 0.69 V

120

i(HSMOD)

input resistance

300

500

ref(HSMOD)

reference voltage at input

HSMOD

= 0

5.0

ro(HSMOD)

roll-off frequency (

3 dB)

HSMOD

A + 15

(RMS)

MHz

RACKING OF

EWDRV

OUTPUT SIGNAL WITH HORIZONTAL FREQUENCY PROPORTIONAL VOLTAGE

H(MULTI)

horizontal frequency range for
tracking

kHz

PAR(EWDRV)

parabola amplitude at EWDRV
(pin 11)

HREF

= 1.052 mA;

= 31.45 kHz;

control bit FHMULT = 1;
note 10

0.72

HREF

= 2.341 mA;

= 70 kHz;

control bit FHMULT = 1;
note 10

1.42

function disabled;
control bit FHMULT = 0;
note 10

1.42

EWDRV

linearity error of horizontal
frequency tracking

Output for asymmetric EW corrections: pin ASCOR

HPARAL(ASCOR)

vertical sawtooth voltage for
EW parallelogram correction

0.825

0.05

HPINBAL(ASCOR)

vertical parabola voltage for pin
unbalance correction

1.0

0.05

o(ASCOR)(max)(p-p)

maximum output voltage swing
(peak-to-peak value)

o(ASCOR)(max)

maximum output voltage

6.5

c(ASCOR)

centre voltage

4.0

o(ASCOR)(min)

minimum output voltage

1.9

o(ASCOR)(max)

maximum output current

ASCOR

1.9 V

1.5

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2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

o(sink)(ASCOR)(max)

maximum output sink current

ASCOR

1.9 V

Focus section: pin FOCUS

VFOCUS(p-p)

amplitude of vertical parabola
(peak-to-peak value)

0.02

0.8

o(FOCUS)(max)

maximum output voltage

FOCUS

= 0

5.7

6.3

o(FOCUS)(min)

minimum output voltage

FOCUS

= 0

4.9

5.2

5.7

o(FOCUS)(max)

maximum output current

1.5

L(FOCUS)(max)

maximum capacitive load

B+ control section; see Figs 21 and 22

RANSCONDUCTANCE AMPLIFIER

PINS

BIN

AND

BOP

i(BIN)

input voltage pin 5

5.25

i(BIN)(max)

maximum input current pin 5

ref(int)

reference voltage at internal
non-inverting input of OTA

2.37

2.5

2.58

o(BOP)(min)

minimum output voltage pin 3

0.5

o(BOP)(max)

maximum output voltage pin 3

BOP

< 1 mA

5.0

5.3

5.6

o(BOP)(max)

maximum output current pin 3

500

m(OTA)

transconductance of OTA

note 11

v(ol)

open-loop voltage gain

note 12

BOP(min)

minimum value of capacitor at
pin 3

OLTAGE COMPARATOR

BSENS

i(BSENS)

voltage range of positive
comparator input

i(BOP)

voltage range of negative
comparator input

LI(BSENS)(max)

maximum leakage current

discharge disabled

PEN

COLLECTOR OUTPUT STAGE

BDRV

o(BDRV)(max)

maximum output current

LO(BDRV)

output leakage current

BDRV

= 16 V

sat(BDRV)

saturation voltage

BDRV

< 20 mA

300

off(BDRV)(min)

minimum off-time

250

d(BDRV-HDRV)

delay between BDRV pulse
and HDRV pulse

measured at
V

HDRV

= V

BDRV

= 3 V

500

BSENS

DISCHARGE CIRCUIT

BSENS

STOP(BSENS)

discharge stop level

capacitive load;
I

BSENS

= 0.5 mA

0.85

1.0

1.15

dch(BSENS)

discharge current

BSENS

> 2.5 V

4.5

6.0

7.5

th(BSENS)(restart)

threshold voltage for restart

fault condition

1.2

1.3

1.4

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

BSENS(min)

minimum value of capacitor at
BSENS (pin 4)

Internal reference, supply voltage, soft start and protection

CC(stab)

external supply voltage for
complete stabilization of all
internal references

9.2

supply current

CC(stb)

standby supply current

STDBY = 1; V

PLL2

< 1 V;

3.5 V < V

< 16 V

PSRR

power supply rejection ratio of
internal supply voltage

f = 1 kHz

CC(blank)

supply voltage level for
activation of continuous
blanking

decreasing from 12 V

8.2

8.6

9.0

CC(blank)(min)

minimum supply voltage level
for function of continuous
blanking

decreasing from 12 V

2.5

3.5

4.0

on(VCC)

supply voltage level for
activation of HDRV, BDRV,
VOUT1, VOUT2 and
HUNLOCK

increasing from below

typical 8 V

7.9

8.3

8.7

off(VCC)

supply voltage level for
deactivation of BDRV, VOUT1,
VOUT2 and HUNLOCK; also
sets register SOFTST

decreasing from

above typical 8.3 V

7.7

8.1

8.5

HRESHOLDS DERIVED FROM

HPLL2

VOLTAGE

HPLL2(blank)(ul)

upper limit voltage for
continuous blanking

4.7

HPLL2(bduty)(ul)

upper limit voltage for variation
of BDRV duty cycle

3.4

HPLL2(bduty)(ll)

lower limit voltage for variation
of BDRV duty cycle

2.8

HPLL2(hduty)(ul)

upper limit voltage for variation
of HDRV duty cycle

2.8

HPLL2(hduty)(ll)

lower limit voltage for variation
of HDRV duty cycle

1.7

HPLL2(stby)(ll)

lower limit voltage for VOUT1
and VOUT2 to be active via
I

C-bus soft start

1.1

HPLL2(stby)(ul)

upper limit voltage for standby
voltage

HPLL2(stby)(ll)

lower limit voltage for VOUT1
and VOUT2 to be active via
external DC current

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

Notes

1. For duration of vertical blanking pulse see subheading `Vertical oscillator [oscillator frequency in application without

adjustment of free-running frequency f

fr(V)

]'.

2. Continuous blanking at CLBL (pin 16) will be activated, if one of the following conditions is true:

a) No horizontal flyback pulses at HFLB (pin 1) within a line

b) X-ray protection is triggered

c) Voltage at HPLL2 (pin 30) is low during soft start

d) Supply voltage at V

(pin 10) is low

e) PLL1 unlocked while frequency-locked loop is in search mode.

3. Oscillator frequency is f

min

when no sync input signal is present (continuous blanking at pins 16 and 17).

4. Loading of HPLL1 (pin 26) is not allowed.

5. Voltage at HPLL1 (pin 26) is fed to HBUF (pin 27) via a buffer. Disturbances caused by horizontal sync are removed

by an internal sample-and-hold circuit.

6. All vertical and EW adjustments in accordance with note 8, but VSIZE = 80% (register VSIZE = 63 and control

bit VOVSCN = 0).

7. Value of resistor at VREF (pin 23) may not be changed.

8. All vertical and EW adjustments are specified at nominal vertical settings; unless otherwise specified, which means:

a) VSIZE = 100% (register VSIZE = 127 and control bit VOVSCN = 0)

b) VSMOD = 0 (no EHT compensation)

c) VPOS centred (register VPOS = X and control bit VPC = 1)

d) VLIN = 0 (register VLIN = X and control bit VSC = 1)

e) VLINBAL = 0 (register VLINBAL = X and control bit VLC = 1)

f) FHMULT = 0

g) HPARAL = 0 (register HPARAL = X and control bit HPC = 1)

h) HPINBAL = 0 (register HPINBAL = X and control bit HBC = 1)

Vertical oscillator synchronized

HSIZE = 255.

9. The output signal at EWDRV (pin 11) may consist of horizontal pincushion + corner correction + DC shift +

trapezium correction. If the control bit VOVSCN is set, and the VPOS adjustment is set to an extreme value, the tip
of the parabola may be clipped at the upper limit of the EWDRV output voltage range. The waveform of corner
correction will clip if the vertical sawtooth adjustment exceeds 110% of the nominal setting.

10. If f

tracking is enabled, the amplitude of the complete EWDRV output signal (horizontal pincushion + corner

correction + DC shift + trapezium) will be changed proportional to I

HREF

. The EWDRV low level of 1.2 V remains

fixed.

11. First pole of transconductance amplifier is 5 MHz without external capacitor (will become the second pole, if the OTA

operates as an integrator).

12. Open-loop gain is

at f = 0 with no resistive load and C

BOP

= 10 nF [from BOP (pin 3) to GND].

BOP

BIN

--------------

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

Vertical and EW adjustments

handbook, halfpage

IVOUT1

IVOUT2

(1)

MBG590

Fig.3 Adjustment of vertical size.

(1)

is the maximum amplitude setting at register VSIZE = 127,

control bit VOVSCN = 0, control bit VPC = 1,
control bit VSC = 1 and control bit VLC = 1.

VSIZE

--------

100%

VSMOD

--------

100%

handbook, halfpage

IVOUT1

IVOUT2

(1)

MBG592

Fig.4 Adjustment of vertical position.

(1)

is the maximum amplitude setting at register VSIZE = 127

and control bit VPC = 1.

VPOS

----------------------

100%

Fig.5

Adjustment of vertical linearity (vertical
S-correction).

(1)

is the maximum amplitude setting at register VSIZE = 127

and VLIN = 0%.

VLIN

----------------------

100%

handbook, halfpage

IVOUT1

IVOUT2

(1)

MBG594

handbook, halfpage

IVOUT1

IVOUT2

(1)

MGM068

Fig.6 Adjustment of vertical linearity balance.

(1)

is the maximum amplitude setting at register VSIZE = 127,

VLINBAL

----------------------

100%

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

C-BUS PROTOCOL

C-bus data format

Notes

1. S = START condition.

2. SLAVE ADDRESS (MAD) = 1000 1100.

3. A = acknowledge, generated by the slave. No acknowledge, if the supply voltage is below 8.3 V for start-up and 8.1 V

for shut-down procedure.

4. SUBADDRESS (SAD).

5. DATA, if more than 1 byte of DATA is transmitted, then no auto-increment of the significant subaddress is performed.

6. P = STOP condition.

It should be noted that clock pulses according to the 400 kHz specification are accepted for 3.3 and 5 V applications
(reference level = 1.8 V). Default register values after power-up are random. All registers have to be preset via software
before the soft start is enabled.

Important: If the register contents are changed during the vertical scan, this might result in a visible interference on the
screen. The cause for this interference is the abrupt change in picture geometry which takes effect at random locations
within the visible picture.

To avoid this kind of interference, the adjustment of the critical geometry parameters HSIZE, HPOS, VSIZE and VPOS
should be synchronized with the vertical flyback. This should be done in such a way that the adjustment change takes
effect during the vertical blanking time (see Fig.17).

For very slow I

C-bus interfaces, it might be necessary to delay the transmission of the last byte (or only the last bit) of

an I

C-bus message until the start of the vertical sync or vertical blanking.

(1)

SLAVE ADDRESS

(2)

(3)

SUBADDRESS

(4)

(3)

DATA

(5)

(3)

(6)

handbook, full pagewidth

MGM088

vertical

sync pulse

vertical

blanking pulse

SDA

parameter change takes effect

Fig.17 Timing of the I

C-bus transmission for interference-free adjustment.

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

Table 4

List of I

C-bus controlled switches; notes 1 and 2

Notes

1. X = don't care.

2. # = this bit is occupied by another function. If the register is addressed, the bit values for both functions must be

transferred.

3. Bits STDBY and SOFTST can be reset by internal protection circuit.

CONTROL

BIT

FUNCTION

SAD

(HEX)

REGISTER ASSIGNMENT

D7 D6 D5 D4 D3 D2 D1 D0

BLKDIS

0: vertical, protection and horizontal unlock blanking
available on pins CLBL and HUNLOCK

1: only vertical and protection blanking available on
pins CLBL and HUNLOCK

HBC

0: HPINBAL (parabola) waveform enabled

D1 #

1: HPINBAL (parabola) waveform disabled

HPC

0: HPARAL (sawtooth) waveform enabled

D2 #

1: HPARAL (sawtooth) waveform disabled

AGCDIS

0: AGC in vertical oscillator active

D3 #

1: AGC in vertical oscillator inhibited

VSC

0: VLIN and HCOR adjustments enabled

D4 #

1: VLIN and HCOR adjustments forced to centre value

MOD

0: horizontal and vertical moire cancellation enabled

D5 #

1: horizontal and vertical moire cancellation disabled

FHMULT

0: EW output independent of horizontal frequency

1: EW output tracks with horizontal frequency

VOVSCN

0: vertical size 100%

D2 X

1: vertical size 116.8% for VGA350

CLAMP

0: trailing edge for horizontal clamp

D3 #

1: leading edge for horizontal clamp

VBLK

0: vertical blanking = 260

D4 #

1: vertical blanking = 340

VLC

0: VLINBAL adjustment enabled

D5 #

1: VLINBAL adjustment forced to centre value

VPC

0: VPOS and HTRAP adjustments enabled

D6 #

1: VPOS and HTRAP adjustments forced to centre value

ACD

0: ASCOR disconnected from PLL2

D7 #

1: ASCOR internally connected with PLL2

STDBY

(3)

0: internal power supply enabled

1: internal power supply disabled

SOFTST

(3)

0: soft start not released (pin HPLL2 pulled to ground)

D1 #

1: soft start is released (power-up via pin HPLL2)

2000

Jan

Philips Semiconductors

Product specification

C-b

us autosync deflection controller f

PC monitors

TD
A4857PS

Table 5

List of I

C-bus controlled functions and those accessible by pins; notes 1 and 2

Notes

1. X = don't care.

2. # = this bit is occupied by another function. If the register is addressed, the bit values for both functions must be transferred.

FUNCTION

NAME

BITS

SAD

(HEX)

REGISTER ASSIGNMENT

CONTROL

BIT

RANGE

FUNCTION

TRACKS WITH

Horizontal size

HSIZE

0.1 to 3.6 V

HSMOD

Vertical position

VPOS

VPC

11.5%

VSMOD

Vertical linearity
balance

VLINBAL

VLC

2.5% of 100%

vertical size

VSIZE, VOVSCN,
VPOS and VSMOD

Moire cancellation via
vertical position

VMOIRE

MOD

0 to 0.08% of
vertical amplitude

Horizontal pincushion

HPIN

0 to 1.44 V

VSIZE, VOVSCN,
VPOS, HSIZE and
HSMOD

Moire cancellation via
horizontal position

HMOIRE

MOD

0 to 0.05% of
horizontal period

Horizontal position

HPOS

13% of horizontal

period

Vertical linearity

VLIN

VSC

2 to

46%

VSIZE, VOVSCN,
VPOS and VSMOD

EW pin balance

HPINBAL

HBC and

ACD

1% of

horizontal period

VSIZE, VOVSCN
and VPOS

Vertical size

VSIZE

60 to 100%

VSMOD

Horizontal corner
correction

HCOR

VSC

+6 to

46% of

parabola amplitude

VSIZE, VOVSCN,
VPOS, HSIZE and
HSMOD

Horizontal trapezium
correction

HTRAP

VPC

0.33 V

VSIZE, VOVSCN,
VPOS, HSIZE and
HSMOD

Horizontal
parallelogram

HPARAL

HPC and

ACD

1% of horizontal

period

VSIZE, VOVSCN
and VPOS

Vertical focus

VFOCUS

0 to 25%

VSIZE, VOVSCN
and VPOS

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

Start-up procedure

< 8.3 V:

As long as the supply voltage is too low for correct
operation, the IC will give no acknowledge due to
internal Power-on reset (POR)

Supply current is 9 mA or less.

> 8.3 V:

The internal POR has ended and the IC is in standby
mode

Control bits STDBY and SOFTST are reset to their start
values

All other register contents are random

Pin HUNLOCK is at HIGH-level.

Setting control bit STDBY = 0:

Enables internal power supply

Supply current increases from 9 to 70 mA

When V

< 8.6 V register SOFTST cannot be set by

the I

C-bus

Output stages are disabled, except the vertical output

Pin HUNLOCK is at HIGH-level.

Setting all registers to defined values:

Due to the hardware configuration of the IC
(no auto-increment) any register setting needs a
complete 3-byte I

C-bus data transfer as follows:

START - IC address - subaddress - data - STOP.

Setting control bit SOFTST = 1:

Before starting the soft-start sequence a delay of
minimum 80 ms is necessary to obtain correct function
of the horizontal drive

HDRV duty cycle increases

BDRV duty cycle increases

PLL1 and PLL2 are enabled.

IC in full operation:

Pin HUNLOCK is at LOW-level when PLL1 is locked

Any change of the register content will result in
immediate change of the output behaviour

Setting control bit SOFTST = 0 is the only way (except
power-down via pin V

) to leave the operating mode.

Soft-down sequence:

See L4 of Fig.19 for starting the soft-down sequence.

MGM078

START

Standby mode (XXXX XX01)

STDBY = 1

SOFTST = 0

all other register contents are random

Protection mode (XXXX XX00)

STDBY = 0

SOFTST = 0

all other register contents are random

Protection mode (XXXX XX00)

STDBY = 0

SOFTST = 0

registers are pre-set

change/refresh of data?

8CH

0DH

00H

A P

8CH

0DH

02H

A P

8CH

SAD

DATA

A P

8CH

SAD

DATA

A P

Operating mode (XXXX XX10)

STDBY = 0

SOFTST = 1

Soft-start sequence (XXXX XX10)

STDBY = 0

SOFTST = 1

Power-down mode (XXXX XXXX)

no acknowledge is given by IC

all register contents are random

(1)

VCC

8.3 V

yes

SOFTST = 0?

yes

all registers defined?

yes

Fig.18 I

C-bus flow for start-up.

(1) See Fig.19.

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

Protection and standby mode

Soft-down sequence:

Start the sequence by setting control bit SOFTST = 0

BDRV duty cycle decreases

HDRV duty cycle decreases.

Protection mode:

Pins HDRV and BDRV are floating

Continuous blanking at pin CLBL is active

Pin HUNLOCK is floating

PLL1 and PLL2 are disabled

Protection mode can be left by 3 ways:

1. Entering standby mode by setting control

bit SOFTST = 0 and control bit STDBY = 1

2. Starting the soft-start sequence by setting control

bit SOFTST = 1 (bit STDBY = don't care);
see L3 of Fig.18 for continuation

3. Decreasing the supply voltage below 8.1 V.

Standby mode:

Set control bit STDBY = 1

Driver outputs are floating (same as protection mode)

Supply current is 9 mA

Only the I

C-bus and protection circuits are operative

Contents of all registers except the value of bit STDBY
and bit SOFTST are lost

See L2 of Fig.18 for continuation.

MBK382

Standby mode (XXXX XX01)

STDBY = 1

SOFTST = 0

all other register contents are random

Soft-down sequence (XXXX XX00)

STDBY = 0

SOFTST = 0

(1)

yes

SOFTST = 1?

yes

(1)

Protection mode (XXXX XX00)

STDBY = 0

SOFTST = 0

registers are set

STDBY = 1?

8CH

0DH

00H

A P

8CH

0DH

01H

A P

Fig.19 I

C-bus flow for protection and standby

mode.

(1) See Fig.18.

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

PLL2 soft start sequence and PLL2 soft-down sequence

handbook, full pagewidth

VHPLL2

continuous blanking off
PLL2 enabled
frequency detector enabled
HDRV/HFLB protection enabled

4.7 V

3.4 V

1.7 V

time

HDRV duty cycle begins to increase

1 V

VOUT1 and VOUT2 enabled

BDRV duty cycle begins to increase
HDRV duty cycle has reached nominal value

2.8 V

BDRV duty cycle has reached nominal value

duty cycle increases

MGM084

handbook, full pagewidth

VHPLL2

continuous blanking (pin 16 and 17) activated
PLL2 disabled
frequency detector disabled
HDRV/HFLB protection disabled

4.7 V

3.4 V

1.7 V

time

HDRV floating

1 V

VOUT1 and VOUT2 floating

BDRV duty cycle begins to decrease

(1)

2.8 V

BDRV floating
HDRV duty cycle begins to decrease

(1)

duty cycle decreases

MGM085

Fig.24 PLL2 soft start sequence and PLL2 soft-down sequence via the I

C-bus.

a. PLL2 soft start sequence, via the I

C-bus, if V

> 8.6 V.

b. PLL2 soft-down sequence, via the I

C-bus, if V

> 8.6 V.

(1) HDRV, BDRV, VOUT2 and VOUT1 are floating for V

< 8.6 V.

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

SOLDERING

Introduction to soldering through-hole mount
packages

This text gives a brief insight to wave, dip and manual
soldering. A more in-depth account of soldering ICs can be
found in our

"Data Handbook IC26; Integrated Circuit

Packages" (document order number 9398 652 90011).

Wave soldering is the preferred method for mounting of
through-hole mount IC packages on a printed-circuit
board.

Soldering by dipping or by solder wave

The maximum permissible temperature of the solder is
260

C; solder at this temperature must not be in contact

with the joints for more than 5 seconds.

The total contact time of successive solder waves must not
exceed 5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg(max)

). If the

printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300

C it may remain in contact for up to

10 seconds. If the bit temperature is between
300 and 400

C, contact may be up to 5 seconds.

Suitability of through-hole mount IC packages for dipping and wave soldering methods

Note

1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

PACKAGE

SOLDERING METHOD

DIPPING

WAVE

DBS, DIP, HDIP, SDIP, SIL

suitable

(1)

2000 Jan 31

Philips Semiconductors

Product specification

C-bus autosync deflection controller for

PC monitors

TDA4857PS

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

2000

Philips Semiconductors a worldwide company

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

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Tel. +61 2 9704 8141, Fax. +61 2 9704 8139

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
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Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102

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Colombia: see South America

Czech Republic: see Austria

Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905

Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920

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Hungary: see Austria

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254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966

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Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

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Tel. +353 1 7640 000, Fax. +353 1 7640 200

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TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

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Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811

Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341

Pakistan: see Singapore

Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001

Portugal: see Spain

Romania: see Italy

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382

Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 3341 299, Fax.+381 11 3342 553

Printed in The Netherlands

753504/01/pp

Date of release:

2000 Jan 31

Document order number:

9397 750 06652

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA4857