1997 Apr 08

Philips Semiconductors

Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

TDA5155

FEATURES

Designed for 10 dual-stripe MR-read/inductive write
heads

Current bias-current sense architecture

Single supply voltage (5.0 V

10%); a separate write

drivers supply pin can be biased from V

to 8 V +10%

MR elements connected to ground (GND)

Equal bias currents in the two MR stripes of each head

On-chip AC couplings eliminate MR head DC offset

3-wire serial interface for programming

Programmable voltage/current mode write data input

Programmable high frequency zero-pole gain boost

Programmable write driver compensation capacitance

Programmable MR bias currents and write currents

1-bit programmable read gain

Sleep, standby, active and test modes available

Measurement of head resistances in test mode

In test mode, one MR bias current may be forced to a
minimum current

Short write current rise and fall times with near
rail-to-rail voltage swing

Head unsafe pin for signalling of abnormal conditions
and behaviour

Low supply voltage write current inhibit (active or
inactive)

Support servo writing

Provide temperature monitor

Thermal asperity detection with programmable
threshold level

Requires only one external resistor.

APPLICATIONS

Hard Disk Drive (HDD).

GENERAL DESCRIPTION

The 5.0 V pre-amplifier for HDD applications has been
designed for five terminal, dual-stripe
Magneto-Resistive (MR)-read/inductive write heads.
The disks of the disk drive are connected to ground.
To avoid voltage breakthrough between the heads and the
disk, the MR elements of the heads are also connected to
ground. The symmetry of the dual-stripe head-amplifier
combination automatically distinguishes between the
differential signals such as signals and the common-mode
effects like interference. The latter are rejected by the
amplifier.

The device incorporates read amplifiers, write amplifiers, a
serial interface, digital-to-analog converters, reference and
control circuits which all operate on a single supply voltage
of 5 V

10%. The output drivers have a separate supply

voltage pin which can be connected to a higher supply
voltage of up to 8 V +10%. The complementary output
stages of the write amplifier allow writing with near
rail-to-rail peak voltages across the inductive write head.

The read amplifier has low input impedance. The DC offset
between the two stripes of the MR head is eliminated using
on-chip AC coupling. Fast settling features are used to
keep the transients short. As an option, the read amplifier
may be left biased during writing so as to reduce the
duration of these transients even further. Series
inductance in the leads between the amplifier and
MR heads influences the bandwidth which can be
compensated by using a programmable high frequency
gain boost (HF zero). HF noise and bandwidth can be
attenuated using a programmable high frequency gain
attenuator (HF pole).

On-chip digital-to-analog converters for MR bias currents
and write currents are programmed via a 3-wire serial
interface. Head selection, mode control, testing and servo
writing can also be programmed using the serial interface.
In sleep mode the CMOS serial interface is operational.
Fig.1 shows the block diagram of the device.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA5155X

naked die

1997 Apr 08

Philips Semiconductors

Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

TDA5155

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

supply voltage

4.5

5.0

5.5

CC(WD)

supply voltage for write drivers

8.0

8.8

v(dif)

differential voltage gain

from head inputs to RDx, RDy;
R

= 28

; I

= 10 mA

data bit d4 = 0

160

data bit d4 = 1

226

3dB

3 dB frequency bandwidth

upper bandwidth without gain
boost (4 nH lead inductance)

220

MHz

noise figure

= 28

; I

= 10 mA;

amb

= 25

C; f = 20 MHz

3.0

3.2

irn

input referred noise voltage

= 28

; I

= 10 mA;

amb

= 25

C; f = 20 MHz

0.9

1.0

nV/

CMRR

common mode rejection ratio
R

mismatch <5%

= 10 mA

f < 1 MHz

f < 100 MHz

PSRR

power supply rejection ratio
(input referred) R

mismatch <5%

= 10 mA

f < 1 MHz

f < 100 MHz

, t

write current rise/fall time
(10% to 90%)

= 150 nH; R

= 10

;

= 35 mA; f = 20 MHz

CC(WD)

= 8.0 V

1.8

CC(WD)

= 6.5 V

2.1

MR(PR)

programming MR bias current
range

ext

= 10 k

20.5

WR(b-p)

programming write current range
(base-to-peak)

ext

= 10 k

SCLK

serial interface clock rate

MHz

1997 Apr 08

Philips Semiconductors

Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

TDA5155

PINNING

SYMBOL PAD

DESCRIPTION

CC(WD)

supply voltage for the write drivers

GND1

ground connection 1

HUS

head unsafe output

WDIx(v)

write data input (differential, voltage
input)

WDIy(v)

write data input (differential, voltage
input)

WDIx(i)

write data input (differential, current
input)

WDIy(i)

write data input (differential, current
input)

R/W

read/write (read = active HIGH,
write = active LOW)

SEN

serial bus enable

SDATA

serial bus data

SCLK

serial bus clock

GND2

ground connection 2

RDx

read data output (differential x

RDy

read data output (differential x

GND3

ground connection 3

supply voltage

ext

10 k

external resistor

GND4

ground connection 4

0Wx

inductive write head connection for
head H0 (differential x

0Wy

inductive write head connection for
head H0 (differential x

0Rx

MR-read head connection for head
H0 (differential x

0GND

ground connection for head H0

0Ry

MR-read head connection for head
H0 (differential x

1Wx

inductive write head connection for
head H1 (differential x

1Wy

inductive write head connection for
head H1 (differential x

1Rx

MR-read head connection for head
H1 (differential x

1GND

ground connection for head H1

1Ry

MR-read head connection for head
H1 (differential x

2Wx

inductive write head connection for
head H2 (differential x

2Wy

inductive write head connection for
head H2 (differential x

2Rx

MR-read head connection for head
H2 (differential x

2GND

ground connection for head H2

2Ry

MR-read head connection for head
H2 (differential x

3Wx

inductive write head connection for
head H3 (differential x

3Wy

inductive write head connection for
head H3 (differential x

3Rx

MR-read head connection for head
H3 (differential x

3GND

ground connection for head H3

3Ry

MR-read head connection for head
H3 (differential x

4Wx

inductive write head connection for
head H4 (differential x

4Wy

inductive write head connection for
head H4 (differential x

4Rx

MR-read head connection for head
H4 (differential x

4GND

ground connection for head H4

4Ry

MR-read head connection for head
H4 (differential x

5Wx

inductive write head connection for
head H5 (differential x

5Wy

inductive write head connection for
head H5 (differential x

5Rx

MR-read head connection for head
H5 (differential x

5GND

ground connection for head H5

5Ry

MR-read head connection for head
H5 (differential x

6Wx

inductive write head connection for
head H6 (differential x

6Wy

inductive write head connection for
head H6 (differential x

6Rx

MR-read head connection for head
H6 (differential x

6GND

ground connection for head H6

6Ry

MR-read head connection for head
H6 (differential x

7Wx

inductive write head connection for
head H7 (differential x

SYMBOL PAD

DESCRIPTION

1997 Apr 08

Philips Semiconductors

Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

TDA5155

7Wy

inductive write head connection for
head H7 (differential x

7Rx

MR-read head connection for head
H7 (differential x

7GND

ground connection for head H7

7Ry

MR-read head connection for head
H7 (differential x

8Wx

inductive write head connection for
head H8 (differential x

8Wy

inductive write head connection for
head H8 (differential x

8Rx

MR-read head connection for head
H8 (differential x

SYMBOL PAD

DESCRIPTION

8GND

ground connection for head H8

8Ry

MR-read head connection for head
H8 (differential x

9Wx

inductive write head connection for
head H9 (differential x

9Wy

inductive write head connection for
head H9 (differential x

9Rx

MR-read head connection for head
H9 (differential x

9GND

ground connection for head H9

9Ry

MR-read head connection for head
H9 (differential x

SYMBOL PAD

DESCRIPTION

Fig.2 Pad arrangement.

handbook, full pagewidth

MGG981

VCC(WD)

WDIx(v)

WDIy(v)

WDIx(i)

WDIy(i)

SCLK

SDATA

SEN

VCC

Rext

GND3

GND4

GND2

R/W

3Wx

3Wy

3Rx

3GND

3Ry

4Wx

4Wy

4Rx

4GND

2Ry

2GND

2Rx

2Wy

2Wx

1Ry

1GND

1Rx

1Wy

1Wx

0Ry

0GND

0Rx

0Wy

0Wx

4Ry

5Wx

5Wy

5Rx

5GND

5Ry

6Wx

6Wy

6Rx

6Ry

7Wx

7Wy

7Rx

7GND

7Ry

8Wx

8Wy

8Rx

8GND

9Wx

9Wy

9Ry

9Rx

9GND

8Ry

6GND

RDx

RDy

GND1

HUS

TDA5155

1997 Apr 08

Philips Semiconductors

Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

TDA5155

FUNCTIONAL DESCRIPTION

8.1

Read mode

The read mode disables the write circuitry to save power
while reading. The read circuitry is disactivated for write,
sleep and standby modes. The read circuitry may also be
biased during write mode to shorten transients.
The selected head is connected to a multiplexed low-noise
read amplifier. The read amplifier has low-impedance
inputs nRx and nRy (n is the number of the head) and
low-impedance outputs RDx and RDy. The signal polarity
is non-inverting from x and y inputs to x and y outputs.

Ambient magnetic fields at the MR elements result in a
relative change in MR resistance:

This change produces a current variation:

where I

is the bias current in the MR element.

The current variation is amplified to form the read data
output signal voltage, which is available at RDx and RDy.
AC coupling between MR elements and amplifier stages
prevents the amplifier input stages from overloading by DC
voltages across the MR elements. A fast settling
procedure shortens DC settling transients.

An on-chip generated stable temperature reference
voltage (1.32 V), available at the R

ext

pin, is dropped

across an external resistor (10 k

) to form a global

reference current for the write and the MR bias currents.
The MR bias current DACs are programmed through the
serial interface according to the following formula:

(in mA), where d4-d0 are bits (either logic 0 or logic 1).
At power-up all bits are set to logic 0, which results in a
default MR current of 5 mA. The adjustable range of the
MR currents is 5 mA to 20.5 mA. The MR bias currents are
equal for the two stripes of each head. The gain amplifier
is 1-bit programmable. The amplifier gain can be set to its
nominal value or to the nominal value +3 dB.

--------------

0.5

10k

ext

--------------- 10

16d4

8d3

4d2

2d1

(

)

8.2

Write mode

To minimize power dissipation, the read circuitry may be
disabled in write mode. The write circuitry is disabled in
read, sleep and standby modes. In write mode, a
programmable current is forced through the selected
two-terminal inductive write head. The push-pull output
drivers yield near rail-to-rail voltage swings for fast current
polarity switching.

The write data input can be either voltage or current input
(see Chapter 12). In voltage mode, the differential write
data inputs WDIx(v) and WDIy(v) are PECL (Positive
Emitter Coupled Logic) compatible. The write data flip-flop
can either be used or passed-by. In the case that the write
data flip-flop is used, current polarity is toggled at the
falling edges of

Switching to write mode initializes the data flip-flop so that
the write current flows in the write head from x to y. In the
case that the write data flip-flop is not used, the signal
polarity is non-inverting from x and y inputs to
x and y outputs.

The write current magnitude is controlled through on-chip
DACs. The write current is defined as follows:

(in mA), where d4-d0 are bits (either logic 0 or logic 1).
The adjustable range of the write current is 20 mA to
51 mA. At power-up, the default values
d4 = d3 = d2 = d1 = d0 = logic 0 are initialized,
corresponding to I

= 20 mA. I

is the current provided

by the write drivers: the current in the write coil and in the
damping resistor together. The static current in the write
coil is

where R

is the resistance of the coil including leads and

is the damping resistor.

data

WDIx v

( )

WDIy v

( )

------------------------------------------------------

10k

ext

--------------- 20

16d4

8d3

4d2

2d1

(

)

-------

-----------------

1997 Apr 08

Philips Semiconductors

Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

TDA5155

8.3

Sleep mode

In sleep mode, the device is accessible via the serial
interface. All circuits are inactive, except the circuits of the
CMOS serial interface and the circuitry which forces the
data registers to their default values at power-up and
which fixes the DC level of outputs RDx and RDy (required
when operating with more than one amplifier). Typical
static current consumption is

A. Dynamic current

consumption during operation of the serial interface in
sleep mode due to external activity at the inputs to the
serial interface is not included. In all modes, including the
sleep mode, data registers can be programmed. Sleep is
the default mode at power-up. Switching to other modes
takes less than 0.1 ms.

8.4

Standby mode

The circuit can be put in standby mode using the serial
interface. In standby mode, the typical DC current
consumption is 330

A. Transients from standby mode to

active mode are two orders of magnitude shorter than from
sleep mode to active mode. This is important in the case
of cylinder mode operation with multiple amplifiers.
All amplifiers can operate from standby mode and all head
switch times can be kept just as short as in the case of
operation with a single amplifier. Head switch times are
summarized in the switching characteristics.

8.5

Active mode

Active mode is either read mode or write mode depending
on the status of the R/W pin.

8.6

Bi-directional serial interface

The serial interface is used for programming the device
and for reading of status information. 16 bits (8 bits for
data and 8 for address) are used to program the device.
The serial interface requires 3 pins: SDATA, SCLK and
SEN. These pins (and R/W as well) are CMOS inputs.
The logic input R/W has an internal 20 k

pull-up resistor

and the SEN logic input has an internal 20 k

pull-down

resistor. Thus, in case the SEN line is opened, no data will
be registered and in case the R/W line is opened, the
device will never be in write mode.

SDATA: serial data; bi-directional data interface. In all
circumstances, the LSB is transmitted first.

SCLK: serial clock; 25 MHz clock frequency.

SEN: serial enable; data transfer takes place when SEN is
HIGH. When SEN is LOW, data and clock signals are
prohibited from entering the circuit.

Three phases in the communication are distinguishable:
addressing, programming and reading. Each
communication sequence starts with an addressing
phase, followed by either a programming phase or a
reading phase.

8.6.1

DDRESSING

When SEN goes HIGH, bits are latched in at rising edges
of SCLK. The first eight bits a7 to a0 (starting with a0) are
shifted serially into an address register. If SEN goes LOW
before 16 bits have been received, the operation is
ignored. When more than 16 bits (address and data) are
latched in before SEN goes LOW, the first 8 bits are
interpreted as an address and the last 8 bits as data. SEN
should go HIGH at least 5 ns before the first rising edge of
SCLK. Data should be valid at least 5 ns before and after
a rising edge of SCLK. The first six bits a5 to a0 constitute
the register address. Bit a6 is unused. If bit a7 = logic 0,
a PROGRAMMING sequence starts. If bit a7 = logic 1,
READING data from the pre-amplifier can start.

8.6.2

ROGRAMMING DATA

If a7 = 0, the last eight bits d7 to d0 before SEN goes LOW
are shifted into an input register. When SEN goes LOW,
the communication sequence is ended and the data in the
input register is copied in parallel to the data register that
corresponds to the decoded address a0 to a5. SEN
should go LOW at least 5 ns after the last rising edge of
SCLK. See Fig.3 for the timing diagram of the
programming.

8.6.3

EADING DATA

Immediately after the IC detects that a7 = logic 1, data
from the data register (address a5 to a0) is copied in
parallel to the input register. Two wait clock cycles must
follow before the controller can start inputting data. At the
first falling edge of SCLK after the 2 wait rising edges of
SCLK, the LSB d0 is placed on SDATA line followed by d1
at the next falling edge of SCLK etc. If SEN goes LOW
before 8 address bits (a7 to a0) have been detected, the
communication is ignored. If SEN goes LOW before the
8 data bits have been sent out of the IC, the reading
sequence is immediately interrupted. See Fig.4 for the
timing diagram of the reading via the serial interface.

1997 Apr 08

Philips Semiconductors

Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

TDA5155

8.7

Operation of the serial interface

The serial interface programming is summarized in
Section 8.7.10.

8.7.1

ONFIGURATION

d0:

By default (d0 = logic 0), write data passes from the
write data input via the data flip-flop to the write driver.
The write driver toggles the current in the head at the
falling edges of:

When d0 = logic 1, the write data flip-flop is not used.
The signal polarity is non-inverting from the inputs WDIx
and WDIy to the outputs nWx and nWy.

d1:

By default (d1 = logic 0), the pre-amplifier senses PECL
write signals at WDIx(v) and WDIy(v). When
d1 = logic 1, the pre-amplifier senses input write
currents at WDIx(i) and WDIy(i).

d2:

By default (d2 = logic 0), the write current is inhibited
under low supply voltage conditions. The write current
inhibit is made inactive by programming d2 to logic 1.

d3:

By default (d3 = logic 0), in write mode low supply
voltage, open head, and other conditions are monitored
and flagged at HUS. If d3 = logic 1, HUS is LOW in write
mode and HIGH in read mode.

d4:

The amplifier read gain may be programmed in the
configuration register. By default (d4 = logic 0), the read
gain is typically 160 with R

= 28

. If d4 = logic 1, the

read amplifier gain is 3 dB higher (226 in this case).

d5:

In order to minimize the write-to-read recovery times,
the first stage of the read amplifier may be kept biased
during write mode. By default, (d5 = logic 0) the read
amplifier is powered down during write mode, and the
fast settling procedure is activated after write-to-read
switching. If d5 = logic 1 the read amplifier is kept biased
during write mode, and the fast settling procedure still
occurs if the head is changed or the MR current is
re-programmed.

data

WDIx v

( )

WDIy v

( )

------------------------------------------------------

data

WDIx i

( )

WDIy i

( )

----------------------------------------------

8.7.2

OWER CONTROL

By default, d1 = d0 = logic 0, the pre-amplifier powers up
in sleep mode. If d1 = logic 0, d0 = logic 1 or d1 = logic 1,
d0 = logic 0 the circuit goes in standby mode.
If d1 = d0 = logic 1, the circuit goes in active mode (read or
write mode depending on the R/W input).

8.7.3

EAD SELECT

Selection of a wrong head (H10-H15) causes an head
unsafe condition. HUS goes HIGH when in write mode a
wrong head is selected and when d3 in the configuration
register is LOW. When in read mode and a wrong head is
selected, head H0 is therefore selected and if d3 in the
configuration register is LOW, HUS goes LOW.

8.7.4

ERVO WRITE

The circuit is prepared for servo writing. However, the
device will not be guaranteed.

8.7.5

EST

d2 = d1 = d0 = logic 0. The circuit is not in test mode. This
is the default situation.

8.7.5.1

MR head test

d2 = logic 0, d1 = logic 0, d0 = logic 1. In read mode, the
voltages at Rx and Ry (at the top of the MR elements) of
the selected head are fed to outputs RDx and RDy.
By measuring the output voltages single ended at two
different I

currents, the MR resistance can be accurately

measured according to the following formula:

for the x-side.

Open head and head short-circuited-to-ground conditions
can therefore be detected.

d2 = logic 0, d1 = logic 1, d0 = logic 0. Same as before,
with the difference that I

MR2

is fixed to a minimum constant

value of 5 mA. Measuring in the same way as above with
I

MR1

> 5 mA, enables the detection of MR elements

shorted together.

8.7.5.2

Temperature monitor

d2 = logic 0, d1 = logic 1, d0 = logic 1. The temperature
monitor voltages are connected to RDx and RDy.
The output differential voltage depends on the
temperature according to: dV =

0.00364

T + 1.7;

0 < T < 140

C. The temperature may be measured with a

typical precision of 5

MRx

RDx1

RDx2

MRx1

MRx2

---------------------------------------

1997 Apr 08

Philips Semiconductors

Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

TDA5155

8.7.5.3

Thermal asperity detector

d2 = logic 1, d1 = x, d0 = (0,1). Unlike the above tests, the
thermal asperity detection does not use the RDx and RDy
outputs. Thus, the reader is fully operational. In case a
thermal asperity is detected, it is flagged at the HUS pin.

The threshold voltage for the thermal asperity detection is
2-bit programmable. These 2 bits consist of d0 (LSB) of
the test mode register (address = 0xxx0110), and d2 of the
compensation capacitor register (address = 0xxx0111).

d0 of test mode register;
d2 of the compensation capacitor register.

8.7.6

RITE AMPLIFIER PROGRAMMABLE CAPACITORS

By default (d2 = d1 = d0 = logic 0) the programmable
capacitors are zero. These capacitors are used to improve
the performance of the write amplifier according to the
write amplifier output load.

8.7.7

IGH FREQUENCY GAIN ATTENUATOR REGISTER

By default (d3 = d2 = d1 = d0 = logic 0) the high frequency
gain attenuator is not active. The gain attenuator provides
a pole which limits the bandwidth and reduces the high

210

560.d0

280.d2

(

) µ

frequency noise. The HF pole can be used in combination
with the HF zero in order to boost the HF gain locally and
yet limit the very high frequency noise enhancement.

8.7.8

IGH FREQUENCY GAIN BOOST REGISTER

By default (d3 = d2 = d1 = d0 = logic 0) the high frequency
gain boost is not active.
The gain boost provides a zero which allows to optimize
the bandwidth of the read amplifier and to correct for
attenuation caused by series inductances in the leads
between the MR heads and the read amplifier inputs.

8.7.9

ETTLE PULSE

By default (d2 = d1 = d0 = logic 0) the settle pulse has a
nominal duration of 3

s. Its value can be programmed

from 2.125

s to 3

s according to the following formula:

The settle pulse is used to shorten the transients during
switching.

4.d2

2.d1

1.d0

(

)

-------------------------------------------------------------------

8.7.10

DDRESS REGISTERS SUMMARY

ADDRESS REGISTERS

(1)

FUNCTION

A7 A6 A5 A4 A3 A2 A1 A0

configuration register:

d0 = 0: use data flip-flop; d0 = 1: by-pass data flip-flop

d1 = 0: WDI PECL; d1 = 1: current input

d2 = 0: write current inhibit active; d2 = 1: write current inhibit inactive

read mode: d3 = 0: HUS active; d3 = 1: HUS HIGH
write mode: d3 = 0: HUS active; d3 = 1: HUS LOW

d4 = 0: read gain nominal; d3 = 1: read gain +3 dB

d5 = 0: read amplifier OFF during write mode; d5 = 1: read amplifier ON
during write mode

power control register:

(d1,d0) = (0,0): sleep mode

(d1,d0) = (1,0) or (0,1): standby mode

(d1,d0) = (1,1): active mode (write or read)

head select register:

(d3,d2,d1,d0) = (0,0,0,0) to (1,0,0,1): H0 to H9
addressing H10 to H15 causes HUS to go HIGH if in write mode and H0 to be
selected if in read mode

1997 Apr 08

Philips Semiconductors

Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

TDA5155

Notes

1. Unused bits in the registers (indicated by X) are don't care. Default data, initialized at Power-up, is zero in all

registers. For V

<2.5 V, the register contents are not guaranteed.

2. V

programming uses both the test mode register and the compensation capacitor register. d0 in the formula above

is the LSB of the test mode register and d2 is the d2 data bit of the compensation capacitor register.

MR current DAC register:

write current DAC register:

servo write register:

(d0,d1) = (0,0): one head

(d0,d1) = (1,1): all heads

(d0,d1) = (1,0): odd numbered heads (H1, H3, H5, H7 and H9)

(d0,d1) = (0,1): even numbered heads (H0, H2, H4, H6 and H8)

test mode register:

(d2,d1,d0) = (0,0,0) = not in test mode

(d2,d1,d0) = (0,0,1) = read head test (I

MR1

= I

MR2

)

(d2,d1,d0) = (0,1,0) = read head test (I

MR2

= 5 mA fixed)

(d2,d1,d0) = (0,1,1) = temperature monitor

(d2,d1,d0) = (1,X,d0) = thermal asperity detection, see note 2
V

= (210 + 560.d0 + 280.d2)

compensation capacitor register:

equivalent differential capacitance = (4.d2 + 2.d1 + 1.d0)

2 pF

high frequency gain attenuator register

nominal pole frequency =

high frequency gain boost register

nominal zero frequency =

settle time register

settle time:

device ID register

ID = 8.d3 + 4.d2 + 2.d1 + 1.d0; d3 to d0 are preset to (0,0,1,1)

when a7 = 1, data from the register with address a3 to a0 is read out on
SDATA

ADDRESS REGISTERS

(1)

FUNCTION

A7 A6 A5 A4 A3 A2 A1 A0

0.5

10k

ext

--------------- 10

16.d4

8.d3

4.d2

2.d1

(

)

10k

ext

--------------- 20

16.d4

8.d3

4.d2

2.d1

(

)

800 MHz

8.d3

4.d2

2.d1

1.d0

---------------------------------------------------------------------

800 MHz

8.d3

4.d2

2.d1

1.d0

---------------------------------------------------------------------

4.d2

2.d1

1.d0

(

)

-------------------------------------------------------------------

1997 Apr 08

Philips Semiconductors

Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

TDA5155

8.8

Head unsafe

The HUS pin is an open collector output. Therefore when
the pin is not connected to an external pull-up resistor,
HUS is LOW. HUS pins can be connected together in case
of operation with more than one amplifier. It is used to
detect abnormal or unexpected operation.

Sleep mode: HUS is HIGH, to permit working with more
than one amplifier.

Standby mode: HUS is HIGH, to permit working with
more than one amplifier.

Read mode:

If in the configuration register d3 = 1, HUS is HIGH

If in the configuration register d3 = 0, HUS goes LOW
for:

Selection of a wrong head (H10 to H15)

(1)

ext

pin open, short-circuited to ground or to V

(read current too low or too high)

Low V

and V

CC(WD)

conditions. A low supply

voltage detector is placed close to the V

and

CC(WD)

pins.

Detection of low V

(main supply): a V

supply voltage

below 4.0 V

5% is flagged at the HUS pin. The voltage

detection range is then 4.2 to 3.8 V with an hysteresis of
110 mV

10%. Detection of low V

CC(WD)

(write drivers

supply): a fault will be flagged at the HUS pin if V

CC(WD)

drops 0.8 V

10% below V

. One must be aware that

such a detection is only aimed to warn for a catastrophic
situation. Indeed, V

CC(WD)

should never be below V

Test mode: HUS is HIGH except when the TAS detector
is ON. If a thermal asperity is detected, HUS goes LOW.

Servo write mode: HUS is LOW.

Write mode:

If in the configuration register d3 = 1, HUS is LOW

If in the configuration register d3 = 0, HUS goes HIGH
for:

Selection of a wrong head (H10 to H15)

(1)

ext

pin open, short-circuited to ground or to V

(write current too low or too high)

Write Data Input frequency too low (WDIx-WDIy)

Write head Wx, Wy open, Wx or Wy short-circuited to

ground

(2)

Write driver still left biased while not selected

Low V

and V

CC(WD)

conditions (write current inhibit

can be active or inactive).

The same detector is used for read and write mode.
The write current may be inhibited if d2 = 0 in the
configuration register.

The HUS line indicates an unsafe condition as long as the
fault is present, in read mode as well as in write mode.
It indicates again a safe condition only 0.5

s to 1

s after

the last fault has disappeared.

(1) Head numbers 0 to 9 are correct, 10 to 15 are signalled as

unsafe.

(2) Switching to write mode makes HUS LOW. After the transient

the HUS detection circuitry is activated. The target for the
head open detection time is 15 ns.

8.9

HUS survey

Notes

1. A-test mode = analog test mode.

2. In servo mode, the performance of the IC is not guaranteed.

HUS

DATA BIT D3

MODE

STATE

Sleep mode

HIGH

Standby mode

HIGH

Active mode

Read

Read mode

ACTIVE

HIGH

A-test mode

(1)

HIGH

TAS mode

ACTIVE

Write

Write mode

ACTIVE

LOW

A-test mode

(1)

HIGH

Servo mode

(2)

LOW

1997 Apr 08

Philips Semiconductors

Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

TDA5155

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

10 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

11 THERMAL CHARACTERISTICS

The thermal resistance depends on the flex used. The TDA5155X is shipped in naked dies form.

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

supply voltage

0.5

+6.0

CC(WD)

write driver supply voltage

0.5

+9.5

voltage on all pins except V

CC(WD)

, read inputs nRx, nRy

and write driver outputs nWx, nWy (n = 0 to 9)

0.5

+5.5

absolute maximum value

+ 0.5

voltage on write driver outputs nWx, nWy

0.5

+8.8

absolute maximum value

CC(WD)

+ 0.5

voltage on read inputs nRx, nRy

0.5

nGND

ground current (pins nGND)

0.1

stg

storage temperature

+150

junction temperature

150

1997 Apr 08

Philips Semiconductors

Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

TDA5155

12 RECOMMENDED OPERATION CONDITIONS

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP

MAX.

UNIT

supply voltage

note 1

4.5

5.5

CC(WD)

write driver supply voltage

note 2

8.8

HIGH level input voltage (CMOS)

3.5

LOW level input voltage (CMOS)

0.8

i(dif)(p-p)

differential input voltage
(peak-to-peak value)

note 3

0.4

0.7

1.5

IH(PECL)

HIGH level PECL input voltage

note 3

2.85

IL(PECL)

LOW level PECL input voltage

note 3

1.5

2.15

i(dif)(p-p)

differential input current
(peak-to-peak value)

note 4

0.4

0.8

1.0

IH(dif)

HIGH level differential input current

note 4

1.4

1.2

IL(dif)

LOW level differential input current

note 4

0.4

0.1

amb

ambient temperature

junction temperature

reading

110

writing (V

CC(WD)

= 8 V)

130

MR element resistance

)

mismatch

note 5

l(tot)

total lead inductance to the head

in each lead; note 6

l(tot)

total lead resistance to the head

in each lead; note 6

1.5

voltage on top of MR elements

note 7

0.5

sig(dif)(p-p)

differential MR head input voltage
(peak-to-peak value)

0.4

write head inductance

including lead; note 6

0.15

write head resistance

including lead; note 6

write head capacitance

including lead; note 6

tbf

ext

external reference resistor

ref

ext

-----------

1997 Apr 08

Philips Semiconductors

Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

TDA5155

Notes to the recommended operating conditions

1. A supply by-pass capacitor from V

to ground or a

low pass filter may be used to optimize the PSRR.

2. The supply voltage V

CC(WD)

must never be below V

in normal mode, and two diode 1.4 V above V

servo mode.

3. The given values should be interpreted in the way that

the single ended voltage could swing from
0.2 to 0.75 V, and that the common mode voltage
should be such that for any of the two states, the
V

IH(PECL)

is less than V

and V

IL(PECL)

is more than

1.5 V.
PECL voltage swing: a wider peak-to-peak voltage
swing can be used. In that case a current will flow
through the WDI inputs. This current is approximately

equal to

WDIx v

( )

WDIy v

( )

1.4

200

-------------------------------------------------------------------------

4. Same comments for the given values as for the

voltage input mode. The HIGH (respectively LOW)
level input current is defined such that it produces the
same effect at the output of the writer (Wx, Wy) as the
HIGH (resp. LOW) level input voltage.

5. The mismatch refers to the resistance of the two

stripes of the same head. This is defined as follows:

) = abs(R

MR1

MR2

6. These parameters depend on the head model.

The data given in the table are those used for testing.

7. The combination of maximum head resistance, lead

resistance and bias current is not permitted. To avoid
voltage breakthrough between heads and disk, the
voltage over the MR elements is limited by two diode
voltages.

1997 Apr 08

Philips Semiconductors

Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

TDA5155

13 CHARACTERISTICS

= 5.0 V; V

CC(WD)

= 8 V; V

GND

= 0 V; T

amb

= 25

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Read characteristics

MR current adjust range

ext

= 10 k

; 0.5 mA steps

20.5

tolerance (excluding R

ext

)

programmed at 10 mA

v(dif)

differential voltage gain;
note 1

from head inputs to RDx, RDy;
R

= 28

; I

= 10 mA;

f = 20 MHz

d4 = 0

160

d4 = 1

226

i(dif)

differential input resistance

= 10 mA

i(dif)

differential input
capacitance

THD

total harmonic distortion

lower signal gain pass-band
edge

3 dB

100

kHz

higher signal gain
pass-band edge

3 dB; note 2

without gain boost
(4 nH lead inductance)

220

MHz

with gain boost
(50 nH lead inductance)

170

MHz

noise figure

= 28

; I

= 10 mA;

amb

= 25

C; f = 20 MHz

3.0

3.2

irn

input referred noise voltage;
note 3

= 28

; I

= 10 mA;

amb

= 25

C; f = 20 MHz

0.9

1.0

nV/

F(L)

lower noise band edge
(+3 dB)

= 28

; I

= 10 mA;

amb

= 25

no lead inductance

400

kHz

F(H)

upper noise band edge
(+3 dB)

= 28

; I

= 10 mA;

amb

= 25

no lead inductance

220

MHz

channel separation; note 4

unselected head

PSRR

power supply rejection ratio;
note 5

f < 1 MHz; I

= 10 mA

f < 100 MHz; I

= 10 mA

CMRR

common mode rejection
ratio; note 5

from nRx-nRy to RDx-RDy R

mismatch < 5%
I

= 10 mA

f < 1 MHz

f < 100 MHz

1997 Apr 08

Philips Semiconductors

Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

TDA5155

rejection ratio of SCLK and
SDATA; note 6

from SCLK, SDATA inputs to the
RDx-RDy outputs; a 200 mV
(peak-to-peak) signal is applied
to SCLK or SDATA inputs at
25 MHz, and measurement is
performed at RDx-RDy

O(R)(dif)

output DC offset voltage in
read mode (differential
after DC settling)

DC voltage between RDx and
RDy

0.2

o(R)

output impedance in read
mode

single ended

o(max)(dif)

maximum differential
output current

o(cm)

common mode output
voltage in read mode

RDx, RDy

1.0

1.5

2.0

common mode DC supply
rejection ratio in read mode

o(n)(dif)

differential output
impedance in other modes
(write, standby, sleep)

Write characteristics

write current adjust range
(in the write drivers)

ext

= 10 k

; 1 mA steps

tolerance (excluding R

ext

)

programmed at 35 mA

s(max)(p-p)

maximum voltage swing
(peak-to-peak value)

CC(WD)

= 5 V

CC(WD)

= 8 V (differential)

o(dif)

differential output
resistance

200

o(dif)

differential output
capacitance

not including the head
capacitance

, t

write current rise/fall time
without flip-flop
(10% to 90%); note 7

= 150 nH; R

= 10

;

= 35 mA; f = 20 MHz

CC(WD)

= 8.0 V

1.8

CC(WD)

= 6.5 V

2.1

write current rise/fall time
asymmetry; note 8

percentage of t

or t

and

logic asymmetry)

propagation delay 50% of
(WDIx/WDIy) to 50% of
(Wx, Wy)

write head short-circuited, data
flip-flop by-passed

channel separation

not-selected head

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

o cm

(

)

----------------------

1997 Apr 08

Philips Semiconductors

Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

TDA5155

Switching characteristics

SCLK

serial interface clock rate

MHz

o(cm)

common mode DC output
voltage change from read to
write mode

= 10 mA; I

= 35 mA

200

rec(W-R)

write-to-read recovery time
(AC and DC settling);
note 9

from 50% of the rising edge of
R/W to steady state read-back
signal: AC and DC settling at
90% (without load at RDx, RDy)

read amplifier OFF: d5 = 0

4.5

read amplifier ON: d5 = 1

100

150

sw(R)

head switching (in read
mode), standby to read
active and MR current
change recovery time.
(AC and DC settling);
note 10

from falling edge of SEN to
steady state read-back signal
(without load at RDx, RDy)

4.5

off(R)

read amplifier off time

from falling edge of R/W to read
head inactive

st(W)

write settling times; note 11

from 50% of the falling edge of
R/W to 90% of the steady state
write current (in write mode)

off(W)

write amplifier off time

from rising edge of R/W to

(programmed)

= 35 mA)

sw(W)

head switching (in write
mode), and standby to write
head active

from falling edge of SEN to write
head active

sw(S)

switch time to and from
sleep mode

100

DC characteristics

CC(R)

read mode supply current

= 10 mA; note 12

CC(W)

write mode supply current

= 35 mA; note 13

from V

(5 V)

from V

CC(WD)

(5 to 8 V)

DD(STB)

standby mode supply
current

0.25

DD(S)

sleep mode supply current

static

0.02

ref

reference voltage for R

ext

1.32

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1997 Apr 08

Philips Semiconductors

Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

TDA5155

Notes to the characteristics

1. The differential voltage gain depends on the MR

resistance. It can be improved by programming the
d4 bit in the configuration register.

2. The gain boost implements a pole-zero combination:

The +3 dB gain boost corner frequency is

. The

3 dB gain

attenuation corner frequency is

, where d3, d2, d1 and d0

are to be programmed via the serial interface. In
practical use, the bandwidth is limited by the
inductance of the connection between the MR heads
and the pre-amplifier.

3. Noise calculation

a) Definitions: The amplifier has a low input

resistance. No lead resistance is taken into
account. The input referred noise voltage,
excluding the noise of the MR resistors, is defined

as:

where G

is the voltage gain, V

is the noise

voltage at the output of the amplifier, k is the
Boltzmann constant and T is the temperature in K.
The noise figure is defined as follows:

in 1 Hz

bandwidth. Note that R

includes all resistances

between Rx or Ry to ground.

b) Noise figure versus I

and R

: Table 1 shows

the variation of the noise figure with I

and R

c) Input referred noise voltage: The input referred

noise voltage calculation can be significantly
different (from 1.0 to 0.44 nV/

Hz for instance) by

taking an equivalent signal-to-noise ratio into
account when using two MR stripes (28

for each

stripe) or one MR stripe (42

). It assumes that the

signal coming from the head is larger for a
dual-stripe head than for a single-stripe head (50%
extra signal for a dual-stripe head).

4. The channel separation is defined by the ratio of the

gain response of the amplifier using the selected head
H(n) to the gain response of the amplifier using the
adjacent head H(n

1), head H(n) being selected.

800 MHz

8.d3

4.d2

2.d1

1.d0

---------------------------------------------------------------------

800 MHz

8.d3

4.d2

2.d1

1.d0

---------------------------------------------------------------------

irn

(

)

---------

4kT

MR1

MR2

(

)

---------

4kT

MR1

MR2

(

)

------------------------------------------------------------

log

The PSRR (in dB) is defined as input referred ratio:

, where G

is the differential input

to differential output gain, and G

is the power supply

to differential output gain.The CMRR (in dB) is defined

as input referred ratio:

, where

is the differential input to differential output gain and

is the common mode input to differential output

gain. Flex and board lay-out may affect these
parameters significantly.

6. This refers to the crosstalk from SCLK and SDATA

inputs via the read inputs to RDx and RDy. Two cases
can be distinguished:

a) When SEN is LOW, SCLK and SDATA are

prohibited reaching the device and crosstalk is low.

b) Programming via the serial interface is done with

SEN HIGH. Then crosstalk can occur. A careful
design of the board or flex-foil is required to avoid
crosstalk via this path.

7. The rise and fall times depend on the

write amplifier/write head combination. L

and R

represent the components on the evaluation board.
Parasitic capacitances also limit the performance.

8. The write current rise/fall time asymmetry is defined by

9. Write-to-read recovery time includes the write mode to

read mode switching using the R/W pin on the same
head (see Fig.5). The AC signal reaches its full
amplitude few tens of ns after appearing at the reader
RDx and RDy outputs.

10. In read mode, the head switching, standby to read

active switching and changing MR current include fast
current settling (see Fig.5). The AC signal reaches its
full amplitude few tenth of ns after appearing at the
reader RDx and RDy outputs.

11. Write settling time includes the read mode to write

mode switching using the R/W pin.

12. The typical supply current in read mode depends on

the bias current for the MR element.

13. The typical supply current in write mode also depends

on the write current.

PSRR

log

-------

CMRR

log

-----------

2 t

(

)

-----------------------

1997 Apr 08

Philips Semiconductors

Preliminary specification

Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads

TDA5155

14 DEFINITIONS

15 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors a worldwide company

SCA54

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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300

Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240

Hungary: see Austria

India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722

Indonesia: see Singapore

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381

Middle East: see Italy

Printed in The Netherlands

297027/20/01/pp24

Date of release: 1997 Apr 08

Document order number:

9397 750 01427

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA5155

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA5155

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA5155