1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

CONTENTS

FEATURES

APPLICATION

QUICK REFERENCE DATA

ORDERING INFORMATION

BLOCK DIAGRAM

PINNING

FUNCTIONAL DESCRIPTION

7.1

Functional description of the individual blocks

7.1.1

Quadrature demodulator and half Nyquist filter

7.1.2

Equalizer

7.1.3

Lock detector

7.1.4

Carrier recovery

7.1.5

Clock recovery

7.1.6

AGC

7.1.7

Offset control

7.1.8

Loop amplifiers

7.1.9

Output formatter

7.1.10

Boundary scan

7.1.11

C-bus interface

7.1.12

C-bus write parameters

7.1.13

C-bus read parameters

LIMITING VALUES

THERMAL CHARACTERISTICS

DEMODULATOR AND HALF NYQUIST
FILTER CHARACTERISTICS

LOCK DETECTOR CHARACTERISTICS

CARRIER RECOVERY CHARACTERISTICS

CLOCK RECOVERY CHARACTERISTICS

AGC CHARACTERISTICS

INTEGRATED LOOP AMPLIFIERS
CHARACTERISTICS

CHARACTERISTICS OF DIGITAL INPUTS
AND OUTPUTS

PACKAGE OUTLINE

SOLDERING

18.1

Introduction

18.2

Reflow soldering

18.3

Wave soldering

18.4

Repairing soldered joints

DEFINITIONS

LIFE SUPPORT APPLICATIONS

PURCHASE OF PHILIPS I

C COMPONENTS

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

FEATURES

Different modulation schemes: 4, 16, 32,
64 and 256-QAM

Digital demodulator and square root raised cosine
Nyquist filter with roll-off of 15% or 20%

High performance adaptive equalizer (no training
sequence needed)

Digital detectors for generation of required control
voltages for carrier recovery, clock recovery and AGC

Digital-to-analog converters and operational amplifiers
allowing high flexibility for selection of the (PLL) loop
time constants

High maximum symbol rate (r

) of 7 Msymbols/s

Input format: Straight binary or 2's complement
(up to 9 bits, TTL compatible)

Output format: 8-bit wide bus (CMOS compatible)

C-bus interface to initialize and monitor the

demodulator. When no I

C-bus usage; 64-QAM,

20% roll-off factor in default mode

5 V peripheral and analog supply voltage

3.3 V core supply voltage

Boundary scan test.

APPLICATION

Demodulation for digital cable TV and cable modem.

QUICK REFERENCE DATA

Notes

1. The supply currents are specified for the maximum symbol frequency.

2. The implementation loss (IL) of the demodulator is defined as the distance between the measured and theoretical

BER curve as function of signal-to-noise ratio at a BER = 10

for a back-to-back measurement at the IF frequency.

This performance depends on the chosen loop parameters (see

Application notes).

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

DDD(core)

core supply voltage

3.00

3.30

3.60

DDD

digital peripheral supply voltage

4.75

5.00

5.25

DDA

analog supply voltage

4.75

5.00

5.25

DDD(core)

core supply current

DDD(core)

= 3.3 V; note 1

100

DDD

digital peripheral supply current

DDD

= 5 V; note 1

DDA

analog supply current

DDA

= 5 V; note 1

symbol rate

Msym/s

implementation loss

note 2

0.7

Nyquist roll-off (programmable)

15 or 20

SNR

lock

signal-to-noise ratio for locking a
64-QAM constellation

signal-to-noise ratio for locking a
256-QAM constellation

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA8046H

QFP64

plastic quad flat package; 64 leads (lead length 1.95 mm);
body 14

2.8 mm

SOT319-2

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

BLOCK DIAGRAM

dbook, full pagewidth

1 to 5,

8 to 11

DIN0

DIN8

SQUARE ROOT

RAISED COSINE

DEMODULATOR

INPUT

REPRESEN-

TATION

SQUARE ROOT

RAISED COSINE

COARSE

AGC

DAC

I ref1

ref

CLOCK

RECOVERY

DAC

I ref2

ref

NCO

CONTROL

DIGITAL

PHASE

ROTATOR

OFFSET

CONTROL

BOUNDARY

SCAN TEST

FINE AGC

EQUALIZER

FINE AGC

CONTROL

OUTPUT

FORMATTER

20 to 23

27 to 30

DO7 to

DO0

CLKSDV

CARREC

CARTC

CLKREC

CLKTC

AGC

DDA

SSA

AGCTC

I BIAS

CARRIER

RECOVERY

DAC

I ref3

ref

BIAS

GENERATOR

ref

I ref1

I ref2

I ref3

ANALOG SECTION

CLOCK GENERATOR

r s

to DACs

internal clock for

digital processing

CLKADC

CLK

SCL

TMS

PRESET

CLKT

TDO

TDI

TRST

TCK

SDA

C-BUS

CONTROL

CLKOUT

6, 13, 16,

25, 33, 38,

45, 51, 63

TDA8046

MGG198

DDD1 to 9

7, 12, 14, 17,

24, 26, 31, 34,

46, 50, 61, 64

SSD1 to 12

TEST1

TEST2

TEST3

Fig.1 Block diagram.

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

PINNING

SYMBOL

PIN

I/O

DESCRIPTION

DIN0

digital input bit 0 (LSB)

DIN1

digital input bit 1

DIN2

digital input bit 2

DIN3

digital input bit 3

DIN4

digital input bit 4

DDD1

supply

digital peripheral supply voltage 1 (+5 V)

SSD1

supply

digital ground 1; for input peripheral and core

DIN5

digital input bit 5

DIN6

digital input bit 6

DIN7

digital input bit 7

DIN8

digital input bit 8 (MSB)

SSD2

supply

digital ground 2; for core and clock buffers

DDD2

supply

digital supply voltage 2; for core and clock buffers (+3.3 V)

SSD3

supply

digital peripheral ground 3

CLKADC

clock output to ADC (4

)

DDD3

supply

digital peripheral supply voltage 3 (+5 V)

SSD4

supply

digital ground 4; for core

CLKSDV

clock symbol data valid output

CLKT

for test purpose only

DO7

parallel data output (bit 7)

DO6

parallel data output (bit 6)

DO5

parallel data output (bit 5)

DO4

parallel data output (bit 4)

SSD5

supply

digital peripheral ground 5

DDD4

supply

digital peripheral supply voltage 4 (+5 V)

SSD6

supply

digital ground 6; for core

DO3

parallel data output (bit 3)

DO2

parallel data output (bit 2)

DO1

parallel data output (bit 1)

DO0

parallel data output (bit 0)

SSD7

supply

digital peripheral ground 7

CLKOUT

output formatter clock output

DDD5

supply

digital peripheral supply voltage 5 (+5 V)

SSD8

supply

digital peripheral ground 8

SCL

serial clock input (I

C-bus)

SDA

I/O

serial data input/output (I

C-bus)

hardware address input (I

C-bus)

DDD6

supply

digital peripheral supply voltage 6 (+5 V)

TEST3

test input 3 (normally connected to ground)

TEST2

test input 2 (normally connected to ground)

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

TEST1

test input 1 input (normally connected to ground)

TRST

optional asynchronous reset input

TCK

dedicated test clock input

TMS

input control signal

DDD7

supply

digital supply voltage 7; for core (+3.3 V)

SSD9

supply

digital ground 9; for core

TDO

serial test data output

TDI

serial test data input

PRESET

set device into default mode input

SSD10

supply

digital ground 10; for the digital section of the analog block

DDD8

supply

digital supply voltage 8; for the digital section of the analog block (+5 V)

BIAS

input bias current for DACs

AGCTC

inverted operational amplifier input voltage for loop filtering

AGC

analog output voltage for AGC

CARTC

inverted operational amplifier input voltage for carrier recovery loop
filtering

CARREC

analog output voltage for carrier recovery

CLKTC

inverted operational amplifier input voltage for clock recovery loop
filtering

CLKREC

analog output voltage for clock recovery

SSA

supply

analog ground

DDA

supply

analog supply voltage (+5 V)

SSD11

supply

digital ground 11; for clock

CLK

clock input (4

)

DDD9

supply

digital supply voltage 9; for clock

SSD12

supply

digital peripheral ground 12

SYMBOL

PIN

I/O

DESCRIPTION

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

FUNCTIONAL DESCRIPTION

Figure 3 shows the application of the TDA8046
multi-mode QAM demodulator. The frequency of the IF
signal (IF

QAM

) is down converted to a frequency that

equals the symbol rate (r

) by a mixer which is driven from

a local oscillator with a frequency of f

CAR

= f

+ r

After low pass filtering this baseband signal is applied to an
external 8 or 9-bit ADC.

For 256-QAM, a 9-bit ADC is preferred, for the other
modes an 8-bit ADC is sufficient.

The multi-mode QAM demodulator has digital detectors for
AGC, carrier recovery and clock recovery. The on-chip
DACs translate the detector values to analog control

currents which are then integrated by a loop filter.
To perform this loop filtering, an operational amplifier is
integrated after each DAC.

The carrier recovery consists of a two-loop system.
The outer loop is shown in Fig.3, and controls both phase
and frequency at a low speed. The inner loop controls the
carrier phase at a high speed (wide loop bandwidth).

The AGC also consists of two loops; the outer loop is the
coarse AGC and one inner loop is the fine AGC.

The recovered symbols are converted into bits according
to a demapping scheme and represented at the output in
an 8-bit parallel output format. The QAM demodulator can
be initialized and monitored by the I

C-bus interface.

Fig.3 Application with multi-mode QAM demodulator.

handbook, full pagewidth

MGG167

LPF

ADC

fCAR = fIF

clock recovery

carrier recovery

AGC

DO7 to DO0
CLKOUT

CLKSDV

8 or 9 bits

IFQAM

SAW

TUNER

signal

fclk

TDA8046

C-BUS

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

7.1

Functional description of the individual blocks

The functional block diagram of the multi-mode QAM
demodulator is illustrated in Fig.1. This section describes
the individual blocks in the demodulator. After adaptation
for the used input format (2's complement or binary), the
input signal is demodulated in the I and Q baseband
signals which are applied to the inputs of the half-Nyquist
filter (equals square root raised cosine). To avoid
overloading of the ADC, an AGC detector is placed after
the adaptation for the input format. The control value for
the clock recovery is generated after half Nyquist filtering.
The echoes created in the cable network are reduced
significantly in the equalizer.

The equalizer produces a `clean' constellation diagram
from which the information for the carrier recovery is
derived. This constellation is also applied to the output
formatter which demaps the transmitted symbols in
corresponding bits. The carrier recovery and lock
detection functions are based on the equalizer output.
The output of the equalizer is applied to an output
formatter, which translates the symbol bits to a FEC input
format. The digital outputs of the clock recovery, AGC, and
carrier recovery section are converted into currents which
are integrated by the loop filters.
To make these loop filters active, operational amplifiers
are integrated on the chip.

The TDA8046 can handle five different digital modulation
schemes; 4, 16, 32, 64 and 256-QAM. These schemes
are selectable via the I

C-bus interface.

7.1.1

UADRATURE DEMODULATOR AND HALF

YQUIST

FILTER

Quadrature demodulation is accomplished after selection
of the appropriate input format via the I

C-bus.

The in-phase and quadrature components are both
applied to a half Nyquist filter. In default mode, this filter
gives a 20% roll-off half Nyquist shaping. The basic
schematic of the quadrature demodulator followed by the
half Nyquist filter is shown in Fig.4. The signs of the
multiplication factors in the Q-branch can be inverted
(I

C-bus bit INVD).

When using an 8-bit ADC the LSB of the 9-bit input word
should be connected to the positive supply (V

DDD

This ensures a symmetrical 2's complement
representation which can be multiplied by

1 in a correct

(2's complement) way. The overall transfer function of the
square root raised cosine filters is shown in Figs 5 and 6.

For characteristics see Chapter 10.

Fig.4 Schematic diagram of the quadrature demodulator and half Nyquist filter.

handbook, full pagewidth

HALF NYQUIST

FILTER

HALF NYQUIST

FILTER

1, 0,

1, 0

1, 0,

DIN8

DIN0

BINARY OR

TWO's

COMPLEMENT

C-BUS

MGG168

C-BUS

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

7.1.2

QUALIZER

This function is realized with a T spaced 12 or 14 taps
(selected via the I

C-bus) adaptive filter with a feedback

part. The equaliser is based on a Decision Feedback
Equalizer (DFE) structure with Least Mean Square (LMS)
coefficient updating algorithm. No training sequence is
required. The block schematic of the total equalizer is
shown in Fig.8. The main tap of the equalizer is adjustable
for fine AGC function (6 dB AGC range). The settings of
the equalizer taps can be read via the I

C-bus. If the

equalizer diverges, an alarm bit is set (I

C-bus bit ALEQ)

and an automatic reset of the taps can be performed
(I

C-bus bit EAR).

To improve acquisition time, the convergence steps of the
FFE/DFE parts of the equalizer are programmable via the
I

C-bus. When the system locks, the steps are

automatically modified for optimum performances.

Besides reading the equalizer tap values, the main tap of
the equalizer can also be programmed. After setting the
main tap, the other coefficients can be set to zero.
The equalizer settings can also be frozen via the I

C-bus.

The equalizer has been proven to work correctly under bad
channel conditions as indicated in Table 1. It is guaranteed
that all loops (including equalizer) converge at a SNR of
21 dB for a 64-QAM modulation format and 27 dB for a
256-QAM modulation format.

Table 1

Channel echo profile

Figure 7 represents the QAM spectrum seen by the
equalizer. It corresponds (in the frequency domain) to the
multiplication of a full nyquist spectrum by the impulse
response of the channel specified in Table 1.

DELAY

AMPLITUDE

PHASE

sym

0.08

130

sym

0.20

sym

0.05

310

sym

0.10

200

sym

0.03

200

Fig.7 QAM spectrum with echo profile as seen by the equalizer.

handbook, full pagewidth

0.5

relative frequency

relative

gain
(dB)

0.375

0.125

0.25

MGD636

(

)

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

Fig.8 DFE equalizer structure.

handbook, full pagewidth

MGG170

FEED

FORWARD

EQUALIZER

TAPS CALCULATION

DECISION

FEEDBACK

EQUALIZER

TAPS CALCULATION

input

output

decision

7.1.3

OCK DETECTOR

The lock detector indicates whether all algorithms in the
demodulator are converged or not. For a symbol error rate
(at the input of the demodulator) smaller than 2

, the

detector will give the indication `LOCK' (I

C-bus bit

LK = 1). For larger symbol error rates, the detector will
generate the `UNLOCK' signal (I

C-bus bit LK = 0).

It should ne noted that this `UNLOCK' signal is generated
before any other part of the demodulator loses lock.
The lock detector is part of the carrier recovery loop, see
Fig.9. The Lock Detector Threshold (LDT) can be changed
with the help of the I

C-bus. The estimation algorithm used

in the lock detector also provides information about the
SER ratio which can be read out via the I

C-bus interface.

For characteristics see Chapter 11.

7.1.4

ARRIER RECOVERY

The carrier recovery detector consists of a
Phase-Frequency Detector (PFD) and Phase Detector
(PD). Depending on the mode of operation, the carrier
recovery is switched either between the phase frequency
(no lock) or the phase detector (lock). The carrier recovery
consists of the following two loops:

1. The outer loop; this loop controls the phase and

frequency of the incoming QAM signal at the IF
frequency in such a way that the constellation is
optimally positioned for detection.

2. The inner loop; the bandwidth of this loop can be large

and can therefore reduce the influence of large
bandwidth phase noise.

A fully digital carrier recovery function is also possible and
can be selected via the I

C-bus. Should this configuration

be used, then the external components of the loop filter will
not have to be implemented.

Four different maximum DAC output currents can be
selected via the I

C-bus. The output currents of the DAC

are defined in such a way that a VCO with a behaviour as
shown in Fig.9 can be connected directly to the output of
the integrated operational amplifier. Should the VCO slope
be negative then the sign of the current can be inverted by
the I

C-bus. Figure 10 defines the DAC output currents.

For characteristics see Chapter 12.

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

7.1.5

LOCK RECOVERY

The clock recovery function uses the unequalized I and Q
signals, i.e. the half Nyquist filter outputs (see Fig.4).
The clock recovery section generates a control value each
symbol period. As this algorithm is based on the energy
maximization, both main and mid symbols are required at
the input. Consequently, the input data rate is twice the
symbol rate. The schematic diagram of this detector is
illustrated in Fig.11.

The clock generator generates the required internal clocks
from the VCXO clock signal at 4

. The input stage

amplifier of this generator enables the designer to supply
a low amplitude oscillator signal to the TDA8046. The DAC
output current range (I

CLK

) can be varied via the I

C-bus.

The sign of the output current can also be inverted to
adjust for the correct sign of the VCXO slope.

For characteristics see Chapter 13.

Fig.11 Schematic diagram of the clock recovery.

handbook, full pagewidth

DAC

rs Iref3

ICLK

Vref

external

CLOCK

RECOVERY

DETECTOR

VCXO

from

VCXO

4rs

2rs

MGG172

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

7.1.6

AGC

The AGC estimates the mean power based on the digital
input signal and relates this to a peak value for a given
constellation. To avoid overloading of the ADC, this
estimation of the peak signals is used to control the AGC
loop. The implemented AGC covers a range of

20 dB in

gain variance. A schematic diagram of the AGC is
illustrated in Fig.13.

If the SAW filter does not have sufficient adjacent channel
attenuation, the AGC threshold can be varied to avoid
clipping of the ADC. To do this, the threshold is made
programmable via the I

C-bus (byte ATH). Table 2 shows

that for each mode, a new ATH value (on address 08)
must be set with the help of the I

C-bus.

The I

C-bus data on address 08 is a factor 16 smaller than

the used AGC threshold ATH.

The DAC output current range can be varied via the
I

C-bus interface (bits AGCA and AGCB) and the sign of

the current can be inverted (bit AGCI). The definition of the
DAC currents and the expected frequency behaviour of
the AGC is illustrated in Fig.14.

For characteristics see Chapter 14.

Table 2

AGC threshold values

MODE

ATH (AGC THRESHOLD)

C-BUS DATA FOR ADDRESS 08

256, 64, 16 and 4-QAM

2040

32-QAM

1442

Fig.13 AGC schematic diagram.

handbook, full pagewidth

DAC

IBIAS

Iref2

IAGC

Vref

external

AGC

DETECTOR

BIAS

GENERATOR

to AGC

amplifier

MGG173

ADC

C-BUS

DIN8

DIN0

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

7.1.7

FFSET CONTROL

To compensate offsets in the I and Q branch, due to
spurious signals at the symbol frequency at the ADC input,
an offset compensation loop is included. This loop forces
the constellation to be symmetrically distributed over its
four quadrants. This function can be switched off by
I

C-bus bit OFFS.

7.1.8

OOP AMPLIFIERS

Analog switches are integrated to discharge the loop filter
capacitors or for test purposes on application boards (a
reference voltage equal to the half of the positive supply
voltage V

DDA

is available at the output of the amplifier

when the switches are closed). The I

C-bus bit ANAS

controls the three switches simultaneously. A schematic
diagram of the loop amplifier and analog switch is
illustrated in Fig.15.

For characteristics see Chapter 15.

Fig.15 Loop amplifier and analog switch.

handbook, halfpage

DAC

Vref

external

MGG174

C-BUS

7.1.9

UTPUT FORMATTER

The output formatter transforms the detected symbols into
bits in accordance with the selected mapping. The
TDA8046 has four possible mapping formats which can be
selected via the I

C-bus interface. The demapping

procedure and the corresponding bits are defined in
Fig.16. After demapping the bits are allocated to the
output. This output allocation corresponds to one of the
selected demapping schemes.

By using the I

C-bus, it is possible to obtain the following

output formats:

8 bits parallel

semi-serial

I and Q 8 bits multiplexed.

The implemented demapping formats and output bit
allocation are illustrated in Figs 17 to 30.

7.1.10

OUNDARY SCAN

The TDA8046H offers the possibility of boundary scan
test. The IEEE Standard Test Access Port and Boundary
Scan Architecture allows board manufacturers to test
board interconnections by using the boundary scan
functions.

Complete information on boundary scan test is available in
"Application note AN96048".

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

Fig.16 Schematic diagram of the output formatter.

handbook, full pagewidth

MGG175

DO1 to DO0

CLKSCV

CLKOUT

DO7 to DO0

CLKSCV

DO7 to DO0

CLKSCV

CLKOUT

DEMAPPING

SCHEMES

1 to 4

MUX

PARALLEL

AND

SEMI-SERIAL

C-BUS

7.1.10.1

Demapping scheme 1; differential decoding

Fig.17 Demapping scheme 1; bit allocation: 256-QAM.

Bit allocation for 256-QAM: b5, b4, b3, b2, b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).

handbook, full pagewidth

MGG193

010110

011110

001110

000110

010111

011111

001111

000111

010101

011101

001101

000101

010100

011100

001100

000100

100110

101110

111110

110110

100111

101111

111111

110111

100101

101101

111101

110101

100100

101100

111100

110100

A quadrant

b5 b4 b3 b2 b1 b0

010000

011000

001000

000000

010001

011001

001001

000001

010011

011011

001011

000011

010010

011010

001010

000010

100000

101000

111000

110000

100001

101001

111001

110001

100011

101011

111011

110011

100010

101010

111010

110010

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

Bit allocation for 4-QAM: b5 = b4 = b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).

Bit allocation for 64-QAM: b5, b4, b3 and b2; b0 = b1 = 0; b7 and b6 differentially decoded (see Table 3).

Fig.18 Demapping scheme 1; bit allocation: 4-QAM and 64-QAM.

handbook, full pagewidth

MGG183

0 0 0 0

0 0 0 1

0 0 1 1

0 0 1 0

0 1 0 0

0 1 0 1

0 1 1 1

0 1 1 0

1 1 0 0

1 1 0 1

1 1 1 1

1 1 1 0

1 0 0 0

1 0 0 1

1 0 1 1

1 0 1 0

1 0 0 0

1 1 0 0

0 1 0 0

0 0 0 0

1 0 0 1

1 1 0 1

0 1 0 1

0 0 0 1

1 0 1 1

1 1 1 1

0 1 1 1

0 0 1 1

1 0 1 0

1 1 1 0

0 1 1 0

0 0 1 0

A quadrant

b5 b4 b3 b2

B quadrant

D quadrant

C quadrant

0 0 1 0

0 1 1 0

1 1 1 0

1 0 1 0

0 0 1 1

0 1 1 1

1 1 1 1

1 0 1 1

0 0 0 1

0 1 0 1

1 1 0 1

1 0 0 1

0 0 0 0

0 1 0 0

1 1 0 0

1 0 0 0

1 0 1 0

1 0 1 1

1 0 0 1

1 0 0 0

1 1 1 0

1 1 1 1

1 1 0 1

1 1 0 0

0 1 1 0

0 1 1 1

0 1 0 1

0 1 0 0

0 0 1 0

0 0 1 1

0 0 0 1

0 0 0 0

Fig.19 Demapping scheme 1; bit allocation: 16-QAM and 32-QAM.

Bit allocation for 16-QAM: b5 and b4; b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).

Bit allocation for 32-QAM: not implemented.

handbook, full pagewidth

MGG184

0 0

0 1

1 0

1 1

1 0

0 0

1 1

0 1

A quadrant

b5 b4

B quadrant

D quadrant

C quadrant

0 1

1 1

0 0

1 0

1 1

1 0

0 1

0 0

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

Fig.24 Demapping scheme 3; bit allocation: 4-QAM and 64-QAM.

Bit allocation for 4-QAM: b5 = b4 = b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).

Bit allocation for 64-QAM: b5, b4, b3 and b2; b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).

handbook, full pagewidth

MGG187

0 0 0 0

0 0 1 0

1 0 1 0

1 0 0 0

0 0 0 1

0 0 1 1

1 0 1 1

1 0 0 1

0 1 0 1

0 1 1 1

1 1 1 1

1 1 0 1

0 1 0 0

0 1 1 0

1 1 1 0

1 1 0 0

0 1 0 0

0 1 0 1

0 0 0 1

0 0 0 0

0 1 1 0

0 1 1 1

0 0 1 1

0 0 1 0

1 1 1 0

1 1 1 1

1 0 1 1

1 0 1 0

1 1 0 0

1 1 0 1

1 0 0 1

1 0 0 0

A quadrant

b5 b4 b3 b2

B quadrant

D quadrant

C quadrant

1 0 0 0

1 0 0 1

1 1 0 1

1 1 0 0

1 0 1 0

1 0 1 1

1 1 1 1

1 1 1 0

0 0 1 0

0 0 1 1

0 1 1 1

0 1 1 0

0 0 0 0

0 0 0 1

0 1 0 1

0 1 0 0

1 1 0 0

1 1 1 0

0 1 1 0

0 1 0 0

1 1 0 1

1 1 1 1

0 1 1 1

0 1 0 1

1 0 0 1

1 0 1 1

0 0 1 1

0 0 0 1

1 0 0 0

1 0 1 0

0 0 1 0

0 0 0 0

Fig.25 Demapping scheme 3; bit allocation: 16-QAM.

Bit allocation for 16-QAM: b5 and b4; b3 = b2 = b1 = b0 = 0; b7 and b6 differentially decoded (see Table 3).

handbook, full pagewidth

MGG188

0 0

1 0

0 1

1 1

0 1

0 0

1 1

1 0

A quadrant

b5 b4

B quadrant

D quadrant

C quadrant

1 0

1 1

0 0

0 1

1 1

0 1

1 0

0 0

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

Table 3

Definition of two MSB's in modulation schemes 1 and 3

Tables 4 and 5 give the output format of the data for semi-serial mode operations.

QUADRANT OF

CURRENTLY

RECEIVED SYMBOL

QUADRANT OF

PREVIOUSLY

RECEIVED SYMBOL

PHASE

CHANGE

(DEGREES)

CURRENT OUTPUT BITS

SCHEME 1

SCHEME 3

270

180

270

180

270

180

Fig.30 Demapping scheme 4; bit allocation: 4-QAM and 16-QAM.

a. Bit allocation for 4-QAM: b7 and b6; b5 = b4 = b3 = b2 = b1 = b0 = 0.

b. Bit allocation for 16-QAM: b7, b6, b5 and b4; b3 = b2 = b1 = b0 = 0.

handbook, full pagewidth

MGG192

1 0

1 1

0 0

0 1

b4 b5

0 1

0 0

1 1

1 0

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

Table 4

Semi-serial format 256, 64 and 32-QAM; see note 1

Note

1. The semi-serial format is only valid for demapping schemes 1, 3 and 4.

Table 5

Semi-serial format 16-QAM and 4-QAM; see note 1

Note

1. The semi-serial format is only valid for demapping schemes 1, 3 and 4.

SLOT

256-QAM

64-QAM

32-QAM

DO1

DO0

CLKSDV

DO1

DO0

CLKSDV

DO1

DO0

CLKSDV

n-1

(7)

n-1

(6)

n-1

(5)

n-1

(4)

n-1

(4)

n-1

(3)

n-1

(5)

n-1

(4)

n-1

(3)

n-1

(2)

n-1

(2)

n-1

(1)

n-1

(3)

n-1

(2)

n-1

(1)

n-1

(0)

n-1

(1)

n-1

(0)

(7)

(6)

(5)

(4)

n-1

(0)

(4)

(5)

(4)

(3)

(2)

(3)

(2)

(3)

(2)

(1)

(0)

(1)

(0)

(1)

(0)

SLOT

16-QAM

4-QAM

DO1

DO0

CLKSDV

DO1

DO0

CLKSDV

n-1

(3)

n-1

(2)

n-1

(1)

n-1

(0)

n-1

(1)

n-1

(0)

(3)

(2)

(1)

(0)

(1)

(0)

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

7.1.11

C-

BUS INTERFACE

The TDA8046 is controlled by an I

C-bus. For programming, there is one module address (7 bits) and the R/W bit for

selecting READ or WRITE mode. It should be noted that the TDA8046 starts up in accordance with to the settings defined
in Tables 7, 8 and 9.

Table 6

Slave address

Table 7

WRITE (R/W = 0)

R/W

FUNCTION

ADD

DAC current
inversion/general

AGCI

CLKI

CARI

OUTE

DEM

NYQ

DPHR

RST

Demodulator

INP

RLF

OUTB

OUTA

INVD

CONC

CONB

CONA

DAC/OFFS/switch

ANAS

OFFS

AGCB

AGCA

CLKB

CLKA

CARB

CARA

Digital test/output
formatter

OUTF

TSEL2

TSEL1

TSEL0

Digital loop filter
B.W.

DCA7

DCA6

DCA5

DCA4

DCA3

DCA2

DCA1

DCA0

Digital loop filter
B.W.

FSOL

DCB2

DCB1

DCB0

Lock detector
threshold

LDT7

LDT6

LDT5

LDT4

LDT3

LDT2

LDT1

LDT0

Lock detector
window size

WS1

WS0

AGC detector
threshold

ATH7

ATH6

ATH5

ATH4

ATH3

ATH2

ATH1

ATH0

Equalizer mode

EAR

FFEL

EDFE

EFFE

EFC

PRESET

Equalizer tap FFEI

FFEI07

FFEI06

FFEI05

FFEI04

FFEI03

FFEI02

FFEI01

FFEI00

Equalizer steps

FSTP2

FSTP1

FSTP0

DSTP2

DSTP1

DSTP0

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

Table 8

Default settings after reset

Table 9

READ (R/W = 1)

FUNCTION

ADD

DAC current inversion/
general

Demodulator

DAC/OFFS/switch

Digital test/output
formatter

Digital loop filter B.W.

Lock detector
threshold

Lock detector window
size

AGC detector
threshold

Equalizer mode

Equalizer tap FFEI

Equalizer steps

FUNCTION

ADD

CARREC

(4 bits)

CR03

CR02

CR01

CR00

CLKREC

(4 bits)

CL03

CL02

CL01

CL00

AGC

(4 bits)

AG03

AG02

AG01

AG00

Alarm equalizer/
lock detector

ALEQ

SER estimation

LE7

LE6

LE5

LE4

LE3

LE2

LE1

LE0

FFEI3

....

...

FFEI0

DFEI1

....

...

DFEI7

DFEI8

FFEQ3

....

...

FFEQ0

DFEQ1

....

...

DFEQ8

FFEI5

FFEQ5

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

7.1.12

C-

BUS WRITE PARAMETERS

Table 10 I

C-bus write parameters; 1-bit values

FFEI4

FFEQ4

IF_frequency_shift

FS7

FS6

FS5

FS4

FS3

FS2

FS1

FS0

IF_frequency_shift

FS11

FS10

FS9

FS8

PARAMETER

BIT

VALUE

DESCRIPTION

Input format

INP

2's complement

straight binary

Inversion demodulator

INVD

Q-branch = 0

1, 0, +1

Q-branch = 0 + 1, 0,

Demodulator

DEM

by-pass mode

normal mode

Half Nyquist filter

NYQ

filter in by-pass mode

half Nyquist filter on

Roll-off factor

RLF

15% roll-off

20% roll-off

Digital phase rotator

DPHR

off: pass through mode

General reset

RST

normal operation

reset (with automatic return to normal operation)

Offset

OFFS

off

Outer loop activation
(carrier recovery)

OUTE

outer loop inactive

outer loop active

Analog switches

ANAS

open

closed

1st and 2nd-order loop
(inner loop)

FSOL

1st-order loop

2nd-order loop

DAC current inversion

CARI

no inversion

inversion

CLKI

no inversion

inversion

AGCI

no inversion

inversion

FUNCTION

ADD

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

Table 11 I

C write parameters; 2-bit values

Equalizer

PRESET

normal operation

coefficient to zero (main tap to 1)

EDFE

normal operation

freeze coefficients of DFE part

EFFE

normal operation

freeze coefficients of FFE part

EFC
[fine AGC (equalizer
freeze centre tap)]

normal operation

freeze centre tap, no fine AGC

EAR

automatic reset switched OFF

automatic reset switched ON

FFEL

5 taps in FFE part

3 taps in FFE part

PARAMETER

BITS

DESCRIPTION

Window size (lock detector)

WS1

WS0

256 symbols

512 symbols

1024 symbols

2048 symbols

Output format

OUTB

OUTA

scheme 1

scheme 2

scheme 3

scheme 4

DAC carrier recovery
(maximum current)

CARB

CARA

100

150

200

DAC clock recovery
(maximum current)

CLKB

CLKA

100

150

200

DAC AGC
(maximum current)

AGCB

AGCA

100

150

200

PARAMETER

BIT

VALUE

DESCRIPTION

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

Table 12 I

C-bus write parameters; 3-bit values

Table 13 Convergence step for the equalizer (DFE and FFE parts)

Table 14 I

C-bus write parameters; 4-bit values

PARAMETER

BITS

DESCRIPTION

CONC

CONB

CONA

Constellation

4-QAM

16-QAM

32-QAM

64-QAM

256-QAM

DSTP2 FSTP2

DSTP1 FSTP1

DSTP0 FSTP0

CONVERGENCE STEP

(LOCK = 0)

CONVERGENCE STEP

(LOCK = 1)

-13

-15

-13

-14

-13

-12

-15

-12

-14

-12

-13

-12

-11

-15

PARAMETER

BITS

DESCRIPTION

OUTF

TSEL2

TSEL1

TSEL0

Output format

8 bits in parallel

I/Q 8 bits multiplexed (equalizer output)

semi-serial

Special test
modes

DO7 to DO4 = carrier recovery DAC input;
DO3 to DO0 = AGC DAC input

DO7 to DO6 = fine AGC;
DO5 to DO0 = clock recovery DAC input

DO7 to DO0 = I and Q equal input
(I/Q 8 bits multiplexed format)

DO7 to DO0 = I and Q equal output
(I/Q 8 bits multiplexed format)

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

7.1.13

C-

BUS READ PARAMETERS

Table 15 I

C-bus read parameter; 1-bit values

Table 16 I

C-bus read parameter; ADC carrier recovery; 4-bit value

Table 17 I

C-bus read parameter; ADC clock recovery; 4-bit value

Table 18 I

C-bus read parameter; ADC AGC; 4-bit value

Table 19 I

C-bus read parameter; 8-bit value

Note

1. The bits LE7 to LE0 give the number of symbols falling inside the lock detector active areas. The count is made during

an observation period (256 to 2048 symbols).
To obtain more details about the SER estimation, refer to

"Application Note AN96048".

Table 20 I

C-bus read parameter; 12-bit value

Note

1. The bits FS11 to FS0 indicate the remaining frequency shift of the QAM spectrum (IF spectrum). This data is useful

if the TDA8046H does not use the outer loop of carrier recovery (bit `OUTE' of the I

C-bus table set to 0).

To obtain more details about the frequency shift calculation, refer to the

"Application Note AN96048".

PARAMETER

BIT

VALUE

DESCRIPTION

Lock detect

no lock

lock

Alarm equalizer

ALEQ

normal operation (alarm off)

divergence detected (alarm on)

PARAMETER

BITS

DESCRIPTION

ADC carrier
recovery

CR03

CR02

CR01

CR00

carrier recovery: V

CARREC

= 0.25 +

DDD

(8b3 + 4b2 + 2b1 + b0) V

PARAMETER

BITS

DESCRIPTION

ADC clock
recovery

CL03

CL02

CL01

CL00

clock recovery: V

CLKREC

= 0.25 +

DDD

(8b3 + 4b2 + 2b1 + b0) V

PARAMETER

BITS

DESCRIPTION

ADC AGC

AG03

AG02

AG01

AG00

AGC: V

AGC

= 0.25 +

DDD

(8b3 + 4b2 + 2b1 + b0) V

PARAMETER

BITS

DESCRIPTION

SER

(1)

LE7

LE6

LE5

LE4

LE3

LE2

LE1

LE0

SER = f (b7 to b0)

PARAMETER

BITS

DESCRIPTION

IF_FREQ_SHIFT

(1)

FS11 to FS0

frequency shift = f (FS11 to FS0)

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

THERMAL CHARACTERISTICS

10 DEMODULATOR AND HALF NYQUIST FILTER CHARACTERISTICS

Note

1. Definition of the power inter-symbol interference:

Where N

conv

is the number of coefficients C

conv

. C

conv

(k) represent the coefficient resulting from the convolution of

the transmission and reception filters (K indicates the K

coefficient).

The power ISI specified in Table 1 has been calculated on a filter resulting from the convolution of the TDA8046 filters
and a truncated half-Nyquist filter with 57 T/4 taps for the 15% roll-off filter and 41 T/4 taps for the 20% roll-of filter
(see "

Application note AN96048" - Appendix B).

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

DDD

digital supply voltage

0.3

6.0

max

maximum voltage on all pins

DDD

tot

total power dissipation

amb

= 70

1.4

stg

storage temperature

+150

amb

operating ambient temperature

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th j-a

thermal resistance from junction to ambient

in free air

K/W

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

roll-off

15 or 20

pass-band ripple

0.05

stop-band ripple

see Figs 5 and 6

ISI

power

power inter-symbol interference (15% roll-off filter) note 1

power inter-symbol interference (20% roll-off filter) note 1

ISI

power

(

)

10 log

conv

(4k)

conv

(

)

conv

(0)

---------------------------------------------------------------------

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

11 LOCK DETECTOR CHARACTERISTICS

12 CARRIER RECOVERY CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

SNR

lock

signal-to-noise ratio to lock the
demodulator

4-QAM

16-QAM

32-QAM

64-QAM

256-QAM

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Carrier recovery detector

ARRIER RECOVERY

BIAS CURRENT FOR

DAC

S SET TO

37.5

detector constant

SNR = 21 dB for
64-QAM constellation

CAR

A/rad

SNR = 27 dB for
256-QAM constellation

6.05I

CAR

A/rad

CAR

frequency range

0.017r

MHz

n(inner)

loop bandwidth of inner loop

= 5 Msym/s

kHz

n(outer)

loop bandwidth of outer loop

0.3f

n(inner)

kHz

zero

zero current of DAC

100

+100

CAR

maximum DAC output current
(programmable)

200

DAC

DAC sampling rate

MHz

ARRIER RECOVERY

DAC

OUTPUT CURRENTS DURING LOCK

oCARlock

mean output current

CAR

oCARlock

matching of output currents

2.5

+2.5

ARRIER RECOVERY

DAC

OUTPUT CURRENTS DURING UNLOCK

oCARunlock

mean output current

CAR

oCARunlock

matching of output currents

2.5

+2.5

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

13 CLOCK RECOVERY CHARACTERISTICS

14 AGC CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Clock recovery detector

LOCK RECOVERY

BIAS CURRENT FOR

DAC

S SET TO

37.5

detector constant

SNR = 21 dB for
64-QAM constellation;
SNR = 27 dB for
256-QAM constellation

0.24I

CLK

A/rad

CLK

frequency range

100

ppm

natural frequency

400

CLK(max)

maximum DAC output current
(programmable)

200

DAC

DAC sample rate

MHz

LOCK RECOVERY

DAC output currents

oCLKlock

mean output current

CLK

oCLKlock

matching of output currents

2.5

+2.5

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

AGC detector

AGC

DETECTOR

BIAS CURRENT FOR

DAC

S SET TO

37.5

AGC

AGC range of detector

zero

zero current

100

+100

AGC(max)

maximum DAC output current
(programmable)

200

DAC

DAC sample rate

MHz

AGC DAC output currents

oAGC

mean output current

in lock

AGC

unlock

AGC

oAGC

matching of output current

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

15 INTEGRATED LOOP AMPLIFIERS CHARACTERISTICS

16 CHARACTERISTICS OF DIGITAL INPUTS AND OUTPUTS

DDD

= V

DDA

= 5 V; V

DDD(core)

= 3.3 V; T

amb

= 25

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Integrated loop amplifiers

OOP AMPLIFIERS

open loop gain

gain bandwidth product

MHz

ref

reference voltage

2.5

output voltage

0.1V

DDA

0.9V

DDA

L(VSSD)

load to ground

L(VDDD)

load to supply

6.5

NALOG SWITCHES

switch impedance

closed

open

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Clock outputs: CLKADC and CLKSDV

LOW level output voltage

0.1V

DDD

HIGH level output voltage

0.9V

DDD

CLK

cycle time

pulse width

40 : 60 duty cycle

rise time

= 30 pF

fall time

= 30 pF

load resistance

Clock input: CLK

i(rms)

input voltage level (RMS value)

sine wave

100

CLK

cycle time

pulse width

40 : 60 duty cycle

source

source resistance

Digital inputs: DIN8 to DIN0

LOW level input voltage

0.8

High level input voltage

2.0

set-up time

hold time

load capacitance

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

Digital outputs: DO1 to DO0 with respect to CLKOUT for semi-serial mode

LOW level output voltage

0.1V

DDD

HIGH level output voltage

0.9V

DDD

output delay time

oHD

output hold time

load capacitance

additional

Digital outputs: DO7 to DO0 with respect to CLKSDV for 8-bit parallel mode

LOW level output voltage

0.1V

DDD

HIGH level output voltage

0.9V

DDD

output delay time

oHD

output hold time

load capacitance

additional

Digital outputs: DO7 to DO0 with respect to CLKOUT for I/Q multiplexed mode

LOW level output voltage

0.1V

DDD

HIGH level output voltage

0.9V

DDD

output delay time

oHD

output hold time

Loop amplifier

output voltage level

0.1V

DDA

0.9V

DDA

DC voltage gain (open loop)

gain bandwidth product

MHz

load resistance

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

18 SOLDERING

18.1

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

18.2

Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

"Quality

Reference Handbook" (order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45

18.3

Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

The footprint must be at an angle of 45

to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

18.4

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

1996 Nov 19

Philips Semiconductors

Product specification

Multi-mode QAM demodulator

TDA8046

19 DEFINITIONS

20 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

21 PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors a worldwide company

SCA52

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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811

Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341

Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327

Portugal: see Spain

Romania: see Italy

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 247 9145, Fax. +7 095 247 9144

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494

South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 829 1849

Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 632 2000, Fax. +46 8 632 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 481 7730

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,
Chung Hsiao West Road, Sec. 1, P.O. Box 22978,
TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101, Fax. +43 1 60 101 1210

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773

Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700

Colombia: see South America

Czech Republic: see Austria

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 1949

Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580/xxx

France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300

Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240

Hungary: see Austria

India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722

Indonesia: see Singapore

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,
Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381

Middle East: see Italy

Printed in The Netherlands

537021/1200/02/pp48

Date of release: 1996 Nov 19

Document order number:

9397 750 01499

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8046H

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8046H