1999 Jul 28
2
Philips Semiconductors
Product specification
Satellite Demodulator and Decoder
(SDD3)
TDA8083
FEATURES
One chip Digital Video Broadcasting (DVB)
(ETS300421) compliant demodulator and concatenated
Viterbi and Reed-Solomon decoder with de-interleaver
and de-randomizer
3.3 V supply voltage
Relevant outputs are 5 V tolerant to ease interface to
5 V environment
Few external components for full application
On-chip crystal oscillator (4 MHz) and Phase-Locked
Loop (PLL) for internal clock generation
Power-on reset module
QPSK/BPSK demodulator:
Different modulation schemes: Quadrature Phase
Shift Keying (QPSK) and Binary Phase Shift Keying
(BPSK)
Interpolator and internal anti-aliasing filter to handle
variable symbol rates
Tuner Automatic Gain Control (AGC) control
Two on-chip matched 7-bit Analog-to-Digital
Converters (ADCs)
Square-root raised-cosine Nyquist
Maximum symbol frequency of 30 Msymbols/s
Can be used at low channel Signal-to-Noise Ratio
(S/R)
Internal full digital carrier recovery, clock recovery
and AGC loops with programmable loop filters
Two carrier recovery loops enabling optimum phase
noise suppression
S/R estimation.
Viterbi decoder:
Rate
1
/
2
convolutional code based
Constraint length K = 7 with G
1
= 171
oct
and
G
2
= 133
oct
Supported puncturing code rates:
1
/
2
,
2
/
3
,
3
/
4
,
4
/
5
,
5
/
6
,
6
/
7
,
7
/
8
and
8
/
9
4-bit `soft decision' inputs for both I and Q
Truncation length of 144
Automatic synchronization to detect puncturing rate
and spectral inversion
Channel Bit Error Rate (BER) estimation from
10
-
2
to 10
-
8
Differential decoding optional.
Reed-Solomon (RS) decoder:
(204, 188, T = 8) Reed-Solomon code
Automatic synchronization of bytes, transport
packets and frames
Internal convolutional de-interleaving (I = 12; using
internal memory)
De-randomizer based on Pseudo Random Binary
Sequence (PRBS)
External indication of uncorrectable error (transport
error indicator is set)
Indication of the number of lost blocks
Indication of the number of corrected blocks.
Interface:
I
2
C-bus interface initializes and monitors the
demodulator and Forward Error Correction (FEC)
decoder; a default mode is defined
6-bit I/O expander for flexible access to and from the
I
2
C-bus
I
2
C-bus configurable interrupt input
Switchable I
2
C-bus loop-through to suppress I
2
C-bus
crosstalk in the tuner
Digital Satellite Equipment Control (DiSEqC) 1.X,
tone burst generation and tone mode with a
22 or 44 kHz carrier
Parallel or serial output mode for MPEG transport
stream (3-state mode also possible)
Standby mode for reduced power consumption.
Package: QFP100
Boundary scan test.
APPLICATIONS
Digital satellite TV: demodulation and FEC.
1999 Jul 28
3
Philips Semiconductors
Product specification
Satellite Demodulator and Decoder
(SDD3)
TDA8083
GENERAL DESCRIPTION
This document specifies a DVB compliant demodulator
and forward error correction decoder IC for reception of
QPSK or BPSK modulated signals for satellite
applications. The Satellite Demodulator and Decoder
(SSD) can handle variable symbol rates without adapting
the analog filters within the tuner. Typical applications for
this device are:
MCPC (Multi-Channel Per Carrier): one QPSK or
BPSK modulated signal in a single satellite channel
(transponder)
Simul-cast: QPSK or BPSK modulated signal together
with a Frequency Modulated (FM) signal in a single
satellite channel (transponder).
The TDA8083 can handle variable symbol rates in the
range of 12 to 30 Msymbols/s with a minimum number of
low cost and non-critical external components.
The TDA8083 has minimal interfaces with the tuner. It only
requires the demodulated analog I and Q baseband input
signals and provides a tuner AGC control signal.
Analog-to-digital conversion is done internally by two
matched 7-bit ADCs.
The TDA8083 runs on a low frequency crystal which is
upconverted to a clock frequency by means of an internal
PLL. Furthermore, the TDA8083 has an internal anti-alias
filter, which can cover the range of symbol frequencies
without the need to switch external (SAW) filters.
The TDA8083 has a double carrier loop configuration
which has excellent capabilities of tracking phase noise.
Synchronization of the FEC unit is done completely
internally, thereby minimizing I
2
C-bus communication.
The output of the TDA8083 allows different output modes
(parallel or serial) to interface to a demultiplexer,
descrambler or MPEG-2 decoder including a 3-state
mode. For evaluation of the TDA8083, demodulator and
Viterbi decoder outputs can be made available externally.
The SDD can be controlled and monitored by the I
2
C-bus.
A 5-bit bidirectional I/O expander and an interrupt line are
available. By sending an interrupt signal, the SDD can
inform the microcontroller of its internal status. Separate
resets are available for logic only, logic plus the I
2
C-bus
and carrier loops. A switchable I
2
C-bus loop-through to the
tuner is implemented to switch off the I
2
C-bus connection
to the tuner. This reduces phase noise in the tuner in case
of I
2
C-bus crosstalk.
Furthermore, for dish control applications hardware
supports DiSEqC 1.X and tone burst generation via
I
2
C-bus control. A 22 or a 44 kHz carrier can be generated
(tone mode).
1999 Jul 28
4
Philips Semiconductors
Product specification
Satellite Demodulator and Decoder
(SDD3)
TDA8083
QUICK REFERENCE DATA
Notes
1. Typical value is specified for a symbol rate of 27.5 Msymbols/s, a puncture rate of
3
/
4
and a supply voltage of 3.3 V.
Maximum value is specified for a symbol rate of 30 Msymbols/s, a puncture rate of
7
/
8
, a supply voltage of 3.6 V and
using a 4 MHz crystal.
2. Implementation loss at the demodulator output and minimum SNR to lock the TDA8083 are measured including tuner
in a laboratory environment at a symbol rate of 27.5 MS/s.
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DDA
analog supply voltage
3.0
3.3
3.6
V
V
DDD
digital supply voltage
3.0
3.3
3.6
V
I
DD(tot)
total supply current
note 1
-
270
340
mA
f
clk(int)
internal clock frequency
-
-
64
MHz
r
s
symbol rate
12
-
30
Msymbols/s
ro
Nyquist roll-off
-
35
-
%
IL
implementation loss
note 2
-
0.3
-
dB
S/R
signal-to-noise ratio
locking the SDD in
QPSK mode; note 2
2
-
-
dB
P
tot
total power dissipation
T
amb
= 70
C; note 1
-
890
1220
mW
T
stg
storage temperature
-
55
-
+150
C
T
amb
ambient temperature
0
-
70
C
T
j
junction temperature
T
amb
= 70
C
-
-
125
C
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TDA8083H
QFP100
plastic quad flat package; 100 leads (lead length 1.95 mm); body
14
20
2.8 mm
SOT317-2
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