September 1994

Philips Semiconductors

Preliminary specification

Integrated NTSC decoder
and sync processor

TDA8315T

FEATURES

CVBS or Y/C input

Integrated chrominance trap and bandpass filters
(automatically calibrated)

Integrated luminance delay line

Alignment-free NTSC colour decoder

Horizontal PLL with an alignment-free horizontal
oscillator

Vertical count-down circuit

Low dissipation (320 mW)

Small amount of peripheral components compared with
competition ICs.

GENERAL DESCRIPTION

The TDA8315T is an alignment-free NTSC decoder/sync
processor. The device can be used for normal television
applications and for Picture-in-Picture (PIP) applications.

The input signal can be either CVBS or Y/C and at the
outputs the following signals are available:

Luminance signal

Colour difference signals (U and V)

Horizontal and vertical synchronization pulses

Back porch clamping pulse (burst-key pulse).

The supply voltage for the IC is 8 V. It is available in a
24-pin SO package.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

supply voltage (pins 11 and 12)

7.2

8.0

8.8

supply current

Input voltages

13(p-p)

CVBS/Y input voltage (peak-to-peak value)

15(p-p)

chrominance input voltage (peak-to-peak value)

0.3

Output signals

O(b-w)

luminance output voltage (blank-to-white value)

1.65

21(p-p)

U output voltage (peak-to-peak value)

1.5

20(p-p)

V output voltage (peak-to-peak value)

1.5

horizontal sync pulse

vertical sync pulse

back porch clamping pulse

Control voltages

control

control voltages for Saturation and Hue

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA8315T

SO24

plastic small outline package; 24 leads; body width 7.5 mm

SOT137-1

September 1994

Philips Semiconductors

Preliminary specification

Integrated NTSC decoder

and sync processor

TDA8315T

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BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MBE015

CHROMINANCE

BANDPASS

CHROMINANCE

TRAP

CVBS/Y

SWITCH

COINCIDENCE

DETECTOR

SYNC

SEPARATOR

PHASE

DETECTOR

VERTICAL

SYNC

SEPARATOR

OSCILLATOR

PLUS

CONTROL

H/V DIVIDER

FILTER

TUNING

NTSC

DECODER

MATRIX

U/V-SIGNALS

SATURATION

CONTROL

LUMINANCE

DELAY LINE

AMPLIFIER

PULSE

SHAPER

reference

PH1LF

DEC DIG

V P1

GND1

V P2

GND2

DEC BG

CVBS

CHROMA

CVBS/Y
switch

DEC FT

PLL

XTAL

HUE

SSC

DEM SW

SAT

VOUT

CLAMP

HOUT

TDA8315T

September 1994

Philips Semiconductors

Preliminary specification

Integrated NTSC decoder
and sync processor

TDA8315T

PINNING

Note

1. In the application the test pins must be connected to

ground.

SYMBOL

PIN

DESCRIPTION

TEST1

(1)

test pin 1

HOUT

horizontal output pulse

GND1

ground 1 (0 V)

PH1LF

phase 1 loop filter

DEC

bandgap decoupling

TEST2

(1)

test pin 2

VOUT

vertical output pulse

DEM

demodulation angle switch

DEC

DIG

decoupling digital supply

CLAMP

back porch clamping pulse

supply voltage 1 (+8 V)

supply voltage 2 (+8 V)

CVBS/Y

CVBS/Y input

DEC

decoupling filter tuning

CHROMA

chrominance and switch input

SAT

saturation control input

SCS

sub-carrier signal output

HUE

hue control input

Y output

V output

U output

PLL

PLL colour filter

GND2

ground 2 (0 V)

XTAL

3.58 MHz crystal connection

Fig.2 Pin configuration.

handbook, halfpage

XTAL

GND2

PLL

HUE

SCS

SAT

CHROMA

DIG

DEC

DEM

DEC

VOUT

TEST2

PH1LF

GND1

HOUT

TEST1

CLAMP

CVBS/Y

DEC FT

MBE016

TDA8315T

September 1994

Philips Semiconductors

Preliminary specification

Integrated NTSC decoder
and sync processor

TDA8315T

FUNCTIONAL DESCRIPTION

CVBS or Y/C input

The TDA8315T has a video input which can be switched
to CVBS (with internal chrominance bandpass and trap
filters) and to Y/C (without chrominance bandpass and
trap filters). The switching between CVBS and Y/C is
achieved by the DC level of the CHROMA input (pin 15).

Integrated video filters

The circuit contains a chrominance bandpass and trap
circuit. The filters are realised by gyrator circuits that are
automatically tuned by comparing the tuning frequency
with the crystal frequency of the decoder. The
chrominance trap can be switched off by the DC level of
the CHROMA input.

The luminance delay line is also realised by gyrator
circuits.

Colour decoder

The colour decoder contains an alignment-free crystal
oscillator, a colour killer circuit and colour difference
demodulators. The gain of the two colour difference signal
demodulators is identical and the phase angle of the
reference carrier signals is 90

. This phase shift is

achieved internally. It is possible to switch the demodulator
angle to 110

by an internal matrix circuit. The switching is

obtained externally via pin 8.

Synchronization circuit

The sync separator is preceded by a voltage controlled
amplifier which adjusts the sync pulse amplitude to a fixed
level. The sync pulses are then fed to the slicing stage
(separator) which operates at 50% of the amplitude.

The separated sync pulses are fed to the first phase
detector and to the coincidence detector. The coincidence
detector is used to detect whether the line oscillator is
synchronized. The PLL has a very high static steepness,
this ensures that the phase of the picture is independent of
the line frequency. The line oscillator operates at twice the
line frequency.

The oscillator network is internal. Because of the spread of
internal components an automatic adjustment circuit has
been added to the IC.
The circuit compares the oscillator frequency with that of
the crystal oscillator in the colour decoder. This results in
a free-running frequency which deviates less than 2% from
the typical value.

The horizontal output pulse is derived from the horizontal
oscillator via a pulse shaper. The pulse width of the output
pulse is 5.4

s, the front edge of this pulse coincides with

the front edge of the sync pulse at the input.

The vertical output pulse is generated by a count-down
circuit. The pulse width is approximately 380

s. Both the

horizontal and vertical pulses will always be available at
the outputs even when no input signal is available.

September 1994

Philips Semiconductors

Preliminary specification

Integrated NTSC decoder
and sync processor

TDA8315T

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC134).

THERMAL CHARACTERISTICS

CHARACTERISTICS

= 8 V; T

amb

= 25

C; unless otherwise specified.

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

supply voltage

9.0

stg

storage temperature

+150

amb

operating ambient temperature

+70

sld

soldering temperature for 5 s

260

maximum operating junction temperature

125

SYMBOL

PARAMETER

VALUE

UNIT

th j-a

thermal resistance from junction to ambient in free air

K/W

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

supply voltage (pins 11 and 12)

7.2

8.0

8.8

supply current (pins 11 and 12)

tot

total power dissipation

320

CVBS or Y/C input

CVBS/Y

INPUT

(

13)

13(p-p)

CVBS/Y input voltage (peak-to-peak value)

notes 1 and 2

1.4

CVBS/Y input current

OMBINED CHROMINANCE AND SWITCH INPUT

(

15)

15(p-p)

chrominance input voltage
(peak-to-peak value)

notes 2 and 3

0.3

15(p-p)

input signal amplitude before clipping
occurs (peak-to-peak value)

note 2

chrominance input resistance

chrominance input capacitance

note 4

DC input voltage for Y/C operation

DC input voltage for CVBS operation

Chrominance filters and luminance delay line

HROMINANCE TRAP CIRCUIT

trap

trap frequency

3.58

MHz

luminance signal bandwidth

note 2

2.7

MHz

colour subcarrier rejection

September 1994

Philips Semiconductors

Preliminary specification

Integrated NTSC decoder
and sync processor

TDA8315T

HROMINANCE BANDPASS CIRCUIT

centre frequency

3.58

MHz

QBP

bandpass quality factor

DELAY LINE

delay time

note 2

390

bandwidth of internal delay line

note 2

MHz

OUTPUT SIGNAL

(

19)

19(p-p)

output signal amplitude
(peak-to-peak value)

note 1

2.27

output impedance

350

top sync level

2.85

S/N

signal-to-noise ratio

notes 2 and 5

Colour decoder

HROMINANCE AMPLIFIER

ACC

ACC control range

note 6

change in amplitude of the output signals
over the ACC range

THR

threshold colour killer ON

tbf

HYS

off

hysteresis colour killer OFF

note 2

strong input signal

S/N

40 dB

noisy input signal

ACL

CIRCUIT

chrominance burst ratio at which the ACL
starts to operate

2.3

2.7

EFERENCE PART

Phase-locked loop; note 7 (filter connected to pin 22)

catching range

300

500

phase shift for a

400 Hz deviation of the

oscillator frequency

note 7

deg

Oscillator (pin 24)

osc

temperature coefficient of f

osc

note 2

2.0

2.5

Hz/K

osc

deviation with respect to V

note 2;
V

= 8 V

10%

250

input resistance

note 4

1.5

input capacitance

note 4

UE CONTROL INPUT

(

18)

HUE

hue control range

see also Fig.4

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

September 1994

Philips Semiconductors

Preliminary specification

Integrated NTSC decoder
and sync processor

TDA8315T

EMODULATOR OUTPUTS

(

PINS

AND

21)

bandwidth of demodulators

3 dB; note 8

650

kHz

change of output signal amplitude with
temperature

note 2

0.1

%/K

change of output signal amplitude with
supply voltage

note 2

0.1

gain ratio of demodulator G(

U)/G(

0.9

1.0

1.1

demodulator angle

pin 8 LOW

deg

pin 8 HIGH

105

110

115

deg

21(p-p)

U output signal amplitude at nominal

saturation (peak-to-peak value)

note 9

1.5

20(p-p)

V output signal amplitude at nominal

saturation (peak-to-peak value)

note 9

1.5

output impedance (

U)/(

V) output

500

DC output voltage

EMODULATION ANGLE SWITCH INPUT

(

input voltage for 90

angle

input voltage for 110

angle

UBCARRIER OUTPUT SIGNAL

(

17)

17(p-p)

output signal amplitude
(peak-to-peak value)

300

output impedance

250

DC output voltage

1.6

Horizontal and vertical synchronization circuits

YNC VIDEO INPUT

(

13)

sync pulse amplitude

note 4

300

slicing level

note 10

ERTICAL SYNC

width of the vertical sync pulse without sync
instability

note 11

ORIZONTAL OSCILLATOR

free-running frequency

15734

spread on free running frequency

osc

frequency variation with respect to the
supply voltage

= 8 V

10%;

note 2

0.2

0.5

osc

frequency variation with temperature

note 2

tbf

Hz/K

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

September 1994

Philips Semiconductors

Preliminary specification

Integrated NTSC decoder
and sync processor

TDA8315T

ORIZONTAL

PLL;

NOTE

12 (

FILTER CONNECTED TO PIN

holding range PLL

0.9

1.2

kHz

catching range PLL

note 2

0.6

0.9

kHz

S/N

signal-to-noise ratio of the video input
signal at which the time constant is
switched

HYS

hysteresis at the switching point

ORIZONTAL OUTPUT

(

HIGH level output voltage

= 2 mA

2.4

4.0

LOW level output voltage

= 2 mA

0.3

0.6

O(sink)

output sink current

O(source)

output source current

pulse width

note 13

5.4

delay time between positive edge of the
horizontal output pulse and start of the
horizontal sync pulse at the input

ACK PORCH CLAMPING OUTPUT

(

10)

HIGH level output voltage

= 2 mA

2.4

4.0

LOW level output voltage

= 2 mA

0.3

0.6

O(sink)

output sink current

O(source)

output source current

pulse width

3.2

3.4

3.6

delay time between start of clamping pulse
and start of the start sync pulse

5.2

5.4

5.6

ERTICAL OUTPUT

(

7);

NOTE

free-running frequency

lock

locking range

54.6

64.5

divider value not locked

525

locking range (lines/frame)

488

576

HIGH level output voltage

= 2 mA

2.4

4.0

LOW level output voltage

= 2 mA

0.3

0.6

O(sink)

output sink current

O(source)

output source current

pulse width (6 line periods)

380

delay time between start of the vertical sync
pulse at the input and the positive edge of
the output pulse

37.5

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

September 1994

Philips Semiconductors

Preliminary specification

Integrated NTSC decoder
and sync processor

TDA8315T

Notes to the characteristics

1. Signal with negative-going sync. Amplitude includes sync pulse amplitude.

2. This parameter is not tested during production and is guaranteed by the design and qualified by matrix batches which

are made in the pilot production period.

3. Burst amplitude; for a colour bar with 75% saturation the chrominance signal amplitude is 660 mV (p-p).

4. This parameter is not tested during production and is just given as application information for the designer of the

television receiver.

5. The signal-to-noise ratio is specified as a peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz).

6. At a chrominance input voltage of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal amplitude

300 mV (p-p)) the dynamic range of the ACC is +6 and

18 dB.

7. All frequency variations are referenced to 3.58 MHz carrier frequency.

All oscillator specifications are measured with the Philips crystal series 9922 520.
If the spurious response of the crystal is lower than

3 dB with respect to the fundamental frequency for a damping

resistance of 1.5 k

, oscillation at the fundamental frequency is guaranteed.

The catching and detuning range are measured for nominal crystal parameters. These are:

a) load resonance frequency f

= 20 pF) = 3.579545 MHz

b) motional capacitance C

= 14.5 fF

c) parallel capacitance C

= 4.5 pF.

The actual load capacitance in the application should be C

= 18 pF to account for parasitic capacitances on

and off chip.
The free-running frequency of the oscillator can be checked by pulling the saturation control pin to the positive supply
rail. In that condition the colour killer is not active so that the frequency offset is visible on the screen.

8. This value indicates the bandwidth of the complete chrominance circuit including the chrominance bandpass filter.

The bandwidth of the demodulator low-pass filter is approximately 1 MHz.

9. Output signal amplitude for a standard colour bar signal with 75% saturation and a demodulation angle of 90

. For a

demodulation angle of 110

the

V signal amplitude will decrease to 1.2 V (p-p) and the

U signal amplitude remains

unchanged. The nominal saturation is specified as maximum

6 dB.

10. Slicing level independent of sync pulse amplitude. The slicing level of the vertical sync separator is 70% (slicing level

in direction of black level) during strong signal reception (no noise detected in the incoming signal) and 30% during
weak signal reception.

11. The horizontal and vertical sync are stable while processing Copy Guard signals and signals with phase shifted sync

pulses (stretched tapes). Trick mode conditions of the VCR will also not disturb the synchronization. The value given
is the delay caused by the vertical sync pulse integrator. The integrator has been designed such that the vertical sync
is not disturbed for special anti-copy tapes with vertical sync pulses with an on/off time of 10/22

12. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is

switched depending on the input signal condition. Therefore the circuit contains a noise detector and the time
constant is switched to `slow' when excessive noise is present in the signal. In the `fast' mode during the vertical
retrace time the phase detector current is increased 50% so that phase errors due to head-switching of the VCR are
corrected as soon as possible.

To prevent the horizontal synchronization being disturbed by anti-copy guard signals such as Macrovision the phase
detector is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage.
The width of the gate pulse is approximately 12

s. during weak signal conditions (noise detector active) the gating

is active during the complete scan period and the width of the gate pulse is reduced to 5.7

s so that the effect of the

noise is reduced to a minimum.

The output current of the phase detector in the two modes is shown in Table 1.

September 1994

Philips Semiconductors

Preliminary specification

Integrated NTSC decoder
and sync processor

TDA8315T

13. The horizontal output pulses are obtained from the horizontal oscillator by a pulse shaper. The width of the output

pulse is approximately 5.4

s and the rising edge of the pulse symmetrically coincides with the start of the sync pulse

at the input.

14. The vertical output pulses are generated by a divider circuit. The vertical output pulse has a delay of 37.5

s with

respect to the start of the vertical sync pulse at the input. This is caused by the clock frequency of the divider being
twice the horizontal frequency.

This divider circuit has 2 modes of operation:

Search mode (large window).

This mode is switched on when the circuit is not synchronized or, when a non-standard signal is received (the number
of lines per frame outside the range is between 261 and 264). In the search mode the divider can be triggered
between line 244 and line 288 (approximately 54 to 64.5 Hz).

Standard mode (narrow window).

This mode is switched on when more than 15 successive vertical sync pulses are detected in the narrow window.
When the circuit is in the standard mode and a vertical sync pulse is missing the output pulse is generated at the end
of the window. Consequently, the disturbance of the picture is very small. The circuit will switch back to the search
window when, for 6 successive vertical periods, no sync pulses are found within the window. When no input signal
is available the divider generates output pulses with a timing of 262.5 lines (standard 60 Hz signal).

Table 1 Output current of phase detector.

Note

1. Vertical retrace.

QUALITY SPECIFICATION

Quality level in accordance with SNW-FQ-611-part E.

Notes

1. All pins are protected against ESD by means of internal clamping diodes.

2. Range A is for Human body model.

3. Range B is for machine model.

Latch up

All pins meet the specification:

trigger

100 mA or

1.5 V

DDmax

trigger

100 mA or

0.5 V

DDmax

CURRENT PHASE DETECTOR DURING

SCAN (

VERTICAL RETRACE (

GATED YES/NO

Weak signal and synchronized

YES (5.7

Strong signal and synchronized

180

270

YES (12

(1)

Not synchronized

180

270

SYMBOL

PARAMETER

RANGE A

(2)

RANGE B

(3)

UNIT

ESD

protection circuit specification (note 1)

>2000

>200

100

200

1500

September 1994

Philips Semiconductors

Preliminary specification

Integrated NTSC decoder
and sync processor

TDA8315T

SOLDERING

Plastic small-outline packages

Y WAVE

During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150

C within 6 s.

Typical dwell time is 4 s at 250

A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.

Y SOLDER PASTE REFLOW

Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45

EPAIRING SOLDERED JOINTS

(

BY HAND

HELD SOLDERING

IRON OR PULSE

HEATED SOLDER TOOL

)

Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300

C. When using proper tools, all other pins can be

soldered in one operation within 2 to 5 s at between 270
and 320

C. (Pulse-heated soldering is not recommended

for SO packages.)

For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.

September 1994

Philips Semiconductors

Preliminary specification

Integrated NTSC decoder
and sync processor

TDA8315T

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Semiconductors

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Pakistan: Philips Electrical Industries of Pakistan Ltd.,

Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. (021)587 4641-49,
Fax. (021)577035/5874546.

Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474

Portugal: PHILIPS PORTUGUESA, S.A.,

Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores,
Apartado 300, 2795 LINDA-A-VELHA,
Tel. (01)14163160/4163333, Fax. (01)14163174/4163366.

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. (65)350 2000, Fax. (65)251 6500

South Africa: S.A. PHILIPS Pty Ltd.,

195-215 Main Road Martindale, 2092 JOHANNESBURG,
P.O. Box 7430 Johannesburg 2000,
Tel. (011)470-5911, Fax. (011)470-5494.

Spain: Balmes 22, 08007 BARCELONA,

Tel. (03)301 6312, Fax. (03)301 42 43

Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,

Tel. (0)8-632 2000, Fax. (0)8-632 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. (01)488 2211, Fax. (01)481 77 30

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West

Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978,
TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382.

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong,
Bangkok 10260, THAILAND,
Tel. (662)398-0141, Fax. (662)398-3319.

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. (0 212)279 2770, Fax. (0212)269 3094

United Kingdom: Philips Semiconductors LTD.,

276 Bath road, Hayes, MIDDLESEX UB3 5BX,
Tel. (081)73050000, Fax. (081)7548421

United States: 811 East Arques Avenue, SUNNYVALE,

CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556

Uruguay: Coronel Mora 433, MONTEVIDEO,

Tel. (02)70-4044, Fax. (02)92 0601

For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-724825

SCD34

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The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
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other industrial or intellectual property rights.

Printed in The Netherlands

533061/1500/01/pp16

Date of release: September 1994

Document order number:

9397 739 00011

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8315T/N3

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8315T/N3