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Электронный компонент: TDA844

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DATA SHEET
Product specification
Supersedes data of 1999 Dec 01
2000 Mar 29
DISCRETE SEMICONDUCTORS
BF1202; BF1202R; BF1202WR
N-channel dual-gate PoLo
MOS-FETs
2000 Mar 29
2
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
FEATURES
Short channel transistor with high
forward transfer admittance to input
capacitance ratio
Low noise gain controlled amplifier
Partly internal self-biasing circuit to
ensure good cross-modulation
performance during AGC and good
DC stabilization.
APPLICATIONS
VHF and UHF applications with
3 to 9 V supply voltage, such as
digital and analogue television
tuners and professional
communications equipment.
DESCRIPTION
Enhancement type N-channel
field-effect transistor with source and
substrate interconnected. Integrated
diodes between gates and source
protect against excessive input
voltage surges. The BF1202,
BF1202R and BF1202WR are
encapsulated in the SOT143B,
SOT143R and SOT343R plastic
packages respectively.
PINNING
PIN
DESCRIPTION
1
source
2
drain
3
gate 2
4
gate 1
handbook, 2 columns
Top view
MSB014
1
2
3
4
Fig.1
Simplified outline
(SOT143B).
BF1202 marking code: LDp
handbook, 2 columns
Top view
MSB035
1
2
4
3
Fig.2
Simplified outline
(SOT143R).
BF1202R marking code: LEp
page
Top view
MSB842
2
1
4
3
Fig.3
Simplified outline
(SOT343R).
BF1202WR marking code: LE
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DS
drain-source voltage
-
-
10
V
I
D
drain current
-
-
30
mA
P
tot
total power dissipation
-
-
200
mW
y
fs
forward transfer admittance
25
30
40
mS
C
ig1-ss
input capacitance at gate 1
-
1.7
2.2
pF
C
rss
reverse transfer capacitance
f = 1 MHz
-
15
30
fF
F
noise figure
f = 800 MHz
-
1.1
1.8
dB
X
mod
cross-modulation
input level for k = 1% at
40 dB AGC
100
105
-
dB
V
T
j
operating junction temperature
-
-
150
C
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
2000 Mar 29
3
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
Note
1. T
s
is the temperature of the soldering point of the source lead.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
drain-source voltage
-
10
V
I
D
drain current
-
30
mA
I
G1
gate 1 current
-
10
mA
I
G2
gate 2 current
-
10
mA
P
tot
total power dissipation
BF1202; BF1202R
T
s
113
C; note 1
-
200
mW
BF1202WR
T
s
119
C; note 1
-
200
mW
T
stg
storage temperature
-
65
+150
C
T
j
operating junction temperature
-
150
C
SYMBOL
PARAMETER
VALUE
UNIT
R
th j-s
thermal resistance from junction to soldering point
BF1202; BF1202R
185
K/W
BF1202WR
155
K/W
handbook, halfpage
0
50
(1)
(2)
Ts (
C)
Ptot
(mW)
100
200
250
0
200
150
150
100
50
MCD951
Fig.4 Power derating curve.
(1) BF1202WR.
(2) BF1202; BF1202R.
2000 Mar 29
4
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
STATIC CHARACTERISTICS
T
j
= 25
C unless otherwise specified.
Note
1. R
G1
connects G
1
to V
GG
= 5 V.
DYNAMIC CHARACTERISTICS
Common source; T
amb
= 25
C; V
G2-S
= 4 V; V
DS
= 5 V; I
D
= 12 mA; unless otherwise specified.
Note
1. Measured in Fig.21 test circuit.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
(BR)DSS
drain-source breakdown voltage
V
G1-S
= V
G2-S
= 0; I
D
= 10
A
10
-
V
V
(BR)G1-SS
gate 1-source breakdown voltage
V
G2-S
= V
DS
= 0; I
G1-S
= 10 mA
6
-
V
V
(BR)G2-SS
gate 2-source breakdown voltage
V
G1-S
= V
DS
= 0; I
G2-S
= 10 mA
6
-
V
V
(F)S-G1
forward source-gate 1 voltage
V
G2-S
= V
DS
= 0; I
S-G1
= 10 mA
0.5
1.5
V
V
(F)S-G2
forward source-gate 2 voltage
V
G1-S
= V
DS
= 0; I
S-G2
= 10 mA
0.5
1.5
V
V
G1-S(th)
gate 1-source threshold voltage
V
G2-S
= 4 V; V
DS
= 5 V; I
D
= 100
A
0.3
1.0
V
V
G2-S(th)
gate 2-source threshold voltage
V
G1-S
= 5 V; V
DS
= 5 V; I
D
= 100
A
0.3
1.2
V
I
DSX
drain-source current
V
G2-S
= 4 V; V
DS
= 5 V; R
G1
= 120 k
;
note 1
8
16
mA
I
G1-SS
gate 1 cut-off current
V
G2-S
= V
DS
= 0; V
G1-S
= 5 V
-
50
nA
I
G2-SS
gate 2 cut-off current
V
G1-S
= V
DS
= 0; V
G2-S
= 4 V
-
20
nA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
y
fs
forward transfer admittance
pulsed; T
j
= 25
C
25
30
40
mS
C
ig1-ss
input capacitance at gate 1
f = 1 MHz
-
1.7
2.2
pF
C
ig2-ss
input capacitance at gate 2
f = 1 MHz
-
1
-
pF
C
oss
output capacitance
f = 1 MHz
-
0.85
-
pF
C
rss
reverse transfer capacitance f = 1 MHz
-
15
30
fF
F
noise figure
f = 10.7 MHz; G
S
= 20 mS; B
S
= 0
-
9
11
dB
f = 400 MHz; Y
S
= Y
S opt
-
0.9
1.5
dB
f = 800 MHz; Y
S
= Y
S opt
-
1.1
1.8
dB
G
tr
power gain
f = 200 MHz; G
S
= 2 mS; B
S
= B
S opt
;
G
L
= 0.5 mS; B
L
= B
L opt
-
34.5
-
dB
f = 400 MHz; G
S
= 2 mS; B
S
= B
S opt
;
G
L
= 1 mS; B
L
= B
L opt
-
30.5
-
dB
f = 800 MHz; G
S
= 3.3 mS; B
S
= B
S opt
;
G
L
= 1 mS; B
L
= B
L opt
-
26.5
-
dB
X
mod
cross-modulation
input level for k = 1%; f
w
= 50 MHz;
f
unw
= 60 MHz; note 1
at 0 dB AGC
90
-
-
dB
V
at 10 dB AGC
-
92
-
dB
V
at 40 dB AGC
100
105
-
dB
V
2000 Mar 29
5
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
handbook, halfpage
0
2
20
0
4
8
12
16
0.4
0.8
1.2
1.6
VG1-S (V)
ID
(mA)
MCD952
VG2-S
=
4 V
2.5 V
3.5 V
3 V
2 V
1.5 V
1 V
Fig.5 Transfer characteristics; typical values.
V
DS
= 5 V.
T
j
= 25
C.
handbook, halfpage
0
10
24
0
8
16
2
VDS (V)
ID
(mA)
6
4
8
MCD953
VG1-S
=
1.5 V
1.4 V
1.2 V
1.3 V
1.1 V
1 V
0.9 V
Fig.6 Output characteristics; typical values.
V
G2-S
= 4 V.
T
j
= 25
C.
handbook, halfpage
0
2.5
100
0
20
40
60
80
0.5
1
1.5
2
VG1-S (V)
IG1
(
A)
MCD954
VG2-S
=
4 V
3.5 V
3 V
2.5 V
2 V
1.5 V
1 V
Fig.7
Gate 1 current as a function of gate 1
voltage; typical values.
V
DS
= 5 V.
T
j
= 25
C.
V
DS
= 5 V.
T
j
= 25
C.
handbook, halfpage
0
ID (mA)
4
20
40
30
10
0
20
8
12
16
MCD955
yfs
(mS)
3.5 V
2.5 V
3 V
2 V
VG2-S
=
4 V
Fig.8
Forward transfer admittance as a function
of drain current; typical values.
V
DS
= 5 V.
T
j
= 25
C.
2000 Mar 29
6
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
handbook, halfpage
0
50
20
0
4
8
12
16
10
20
30
40
IG1 (
A)
ID
(mA)
MCD956
Fig.9
Drain current as a function of gate 1 current;
typical values.
V
DS
= 5 V; V
G2-S
= 4 V.
T
j
= 25
C.
handbook, halfpage
0
VGG (V)
1
5
16
12
4
0
8
2
3
4
MCD957
ID
(mA)
Fig.10 Drain current as a function of gate 1 supply
voltage (= V
GG
); typical values.
V
DS
= 5 V; V
G2-S
= 4 V; T
j
= 25
C.
R
G1
= 120 k
(connected to V
GG
); see Fig.21.
handbook, halfpage
0
2
4
6
VGG
=
VDS (V)
ID
(mA)
20
0
16
12
8
4
MCD958
RG1
=
68 k
82 k
100 k
120 k
150 k
220 k
180 k
Fig.11 Drain current as a function of gate 1 (= V
GG
)
and drain supply voltage; typical values.
V
G2-S
= 4 V; T
j
= 25
C.
R
G1
connected to V
GG
; see Fig.21.
handbook, halfpage
0
2
4
6
16
12
4
0
8
MCD959
VG2-S (V)
ID
(mA)
4.5 V
4 V
3 V
VGG
=
5 V
3.5 V
V
DS
= 5 V; T
j
= 25
C.
R
G1
= 120 k
(connected to V
GG
); see Fig.21.
Fig.12 Drain current as a function of gate 2
voltage; typical values.
2000 Mar 29
7
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
handbook, halfpage
0
2
4
6
40
30
10
0
20
MCD960
VG2-S (V)
IG1
(
A)
4 V
3.5 V
3 V
4.5 V
VGG
=
5 V
Fig.13 Gate 1 current as a function of gate 2
voltage; typical values.
V
DS
= 5 V; T
j
= 25
C.
R
G1
= 120 k
(connected to V
GG
); see Fig.21.
handbook, halfpage
0
1
2
4
0
-
50
-
10
3
VAGC (V)
gain
reduction
(dB)
-
20
-
30
-
40
MCD961
Fig.14 Typical gain reduction as a function of the
AGC voltage; see Fig.21.
V
DS
= 5 V; V
GG
= 5 V; R
G1
= 120 k
;
f = 50 MHz; T
amb
= 25
C.
handbook, halfpage
0
gain reduction (dB)
10
50
120
110
90
80
100
20
30
40
MCD962
Vunw
(dB
V)
Fig.15 Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; Fig.21.
V
DS
= 5 V; V
GG
= 5 V; R
G1
= 120 k
;
f= 50 MHz; f
unw
= 60 MHz; T
amb
= 25
C.
handbook, halfpage
0
gain reduction (dB)
10
50
16
12
4
0
8
20
30
40
MCD963
ID
(mA)
Fig.16 Drain current as a function of gain
reduction; typical values; see Fig.21.
V
DS
= 5 V; V
GG
= 5 V; R
G1
= 120 k
;
f = 50 MHz; T
amb
= 25
C.
2000 Mar 29
8
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
handbook, halfpage
MCD964
10
f (GHz)
Yis
(mS)
10
2
10
3
10
2
10
1
10
-
1
bis
gis
Fig.17 Input admittance as a function of frequency;
typical values.
V
DS
= 5 V; V
G2
= 4 V.
I
D
= 12 mA; T
amb
= 25
C.
handbook, halfpage
MCD965
10
f (MHz)
10
2
10
3
10
3
10
2
10
1
-
10
3
-
10
2
-
10
-
1
yrs
(
S)
rs
(deg)
rs
yrs
Fig.18 Reverse transfer admittance and phase as
a function of frequency; typical values.
V
DS
= 5 V; V
G2
= 4 V.
I
D
= 12 mA; T
amb
= 25
C.
handbook, halfpage
10
2
10
1
-
10
2
-
10
-
1
MCD966
10
10
2
10
3
f (MHz)
yfs
(mS)
fs
(deg)
yfs
fs
Fig.19 Forward transfer admittance and phase as
a function of frequency; typical values.
V
DS
= 5 V; V
G2
= 4 V.
I
D
= 12 mA; T
amb
= 25
C.
handbook, halfpage
MCD967
10
bos
f (MHz)
Yos
(mS)
10
2
10
3
10
1
10
-
2
10
-
1
gos
Fig.20 Output admittance as a function of
frequency; typical values.
V
DS
= 5 V; V
G2
= 4 V.
I
D
= 12 mA; T
amb
= 25
C.
2000 Mar 29
9
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
handbook, full pagewidth
DUT
C1
4.7 nF
R1
10 k
MGS315
C4
4.7 nF
L1
2.2
H
C3
4.7 nF
RL
50
VGG
VAGC
VDS
RGEN
50
VI
R2
50
4.7 nF
C2
RG1
Fig.21 Cross-modulation test set-up.
Table 1
Scattering parameters: V
DS
= 5 V; V
G2-S
= 4 V; I
D
= 12 mA; T
amb
= 25
C
Table 2
Noise data: V
DS
= 5 V; V
G2-S
= 4 V; I
D
= 12 mA; T
amb
= 25
C
f
(MHz)
s
11
s
21
s
12
s
22
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
MAGNITUDE
(ratio)
ANGLE
(deg)
50
0.988
-
3.26
2.989
176.2
0.0005
92.6
0.995
-
1.50
100
0.988
-
6.52
3.017
172.5
0.0009
88.0
0.995
-
3.01
200
0.984
-
12.99
2.990
165.0
0.0018
82.5
0.994
-
5.95
300
0.977
-
19.39
2.949
157.6
0.0027
78.2
0.992
-
8.86
400
0.965
-
25.65
2.913
150.3
0.0036
75.4
0.990
-
11.79
500
0.951
-
31.76
2.853
143.2
0.0039
71.8
0.988
-
14.65
600
0.936
-
37.68
2.793
136.3
0.0042
69.9
0.986
-
17.41
700
0.919
-
43.42
2.727
129.5
0.0044
68.9
0.984
-
20.10
800
0.903
-
48.94
2.664
123.0
0.0043
68.5
0.980
-
22.69
900
0.887
-
54.25
2.593
116.7
0.0041
70.7
0.975
-
25.27
1000
0.870
-
59.34
2.518
110.5
0.0038
72.4
0.970
-
27.90
f
(MHz)
F
min
(dB)
opt
R
n
(
)
(ratio)
(deg)
400
0.9
0.805
28.5
50
800
1.1
0.725
47.2
40
2000 Mar 29
10
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
PACKAGE OUTLINES
UNIT
A
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
1.1
0.9
A1
max
0.1
b1
0.88
0.78
c
0.15
0.09
D
3.0
2.8
E
1.4
1.2
HE
y
w
v
Q
2.5
2.1
0.45
0.15
0.55
0.45
e
1.9
e1
1.7
Lp
0.1
0.1
0.2
bp
0.48
0.38
DIMENSIONS (mm are the original dimensions)
SOT143B
97-02-28
0
1
2 mm
scale
Plastic surface mounted package; 4 leads
SOT143B
D
HE
E
A
B
v
M
A
X
A
A1
Lp
Q
detail X
c
y
w
M
e1
e
B
2
1
3
4
b1
bp
2000 Mar 29
11
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
UNIT
A
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
1.1
0.9
A1
max
0.1
b1
0.88
0.78
c
0.15
0.09
D
3.0
2.8
E
1.4
1.2
HE
y
w
v
Q
2.5
2.1
0.55
0.25
0.45
0.25
e
1.9
e1
1.7
Lp
0.1
0.1
0.2
bp
0.48
0.38
DIMENSIONS (mm are the original dimensions)
SOT143R
SC-61B
97-03-10
99-09-13
0
1
2 mm
scale
Plastic surface mounted package; reverse pinning; 4 leads
SOT143R
D
HE
E
A
B
v
M
A
X
A
A1
Lp
Q
detail X
c
y
w
M
e1
e
B
1
2
4
3
b1
bp
2000 Mar 29
12
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
SOT343R
D
A
A1
Lp
Q
detail X
c
HE
E
v
M
A
A
B
0
1
2 mm
scale
X
2
1
4
3
Plastic surface mounted package; reverse pinning; 4 leads
SOT343R
w
M
B
97-05-21
bp
UNIT
A1
max
bp
c
D
E
b1
HE
Lp
Q
w
v
mm
0.1
1.1
0.8
0.4
0.3
0.25
0.10
0.7
0.5
2.2
1.8
1.35
1.15
e
2.2
2.0
1.3
e1
0.2
y
0.1
0.2
1.15
DIMENSIONS (mm are the original dimensions)
0.45
0.15
0.23
0.13
e1
A
e
y
b1
2000 Mar 29
13
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
DATA SHEET STATUS
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
DATA SHEET STATUS
PRODUCT
STATUS
DEFINITIONS
(1)
Objective specification
Development
This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification
Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
DEFINITIONS
Short-form specification
The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition
Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications
These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
2000 Mar 29
14
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
NOTES
2000 Mar 29
15
Philips Semiconductors
Product specification
N-channel dual-gate PoLo MOS-FETs
BF1202; BF1202R;
BF1202WR
NOTES
Philips Electronics N.V.
SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Internet: http://www.semiconductors.philips.com
2000
69
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Printed in The Netherlands
603504/02/pp
16
Date of release:
2000 Mar 29
Document order number:
9397 750 06902