DATA SHEET
Product specification
Supersedes data of April 1993
File under Integrated Circuits, IC02
1996 Aug 26
INTEGRATED CIRCUITS
TDA8703
8-bit high-speed analog-to-digital
converter
1996 Aug 26
2
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital
converter
TDA8703
FEATURES
8-bit resolution
Sampling rate up to 40 MHz
High signal-to-noise ratio over a large analog input
frequency range (7.1 effective bits at 4.43 MHz
full-scale input)
Binary or two's complement 3-state TTL outputs
Overflow/underflow 3-state TTL output
TTL compatible digital inputs
Low-level AC clock input signal allowed
Internal reference voltage generator
Power dissipation only 290 mW (typical)
Low analog input capacitance, no buffer amplifier
required
No sample-and-hold circuit required.
APPLICATIONS
General purpose high-speed analog-to-digital
conversion
Digital TV, IDTV
Subscriber TV decoder
Satellite TV decoders
Digital VCR.
GENERAL DESCRIPTION
The TDA8703 is an 8-bit high-speed Analog-to-Digital
Converter (ADC) for video and other applications.
It converts the analog input signal into 8-bit binary-coded
digital words at a maximum sampling rate of 40 MHz.
All digital inputs and outputs are TTL compatible, although
a low-level AC clock input signal is allowed.
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TDA8703
DIP24
plastic dual in-line package; 24 leads (600 mil)
SOT101-1
TDA8703T
SO24
plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
1996 Aug 26
3
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
QUICK REFERENCE DATA
Notes
1. Full-scale sinewave (f
i
= 4.4 MHz; f
CLK
; f
CLK
= 27 MHz).
2. The
-
3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at input).
3. The circuit has two clock inputs CLK and CLK. There are four modes of operation:
a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the LOW-to-HIGH transition of the input clock signal.
b) TTL (mode 2); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the HIGH-to-LOW transition of the input clock signal.
c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V
(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the
clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition.
d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF
capacitor.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CCA
analog supply voltage
4.5
5.0
5.5
V
V
CCD
digital supply voltage
4.5
5.0
5.5
V
V
CCO
output stages supply voltage
4.2
5.0
5.5
V
I
CCA
analog supply current
-
28
36
mA
I
CCD
digital supply current
-
19
25
mA
I
CCO
output stages supply current
-
11
14
mA
ILE
DC integral linearity error
-
-
1
LSB
DLE
DC differential linearity error
-
-
1/2
LSB
AILE
AC integral linearity error
note 1
-
-
2
LSB
B
-
3 dB bandwidth
note 2; f
CLK
= 40 MHz
-
19.5
-
MHz
f
CLK
/f
CLK
maximum conversion rate
note 3
40
-
-
MHz
P
tot
total power dissipation
-
290
415
mW
1996 Aug 26
4
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
4
8
9
VI
VRB
VRT
19
18
17
16
CLK
CLK
VCCD
7
VCCA
23
15
13
24 D2
D3
D4
D5
D6
1
2
12
D1
D0
D7
TTL OUTPUTS
CLOCK DRIVER
TDA8703
TDA8703T
analog
voltage input
clock inputs
overflow /
underflow
output
data outputs
LSB
MSB
14
ANALOG - TO - DIGITAL
CONVERTER
LATCHES
MGA015
20
DGND
3
AGND
analog ground
digital ground
11
21
22
TC
CE
STABILIZER
TTL OUTPUT
OVERFLOW / UNDERFLOW
LATCH
V
CCO
5
DEC
1996 Aug 26
5
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDA8703
PINNING
SYMBOL PIN
DESCRIPTION
D1
1
data output; bit 1
D0
2
data output; bit 0 (LSB)
AGND
3
analog ground
V
RB
4
reference voltage bottom (decoupling)
DEC
5
decoupling input (internal stabilization
loop decoupling)
n.c.
6
not connected
V
CCA
7
positive supply voltage for analog
circuits (+5 V)
VI
8
analog voltage input
V
RT
9
reference voltage top (decoupling)
n.c.
10
not connected
O/UF
11
overflow/underflow data output
D7
12
data output; bit 7 (MSB)
D6
13
data output; bit 6
D5
14
data output; bit 5
D4
15
data output; bit 4
CLK
16
clock input
CLK
17
complementary clock input
V
CCD
18
positive supply voltage for digital
circuits (+5 V)
V
CCO
19
positive supply voltage for output
stages (+5 V)
DGND
20
digital ground
TC
21
input for two's complement output (TTL
level input, active LOW)
CE
22
chip enable input (TTL level input,
active LOW)
D3
23
data output; bit 3
D2
24
data output; bit 2
Fig.2 Pin configuration.
handbook, halfpage
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
TDA8703/
TDA8703T
MLB034
D1
D0
AGND
V RB
DEC
n.c.
V CCA
VI
VRT
n.c.
O/UF
D7
D6
D5
D4
CLK
VCCD
V CCO
DGND
D3
D2
CE
TC
CLK
PDF 
ZIP