June 1994

Philips Semiconductors

Product specification

Video analog input interface

TDA8708A

FEATURES

8-bit resolution

Sampling rate up to 32 MHz

Binary or two's complement 3-state TTL outputs

TTL-compatible digital inputs and outputs

Internal reference voltage regulator

Power dissipation of 365 mW (typical)

Input selector circuit (one out of three video inputs)

Clamp and Automatic Gain Control (AGC) functions for
CVBS and Y signals

No sample-and-hold circuit required.

The TDA8708A has white peak control in modes 1 and
2 whereas the TDA8708B has control in mode 1 only.

APPLICATIONS

Video signal decoding

Scrambled TV (encoding and decoding)

Digital picture processing

Frame grabbing.

GENERAL DESCRIPTION

The TDA8708A is an analog input interface for video signal
processing. It includes a video amplifier with clamp and
gain control, an 8-bit analog-to-digital converter (ADC)
with a sampling rate of 32 MHz and an input selector.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

CCA

analog supply voltage

4.5

5.0

5.5

CCD

digital supply voltage

4.5

5.0

5.5

CCO

TTL output supply voltage

4.2

5.0

5.5

CCA

analog supply current

CCD

digital supply current

CCO

TTL output supply current

ILE

DC integral linearity error

LSB

DLE

DC differential linearity error

0.5

LSB

clk(max)

maximum clock frequency

MHz

maximum

3 dB bandwidth (AGC amplifier)

MHz

tot

total power dissipation

365

500

TYPE NUMBER

PACKAGE

PINS

PIN POSITION

MATERIAL

CODE

TDA8708A

DIP

plastic

SOT117-1

TDA8708AT

SO28L

plastic

SOT136-1

June 1994

Philips Semiconductors

Product specification

Video analog input interface

TDA8708A

PINNING

SYMBOL

PIN

DESCRIPTION

data output; bit 7 (MSB)

data output; bit 6

data output; bit 5

data output; bit 4

CLK

clock input

CCD

digital supply voltage (+5 V)

CCO

TTL outputs supply voltage (+5 V)

DGND

digital ground

output format/chip enable
(3-state input)

data output; bit 3

data output; bit 2

data output; bit 1

data output; bit 0 (LSB)

video input selection bit 0

video input selection bit 1

VIN0

video input 0

VIN1

video input 1

VIN2

video input 2

ANOUT

analog voltage output

ADCIN

analog-to-digital converter input

DEC

decoupling input

CCA

analog supply voltage (+5 V)

AGND

analog ground

CLAMP

clamp capacitor connection

AGC

AGC capacitor connection

GATE B

black level synchronization pulse

GATE A

sync level synchronization pulse

RPEAK

peak level current resistor input

Fig.2 Pin configuration.

TDA8708A

CLK

VCCD

VCCO

DGND

ADCIN

ANOUT

VIN2

VIN1

VIN0

GATE B

AGC

CLAMP

AGND

VCCA

DEC

RPEAK

GATE A

MBB964

June 1994

Philips Semiconductors

Product specification

Video analog input interface

TDA8708A

FUNCTIONAL DESCRIPTION

The TDA8708A provides a simple interface for decoding
video signals.

The TDA8708A operates in configuration mode 1 (see
Fig.4) when the video signals are weak (i.e. when the gain
of the AGC amplifier has not yet reached its optimum
value). This enables a fast recovery of the synchronization
pulses in the decoder circuit. When the pulses at the
GATE A and GATE B inputs become distinct (GATE A and
GATE B pulses are synchronization pulses occurring
during the sync period and rear porch respectively) the
TDA8708A automatically switches to configuration mode 2
(see Fig.5).

When the TDA8708A is in configuration mode 1, the gain
of the AGC amplifier will be roughly adjusted (sync level to
a digital output level of 0 and the peak level to a digital
output level of 255).

In configuration mode 2 the digital output of the ADC is
compared to internal digital reference levels. The resultant
outputs control the charge or discharge current of a
capacitor connected to the AGC pin. The voltage across
this capacitor controls the gain of the video amplifier. This
is the gain control loop.

The sync level comparator is active during a positive-going
pulse at the GATE A input. This means that the sync pulse
of the composite video signal is used as an amplitude
reference. The bottom of the sync pulse is adjusted to
obtain a digital output of logic 0 at the converter output. As
the black level is at digital level 64, the sync pulse will have
a digital amplitude of 64 LSBs.

The peak-white control loop is always active. If the video
signal tends to exceed the digital code of 248, the gain will
be limited to avoid any over-range of the converter.

The use of nominal signals will prevent the output from
exceeding a digital code of 213 and the peak-white control
loop will be non-active.

The clamp level control is accomplished by using the same
techniques as used for the gain control. The black-level
digital comparator is active during a positive-going pulse at
the GATE B input. The clamp capacitor will be charged or
discharged to adjust the digital output to code 64.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

CCA

analog supply voltage

0.3

+7.0

CCD

digital supply voltage

0.3

+7.0

CCO

output supply voltage

0.3

+7.0

supply voltage difference between V

CCA

and V

CCD

1.0

+1.0

supply voltage difference between V

CCO

and V

CCD

1.0

+1.0

supply voltage difference between V

CCA

and V

CCO

1.0

+1.0

input voltage

0.3

CCA

output current

+10

stg

storage temperature

+150

amb

operating ambient temperature

+70

junction temperature

+125

SYMBOL

PARAMETER

VALUE

UNIT

th j-a

thermal resistance from junction to ambient in free air

SOT117-1

K/W

SOT136-1

K/W

June 1994

Philips Semiconductors

Product specification

Video analog input interface

TDA8708A

CHARACTERISTICS

CCA

= V

to V

= 4.5 to 5.5 V; V

CCD

= V

to V

= 4.5 to 5.5 V; V

CCO

= V

to V

= 4.2 to 5.5 V; AGND and DGND

shorted together; V

CCA

to V

CCD

0.5 to +0.5 V; V

CCO

to V

CCD

0.5 to +0.5 V; V

CCA

to V

CCO

0.5 to +0.5 V;

amb

= 0 to +70

C; typical readings taken at V

CCA

= V

CCD

= V

CCO

= 5 V and T

amb

= 25

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

CCA

analog supply voltage

4.5

5.0

5.5

CCD

digital supply voltage

4.5

5.0

5.5

CCO

TTL output supply voltage

4.2

5.0

5.5

CCA

analog supply current

CCD

digital supply current

CCO

TTL output supply current

TTL load (see Fig.8)

Video amplifier inputs

VIN(0

INPUTS

I(p-p)

input voltage (peak-to-peak value)

AGC load with external
capacitor; note 1

0.6

1.5

input impedance

= 6 MHz

input capacitance

= 6 MHz

AND

I1 TTL

INPUTS

(

SEE TABLE

LOW level input voltage

0.8

HIGH level input voltage

2.0

CCD

LOW level input current

= 0.4 V

400

HIGH level input current

= 2.7 V

GATE A

AND

GATE B TTL

INPUTS

(

SEE FIGS

AND

LOW level input voltage

0.8

HIGH level input voltage

2.0

CCD

LOW level input current

= 0.4 V

400

HIGH level input current

= 2.7 V

pulse width

see Fig.5

RPEAK

INPUT

(

28)

28(min)

minimum peak level current

= 0

150

AGC

INPUT

(

25)

25(min)

AGC voltage for minimum gain

2.8

25(max)

AGC voltage for maximum gain

4.0

AGC output current

see Table 2

CLAMP

INPUT

(

24)

clamp voltage for code 128 output

3.5

clamp output current

see Table 3

June 1994

Philips Semiconductors

Product specification

Video analog input interface

TDA8708A

Video amplifier outputs

ANOUT

OUTPUT

(

19)

19(p-p)

AC output voltage
(peak-to-peak value)

VIN

= 1.33 V (p-p);

= 3.6 V

1.33

internal current source

2.0

2.5

O(p-p)

output current driven by the load

ANOUT

= 1.33 V (p-p);

note 2

1.0

DC output voltage for black level

note 3

CCA

2.24

output impedance

Video amplifier dynamic characteristics

crosstalk between VIN inputs

CCA

= 4.75 to 5.25 V

diff

differential gain

VIN

= 1.33 V (p-p);

= 3.6 V

diff

differential phase

VIN

= 1.33 V (p-p);

= 3.6 V

0.8

deg

3 dB bandwidth

MHz

S/N

signal-to-noise ratio

note 4

SVRR1

supply voltage ripple rejection

note 5

gain range

see Fig.10

4.5

+6.0

stab

gain stability as a function of supply
voltage and temperature

see Fig.10

Analog-to-digital converter inputs

CLK

INPUT

(

LOW level input voltage

0.8

HIGH level input voltage

2.0

CCD

LOW level input current

clk

= 0.4 V

400

HIGH level input current

clk

= 2.7 V

100

input impedance

clk

= 10 MHz

input capacitance

clk

= 10 MHz

4.5

INPUT

(3-

STATE

;

SEE TABLE

LOW level input voltage

0.2

HIGH level input voltage

2.6

CCD

input voltage in high impedance state

1.15

LOW level input current

370

300

HIGH level input current

300

450

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

June 1994

Philips Semiconductors

Product specification

Video analog input interface

TDA8708A

ADCIN

INPUT

(

20;

SEE

ABLE

input voltage

digital output = 00

CCA

2.42

input voltage

digital output = 255

CCA

1.41

20(p-p)

input voltage amplitude
(peak-to-peak value)

1.0

input current

1.0

input impedance

= 6 MHz

input capacitance

= 6 MHz

Analog-to-digital converter outputs

IGITAL OUTPUTS

LOW level output voltage

= 2 mA

0.6

HIGH level output voltage

0.4 mA

2.4

CCD

output current in 3-state mode

0.4 V < V

< V

CCD

+20

Switching characteristics

clk(max)

maximum clock input frequency

see Fig.6; note 6

MHz

Analog signal processing (f

clk

= 32 MHz; see Fig.8)

diff

differential gain

= 1.0 V (p-p);

see Fig.3; note 7

diff

differential phase

see Fig.3; note 7

deg

fundamental harmonics (full-scale)

= 4.43 MHz; note 7

all

harmonics (full-scale);
all components

= 4.43 MHz; note 7

SVRR2

supply voltage ripple rejection

note 8

%/V

Transfer function (see Fig.8)

ILE

DC integral linearity error

LSB

DLE

DC differential linearity error

0.5

LSB

ILE

AC integral linearity error

note 9

LSB

Timing (f

clk

= 32 MHz; see Figs 6, 7 and 8)

IGITAL OUTPUTS

= 15 pF; I

= 2 mA; R

= 2 k

)

sampling delay time

output hold time

output delay time

dEZ

3-state delay time; output enable

dDZ

3-state delay time; output disable

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

June 1994

Philips Semiconductors

Product specification

Video analog input interface

TDA8708A

Notes

1. 0 dB is obtained at the AGC amplifier when applying V

i(p-p)

= 1.33 V.

2. The output current at pin 19 should not exceed 1 mA. The load impedance R

should be referenced to V

CCA

and

defined as:

a) AC impedance

1 k

and the DC impedance >2.7 k

b) The load impedance should be coupled directly to the output of the amplifier so that the DC voltage supplied by

the clamp is not disturbed.

3. Control mode 2 is selected.

4. Signal-to-noise ratio measured with 5 MHz bandwidth:

5. The voltage ratio is expressed as:

for V

= 1 V (p-p), gain at 100 kHz = 1 and 1 V supply variation.

6. It is recommended that the rise and fall times of the clock are

2 ns. In addition, a `good layout' for the digital and

analog grounds is recommended.

7. These measurements are realized on analog signals after a digital-to-analog conversion (TDA8702 is used).

8. The supply voltage rejection is the relative variation of the analog signal (full-scale signal at input) for 1 V of supply

variation:

9. Full-scale sine wave (f

= 4.4 MHz; f

clk

= 27 MHz).

S
N

----

20 log

ANOUTC p

(

)

ANOUTY (RMS noise)

-------------------------------------------------at B = 5 MHz.

SVRR1

20 log

CCA

------------------

--------

SVRR2

I 00

( )

I FF

(

)

(

)

I 00

( )

I FF

(

)

(

)

CCA

-----------------------------------------------------------------------------------------------------

June 1994

Philips Semiconductors

Product specification

Video analog input interface

TDA8708A

Table 1 Video input selection (CVBS).

Table 2 AGC output current.

Note

1. X = don't care.

2. Mode 2 can only be initialized with successive pulses

on GATE A and GATE B (see Fig.5).

SELECTED INPUT

VIN0

VIN1

VIN2

GATE A GATE B

DIGITAL

OUTPUT

AGC

MODE

(2)

output

255

2.5

output

255

AGCM

(1)

output

248

output

248

AGCM

output

+2.5

0 < output <
248

2.5

output > 248

AGCM

Table 3 CLAMP output current.

Note

1. X = don't care.

Table 4 OF input coding.

Note

1. Use C

10 pF to DGND.

GATE A GATE B

DIGITAL

OUTPUT

CLAMP

MODE

output

CLAMPM

output

2.5

(1)

output

+50

64 < output

D0 TO D7

active, two's complement

high impedance

open circuit

(1)

active, binary

Table 5 Output coding and input voltage (typical values).

STEP

ADCIN

BINARY OUTPUTS

TWO'S COMPLEMENT

Underflow

CCA

2.41 V

254

255

CCA

1.41 V

Overflow

June 1994

Philips Semiconductors

Product specification

Video analog input interface

TDA8708A

SOLDERING

Plastic dual in-line packages

Y DIP OR WAVE

The maximum permissible temperature of the solder is
260

C; this temperature must not be in contact with the

joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron below the seating plane
(or not more than 2 mm above it). If its temperature is
below 300

C, it must not be in contact for more than 10 s;

if between 300 and 400

C, for not more than 5 s.

Plastic small-outline packages

Y WAVE

During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150

C within 6 s.

Typical dwell time is 4 s at 250

A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.

Y SOLDER PASTE REFLOW

Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45

EPAIRING SOLDERED JOINTS

(

BY HAND

HELD SOLDERING

IRON OR PULSE

HEATED SOLDER TOOL

)

Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300

C. When using proper tools, all other pins can be

soldered in one operation within 2 to 5 s at between 270
and 320

C. (Pulse-heated soldering is not recommended

for SO packages.)

For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.

June 1994

Philips Semiconductors

Product specification

Video analog input interface

TDA8708A

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Semiconductors

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SCD31

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or contract, is believed to be accurate and reliable and may be changed without
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use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.

Printed in The Netherlands

533061/1500/05/pp24

Date of release: June 1994

Document order number:

9397 734 20011

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