1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

FEATURES

Triple 8-bit ADC

Sampling rate up to 100 MHz

IC controllable via a serial interface, which can be either
I

C-bus or 3-wire, selected via a TTL input pin

IC analog voltage input from 0.4 to 1.2 V (p-p) to
produce full-scale ADC input of 1 V (p-p)

3 clamps for programming a clamping code between

63.5 and +64 in steps of

LSB

3 controllable amplifiers: gain controlled via the serial
interface to produce a full scale resolution of

LSB

peak-to-peak

Amplifier bandwidth of 250 MHz

Low gain variation with temperature

PLL, controllable via the serial interface to generate the
ADC clock, which can be locked to a line frequency from
15 to 280 kHz

Integrated PLL divider

Programmable phase clock adjustment cells

Internal voltage regulators

TTL compatible digital inputs and outputs

Chip enable high-impedance ADC output

Power-down mode

Possibility to use up to four ICs in the same system,
using the I

C-bus interface, or more, using the 3-wire

serial interface

1 W power dissipation.

APPLICATIONS

R, G and B high-speed digitizing

LCD panels drive

LCD projection systems

VGA and higher resolutions

Using two ICs in parallel, higher display resolution can
be obtained; 200 MHz pixel frequency.

GENERAL DESCRIPTION

The TDA8752A is a triple 8-bit ADC with controllable
amplifiers and clamps for the digitizing of large bandwidth
RGB signals.

The clamp level, the gain and all of the other settings are
controlled via a serial interface (either I

C-bus or 3-wire

serial bus, selected via a logic input).

The IC also includes a PLL that can be locked on the
horizontal line frequency and generates the ADC clock.
The PLL jitter is minimized for high resolution PC graphics
applications. An external clock can also be input to the
ADC.

It is possible to set the TDA8752A serial bus address
between four fixed values, in the event that several
TDA8752A ICs are used in a system, using the I

C-bus

interface (for example, two ICs used in an odd/even
configuration).

ORDERING INFORMATION

TYPE NUMBER

PACKAGE

SAMPLING

FREQUENCY

(MHz)

NAME

DESCRIPTION

VERSION

TDA8752AH/6

QFP100

plastic quad flat package; 100 leads (lead length
1.95 mm); body 14

2.8 mm

SOT317-2

TDA8752AH/8

100

1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

CCA

analog supply voltage

for R, G and B channels

4.75

5.0

5.25

DDD

logic supply voltage

for I

C-bus and 3-wire

4.75

5.0

5.25

CCD

digital supply voltage

4.75

5.0

5.25

CCO

output stages supply voltage

for R, G and B channels

4.75

5.0

5.25

CCA(PLL)

analog PLL supply voltage

4.75

5.0

5.25

CCO(PLL)

output PLL supply voltage

4.75

5.0

5.25

CCA

analog supply current

120

DDD

logic supply current

for I

C-bus and 3-wire

1.0

CCD

digital supply current

CCO

output stages supply current

CLK

= 100 MHz;

ramp input

CCA(PLL)

analog PLL supply current

CCO(PLL)

output PLL supply current

CLK

maximum clock frequency

TDA8752A/6

MHz

TDA8752A/8

100

MHz

ref(PLL)

PLL reference clock frequency

280

kHz

VCO

VCO output clock frequency

100

MHz

INL

DC integral non linearity

from analog input to
digital output; full-scale;
ramp input;
f

CLK

= 100 MHz

0.5

1.5

LSB

DNL

DC differential non linearity

from analog input to
digital output; full-scale;
ramp input;
f

CLK

= 100 MHz

0.5

1.0

LSB

amp

amplifier gain stability as a function of
temperature

ref

= 2.5 V with

100 ppm/

C maximum

200

ppm/

amplifier bandwidth

3 dB; T

amb

= 25

250

MHz

set

settling time of the ADC block plus AGC

input signal settling
time < 1 ns; T

amb

= 25

PLL

PLL divider ratio

100

4095

tot

total power consumption

CLK

= 100 MHz;

ramp input

1.0

PLL(rms)

maximum PLL phase jitter (RMS value)

ref

= 66.67 kHz;

CLK

= 100 MHz

0.3

1999

Feb

Philips Semiconductors

Product specification

riple high-speed Analog-to-Digital

Converter (ADC)

TDA8752A

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BLOCK DIAGRAM

book, full pagewidth

FCE079

SERIAL

INTERFACE

C-BUS

3-WIRE

C/3W

C-bus; 1-bit

(H level)

REGULATOR

PLL

PWDWN

CKREF

COAST

INV

CKEXT

CKREFO

CKAO

CKBO

CKADCO

B0 to B7

BOR

R0 to R7

G0 to G7

BBOT

BCLP

RBOT

RCLP

GBOT

GCLP

DEC2

DEC1

HSYNC

n.c.

HSYNCI

ADD2

BIN

BGAINC

BAGC

GAGC

Vref

RDEC

RIN

RGAINC

RAGC

GDEC

GIN

GGAINC

BDEC

ADD1

SEN

SCL

SDA

DIS

BLUE CHANNEL

GREEN CHANNEL

TDA8752A

RED CHANNEL

ADC

GOR

ROR

MUX

CLAMP

OUTPUTS

VCCAR

VCCAG

VCCAB

VDDD

AGNDG

VCCOG

VCCOB

VCCOR

VCCD

VCCA(PLL)

VCCO(PLL)

CLP

AGNDR

VSSD

AGNDB

OGNDG

OGNDR

AGNDPLL

OGNDB

DGND

OGNDPLL

TDO

TCK

1, 5, 30, 31, 43 , 44
50, 51, 100

71 to 78

61 to 68

49, 52 to 58

Fig.1 Block diagram.

1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

PINNING

SYMBOL

PIN

DESCRIPTION

n.c.

not connected

DEC2

main regulator decoupling input

ref

gain stabilizer voltage reference input

DEC1

main regulator decoupling input

n.c.

not connected

RAGC

red channel AGC output

RBOT

red channel ladder decoupling input (BOT)

RGAINC

red channel gain capacitor input

RCLP

red channel gain clamp capacitor input

RDEC

red channel gain regulator decoupling input

CCAR

red channel gain analog power supply

RIN

red channel gain analog input

AGNDR

red channel gain analog ground

GAGC

green channel AGC output

GBOT

green channel ladder decoupling input (BOT)

GGAINC

green channel gain capacitor input

GCLP

green channel gain clamp capacitor input

GDEC

green channel gain regulator decoupling input

CCAG

green channel gain analog power supply

GIN

green channel gain analog input

AGNDG

green channel gain analog ground

BAGC

blue channel AGC output

BBOT

blue channel ladder decoupling input (BOT)

BGAINC

blue channel gain capacitor input

BCLP

blue channel gain clamp capacitor input

BDEC

blue channel gain regulator decoupling input

CCAB

blue channel gain analog power supply

BIN

blue channel gain analog input

AGNDB

blue channel gain analog ground

n.c.

not connected

n.c.

not connected

C/3W

selection input between I

C-bus (active HIGH) and 3-wire serial bus (active LOW)

ADD1

C-bus address control input 1

ADD2

C-bus address control input 2

TCK

scan test mode (active HIGH)

1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

TDO

scan test output

DIS

C-bus and 3-wire disable control input (disable at HIGH level)

SEN

select enable for 3-wire serial bus input (see Fig.10)

SDA

C-bus/3 W serial data input

DDD

logic I

C-bus/3 W digital power supply

SSD

logic I

C-bus/3 W digital ground

SCL

C-bus/3 W serial clock input

n.c.

not connected

n.c.

not connected

ROR

red channel ADC output bit out of range

GOR

green channel ADC output bit out of range

BOR

blue channel ADC output bit out of range

OGNDB

blue channel ADC output ground

blue channel ADC output bit 0 (LSB)

n.c.

not connected

n.c.

not connected

blue channel ADC output bit 1

blue channel ADC output bit 2

blue channel ADC output bit 3

blue channel ADC output bit 4

blue channel ADC output bit 5

blue channel ADC output bit 6

blue channel ADC output bit 7 (MSB)

CCOB

blue channel ADC output power supply

OGNDG

green channel ADC output ground

green channel ADC output bit 0 (LSB)

green channel ADC output bit 1

green channel ADC output bit 2

green channel ADC output bit 3

green channel ADC output bit 4

green channel ADC output bit 5

green channel ADC output bit 6

green channel ADC output bit 7 (MSB)

CCOG

green channel ADC output power supply

OGNDR

red channel ADC output ground

red channel ADC output bit 0 (LSB)

SYMBOL

PIN

DESCRIPTION

1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

red channel ADC output bit 1

red channel ADC output bit 2

red channel ADC output bit 3

red channel ADC output bit 4

red channel ADC output bit 5

red channel ADC output bit 6

red channel ADC output bit 7 (MSB)

CCOR

red channel ADC output power supply

CKREFO

reference output clock resynchronized horizontal pulse

CKAO

PLL clock output 3 (in phase with reference output clock)

OGNDPLL

PLL digital ground

CKBO

PLL clock output 2

CKADCO

PLL clock output 1 (in phase with internal ADC clock)

CCO(PLL)

PLL output power supply

DGND

digital ground

output enable not (when OE is HIGH, the outputs are in high-impedance)

PWDWN

power-down control input (IC is in power-down mode when this pin is HIGH)

CLP

clamp pulse input (clamp active HIGH)

HSYNC

horizontal synchronization input pulse

INV

PLL clock output inverter command input (invert when HIGH)

CKEXT

external clock input

COAST

PLL coast command input

CKREF

PLL reference clock input

CCD

digital power supply

AGNDPLL

PLL analog ground

PLL filter input

CCAPLL

PLL analog power supply

n.c.

100

not connected

SYMBOL

PIN

DESCRIPTION

1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

FUNCTIONAL DESCRIPTION

This triple high-speed 8-bit ADC is designed to convert
RGB signals, from a PC or work station, into data used by
a LCD driver (pixel clock up to 200 MHz, using 2 ICs).

IC analog video inputs

The video inputs are internally DC polarized. These inputs
are AC coupled externally.

Clamps

Three independent parallel clamping circuits are used to
clamp the video input signals on the black level and to
control the brightness level. The clamping code is
programmable between code

63.5 and +64 in steps of

LSB. The programming of the clamp value is achieved

via an 8-bit DAC. Each clamp must be able to correct an
offset from

0.1 V to

10 mV within 300 ns, and correct the

total offset in 10 lines.

The clamps are controlled by an external TTL positive
going pulse (pin CLP). The drop of the video signal is
<1 LSB.

Normally, the circuit operates with a 0 code clamp,
corresponding to the 0 ADC code. This clamp code can be
changed from

63.5 to +64 as represented in Fig.7, in

steps of

LSB. The digitized video signal is always

between code 0 and code 255 of the ADC.

Variable gain amplifier

Three independent variable gain amplifiers are used to
provide, to each channel, a full-scale input range signal to
the 8-bit ADC. The gain adjustment range is designed so
that, for an input range varying from 0.4 to 1.2 V (p-p), the
output signal corresponds to the ADC full-scale input of
1 V (p-p).

To ensure that the gain does not vary over the whole
operating temperature range, an external reference of
2.5 V DC, (V

ref

with a 100 ppm/

C maximum variation)

supplied externally, is used to calibrate the gain at the
beginning of each video line before the clamp pulse using
the following principle.

A differential of 0.156 V (p-p) (

ref

) reference signal is

generated internally from the reference voltage (V

ref

During the synchronization part of the video line, the
multiplexer, controlled by the TTL synchronization signal
(HSYNCI, coming from HSYNC; see Fig.1) with a width
equal to one of the video synchronization signals
(e.g. signal coming from a synchronization separator), is
switched between the two amplifiers.

The output of the multiplexer is either the normal video
signal or the 0.156 V reference signal (during HSYNC).

The corresponding ADC outputs are then compared to a
pre-set value loaded in a register. Depending on the result
of the comparison, the gain of the variable gain amplifiers
is adjusted (coarse gain control; see Figs 2 and 8).
The three 7-bit registers receive data via a serial interface
to enable the gain to be programmed.

The pre-set value loaded in the 7-bit register is chosen
between approximately 67 codes to ensure the full-scale
input range (see Fig.8). A contrast control can be achieved
using these registers. In this case care should be taken to
stay within the allowed code range (32 to 99).

A fine correction using three 5-bit DACs, also controlled via
the serial interface, is used to finely tune the gain of the
three channels (fine gain control; see Figs 2 and 9) and to
compensate the channel-to-channel gain mismatch.

With a full scale ADC input, the resolution of the fine
register corresponds to

LSB peak-to-peak variation.

To use these gain controls correctly, it is recommended to
fix the coarse gain (to have a full-scale ADC input signal)
to within 4 LSB and then adjust it with the fine gain.
The gain is adjusted during HSYNC. During this time the
output signal is not related to the amplified input signal.
The outputs, when the coarse gain system is stable, are
related to the programmed coarse code (see Fig.8).

ADCs

The ADCs are 8-bit with a maximum clock frequency of
100 Msps. The ADCs input range is 1 V (p-p) full-scale.
One out of range bit exists per channel (ROR, GOR and
BOR). It will be at logic 1 when the signal is out of range
the full scale of the ADCs.

Pipeline delay in the ADCs is 1 clock cycle from sampling
to data output.

The ADCs reference ladders regulators are integrated.

ADC outputs

ADC outputs are straight binary. An output enable pin
(OE; active LOW) enables the output status between
active and high-impedance (OE = HIGH) to be switched;
it is recommended to load the outputs with a 10 pF
capacitive load. The timing must be checked very carefully
if the capacitive load is more than 10 pF.

1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

Phase-locked loop

The ADCs are clocked either by an internal PLL locked to
the CKREF clock, (all of the PLL is on-chip except the loop
filter capacitance) or an external clock, CKEXT. Selection
is performed via the serial interface bus.

The reference clock (CKREF) range is between
15 and 280 kHz. Consequently, the VCO minimum
frequency is 12 MHz and the maximum frequency
100 MHz for the TDA8752A/8 and 60 MHz for the
TDA8752A/6. The gain of the VCO part can be controlled
via the serial interface, depending on the frequency range
to which the PLL is locked.

To increase the bandwidth of the PLL, the charge pump
current, controlled by the serial interface, must also be
increased. The relationship between the frequency and
the current is given by the following equation:

Where:

= the natural PLL frequency

= the VCO gain

N = the division number

and C

= capacitors of the PLL filter.

The other PLL equation is as follows:

Where:

= loop filter zero frequency

R = the chosen resistance for the filter

= the damping factor.

Different resistances for the filter can be programmed via
the serial interface. To have better performances, the PLL
parameters should be chosen so that:

ref

0.05

1.5.

It is possible to control (independently) the phase of the
ADC clock and the phase of an additional clock output
(which could be used to drive a second TDA8752A).
For this, two serial interface-controlled digital phase-shift
controllers are included (controlled by 5-bit registers,
phase shift controller steps are 11.25

each on the whole

PLL frequency range).

-------

(

)

-----------------------------------

------------------------------ and

1
2

---

----

CKREF is resynchronized, by the synchro block, on the
CKAO clock. The output is CKREFO (LOW during 8 clock
periods). CKAO is the clock at the output of the phase
selector A. This clock can be used as the clocks for CKBO
and CKADCO. The timing is given in Fig.5.

The COAST pin is used to disconnect the PLL phase
frequency detector during the frame flyback or the
unavailability of the CKREF signal. This signal can
normally be derived from the VSYNC signal.

The clock output is able to drive an external 10 pF load
(for the on-chip ADCs).

The PLL can be used in three different methods:

1. The IC can be used as stand-alone with a sampling

frequency of up to 100 MHz for the TDA8752A/8 and
up to 60 MHz for the TDA8752A/6.

2. When an RGB signal is at a pixel frequency exceeding

100 to 200 MHz, it is possible to follow one of the two
possibilities given below:

a) Using one TDA8752A; the sampling rate can be

reduced by a factor of two, by sampling the even
pixels in the even frame and the odd pixels in the
odd frame. The INV pin is used to toggle between
frames.

b) Using two TDA8752As the PLL of the master

TDA8752A is used to drive both ADC clocks.
The PLL of the slave TDA8752A is disconnected
and the CKBO of the master TDA8752A is
connected to pin CKEXT of both TDA8752A.

The master TDA8752A is used to sample the even
pixels and the slave TDA8752A for odd pixels,
using a 180

phase shift between the clocks

(CKADCO pins). The master chip has its INV pin
LOW while the slave chip has its INV pin HIGH,
which guarantees the 180

shift ADC clock drive.

It is then necessary to adjust phase B of the master
chip. Special care should be taken with the quality
of the input signal (input setting time).

If CKREFO output signal at the master chip is
needed, it is possible to use one of the two phase A
values in order to avoid set-up and hold problems
in the SYNCHRO function; e.g.
PHASEA = 100000 and PHASEA = 111111.

1999

Feb

Philips Semiconductors

Product specification

riple high-speed Analog-to-Digital

Converter (ADC)

TDA8752A

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C-BUS AND 3-WIRE INTERFACES

Register definitions

The configuration of the different registers is shown in Table 1.

Table 1

C-bus and 3-wire registers

All the registers are defined by a subaddress of 8 bits; bit A4 refers to the mode which is used with the I

C-bus interface; bits Sa3 to Sa0 are the

subaddresses of each register.

The bit mode, used only with the I

C-bus, enables two modes to be programmed:

If Mode = 0, each register is programmed independently by giving its subaddress and its content

If Mode = 1, all the registers are programmed one after the other by giving this initial condition (xxx1 1111) as the subaddress state; thus, the registers
are charged following the predefined sequence of 16 bytes (from subaddress 0000 to 1101).

FUNCTION

NAME

SUB-ADDRESS

BIT DEFINITION

DEFAULT

VALUE

MSB

LSB

SUBADDR

Mode

Sa3

Sa2

Sa1

Sa0

xxx1 0000

OFFSETR

Or7

Or6

Or5

Or4

Or3

Or2

Or1

Or0

0111 1111

COARSER

Cr6

Cr5

Cr4

Cr3

Cr2

Cr1

Cr0

x010 0000

FINER

Fr4

Fr3

Fr2

Fr1

Fr0

xxx0 0000

OFFSETG

Og7

Og6

Og5

Og4

Og3

Og2

Og1

Og0

0111 1111

COARSEG

Cg6

Cg5

Cg4

Cg3

Cg2

Cg1

Cg0

x010 0000

FINEG

Fg4

Fg3

Fg2

Fg1

Fg0

xxx0 0000

OFFSETB

Ob7

Ob6

Ob5

Ob4

Ob3

Ob2

Ob1

Ob0

0111 1111

COARSEB

Cb6

Cb5

Cb4

Cb3

Cb2

Cb1

Cb0

x010 0000

FINEB

Fb4

Fb3

Fb2

Fb1

Fb0

xxx0 0000

CONTROL

V level

H level

edge

Ip2

Ip1

Ip0

0000 0100

VCO

Vco1

Vco0

Di11

Di10

Di9

0110 0001

DIVIDER
(LSB)

Di8

Di7

Di6

Di5

Di4

Di3

Di2

Di1

1001 0000

PHASEA

Di0

Cka

Pa4

Pa3

Pa2

Pa1

Pa0

x000 0000

PHASEB

Ckb

Pb4

Pb3

Pb2

Pb1

Pb0

xx00 0000

1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

FFSET REGISTER

This register controls the clamp level for the
RGB channels. The relationship between the
programming code and the level of the clamp code is given
in Table 2.

Table 2

Coding

The default programmed value is:

Programmed code = 127

Clamp code = 0

ADC output = 0.

OARSE AND FINE REGISTERS

These two registers enable the gain control, the AGC gain
with the coarse register and the reference voltage with the
fine register. The coarse register programming equation is
as follows:

Where: V

ref

= 2.5 V.

The gain correspondence is given in Table 3. The gain is
linear with reference to the programming code (N

FINE

= 0).

PROGRAMMED

CODE

CLAMP CODE

ADC OUTPUT

63.5

underflow

62.5

127

254

63.5

63 or 64

255

GAIN

COARSE

ref

FINE

-------------------

----------------------------------------------

------

COARSE

ref

512

FINE

(

)

-------------------------------------------------

Table 3

Gain correspondence (COARSE)

The default programmed value is as follows:

COARSE

= 32

Gain = 0.825

to be full-scale = 1.212.

To modulate this gain, the fine register is programmed
using the above equation. With a full-scale ADC input, the
fine register resolution is a

LSB peak-to-peak

(see Table 4 for N

COARSE

= 32).

Table 4

Gain correspondence (FINE)

The default programmed value is: N

FINE

= 0.

ONTROL REGISTER

COAST and HSYNC signals can be inverted by setting the
I

C-bus control bits V level and H level respectively. When

V level and H level are set to zero respectively, COAST
and HSYNC are active HIGH.

The bit `edge' defines the rising or falling edge of CKREF
to synchronise the PLL. It will be on the rising edge if the
bit is at logic 0 and on the falling edge if the bit is at logic 1.

The bits Up and Do are used for the test, to force the
charge pump current. These bits have to be logic 0 during
normal use.

The bits Ip0, Ip1 and Ip2 control the charge pump current,
to increase the bandwidth of the PLL, as shown in Table 5.

COARSE

GAIN

TO BE

FULL-SCALE

0.825

1.212

2.5

0.4

FINE

GAIN

TO BE

FULL-SCALE

0.825

1.212

0.878

1.139

1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

Table 5

Charge-pump current control

The default programmed value is as follows:

Charge pump current = 100

Test bits: no test mode; bits Up and Do at logic 0

Rising edge of CKREF: bit edge at logic 0

COAST and HSYNC inputs are active HIGH: V level and
H level at logic 0.

VCO

The bits Z2, Z1 and Z0 enable the internal resistance for
the VCO filter to be selected.

Table 6

VCO register bits

Ip2

Ip1

Ip0

CURRENT

(

6.25

12.5

100

200

400

700

RESISTANCE

)

high impedance

128

Table 7

VCO gain control

The bits V

CO1

and V

CO0

control the VCO gain.

The default programmed value is as follows:

Internal resistance = 16 k

VCO gain = 15 MHz/V.

IVIDER REGISTER

This register controls the PLL frequency. The bits are the
LSB bits.

The default programmed value is 0011 0010 0000 = 800.

The MSB bits (Di11, Di10 and Di9) and the LSB bit (Di0)
have to be programmed before the bits Di8 to Di1 to have
the required divider ratio. The bit Di0 is used for the parity
divider number = Di0 = 0 = even number Di0 = 1 = odd
number. It should be noted that if the I

C-bus programming

is done in mode = 1 and the bit Di0 has to be toggled, then
the registers have to be loaded twice to have the update
divider ratio.

OWER

DOWN MODE

When the supply is completely switched off, the
registers are set to their default values; in that event they
have to be reprogrammed if the required settings are
different (e.g. through an EEPROM)

When the device is in power-down mode, the previously
programmed register values remain unaffected.

PHASEA

AND

PHASEB

REGISTERS

The bit Cka is logic 0 when the used clock is the PLL clock,
and logic 1 when the used clock is the external clock.

The bit Ckb is logic 0 when the second clock is not used.

The bits Pa4 to Pa0 and Pb4 to Pb0 are used to program
the phase shift for the clock, CKADCO, CKAO and CKBO
(see Table 8).

CO1

CO0

VCO gain

(MHz/V)

PIXEL CLOCK

FREQUENCY

RANGE (MHz)

10 to 17

17 to 35

35 to 60

100

60 to 100

1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

Table 8

Phase registers bits

The default programmed value is as follows:

No external clock: CKA at logic 0

No use of the second clock: CKB at logic 0

Phase shift for CKAO and CKADCO = 0

Phase shift for CKBO = 0

C-bus protocol

Table 9

C-bus address

The I

C-bus address of the circuit is 10011 xx0.

Bits A2 and A1 are fixed by the potential on pins ADD1 and ADD2. Thus, four TDA8752As can be used on the same
system, using the addresses for ADD1 and ADD2 with the I

C-bus. The A0 bit must always be equal to logic 0 because

it is not possible to read the data in the register. The timing and protocol for the I

C-bus are standard. Two sequences

are available, see Tables 10 and 11.

Table 10 Address sequence for mode 0; note 1

Note

1. Where: S = START condition, ACK = acknowledge and P = STOP condition.

Table 11 Address sequence for mode 1; note 1

Note

1. Where: S = START condition, ACK = acknowledge and P = STOP condition.

Pa4 AND Pb4

Pa3 AND Pb3

Pa2 AND Pb2

Pa1 AND Pb1

Pa0 AND Pb0

PHASE SHIFT (

)

11.25

337.5

348.75

ADD2

ADD1

IC ADDRESS

ACK

SUBADDRESS

REGISTER1

ACK

DATA

REGISTER1

(see Table 1)

ACK

SUBADDRESS

REGISTER2

ACK

IC ADDRESS

ACK

SUBADDRESS

xxx1 1111

ACK

DATA

REGISTER1

(see Table 1)

ACK

DATA

REGISTER2

ACK

1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

THERMAL CHARACTERISTICS

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

CCA

analog supply voltage

0.3

+7.0

CCD

digital supply voltage

0.3

+7.0

DDD

logic input voltage

0.3

+7.0

CCO

output stages supply voltage

0.3

+7.0

supply voltage differences

CCA

CCD

1.0

+1.0

CCO

CCD

; V

CCO

DDD

1.0

+1.0

CCA

DDD

; V

CCD

DDD

1.0

+1.0

CCA

CCO

1.0

+1.0

i(RGB)

RGB input voltage range

referenced to AGND

0.3

+7.0

output current

stg

storage temperature

+150

amb

operating ambient temperature

junction temperature

150

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th(j-a)

thermal resistance from junction to ambient

in free air

K/W

1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

CHARACTERISTICS

CCA

= V11 (or V19, V27 or V99) referenced to AGND (V13, V21, V29 or V96 = 4.75 to 5.25 V; V

CCD

= V95 referenced

to DGND (V86) = 4.75 to 5.25 V; V

DDD

= V40 referenced to V

SSD

(V41) = 4.75 to 5.25 V; V

CCO

= V59

(or V69, V79 or V85) referenced to OGND (V48, V60, V70 or V82) = 4.75 to 5.25 V; AGND, DGND, OGND and V

SSD

short circuited together. T

amb

= 0 to 70

C; typical values measured at V

CCA

= V

DDD

= V

CCD

= V

CCO

= 5 V and

amb

= 25

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

CCA

analog supply voltage

4.75

5.0

5.25

CCD

digital supply voltage

4.75

5.0

5.25

DDD

logic supply voltage

4.75

5.0

5.25

CCO

output stages supply voltage

4.75

5.0

5.25

CCA

analog supply current

120

DDD

logic supply current for
I

C-bus and 3-wire

1.0

CCD

digital supply current

CCO

output stages supply current

ramp input; f

CLK

= 100 MHz

CCO(PLL)

output PLL supply current

CCA(PLL)

analog PLL supply current

supply voltage differences

CCA

CCD

0.25

+0.25

CCO

CCD

; V

CCO

DDD

0.25

+0.25

CCA

DDD

; V

CCD

DDD

0.25

+0.25

CCA

CCO

0.25

+0.25

tot

total power consumption

ramp input; f

CLK

= 100 MHz

1.0

power consumption in
power-down mode

R, G and B amplifiers

bandwidth

3 dB; T

amb

= 25

250

MHz

set

settling time of the block ADC
plus AGC

full-scale (black-to-white)
transition; input signal
settling time < 1 ns;
1 to 99%; T

amb

= 25

4.5

NCOARSE

coarse gain range

ref

= 2.5 V; minimum

coarse gain register;
code = 32; (see Fig.8)

1.67

maximum coarse gain
register; code = 99;
(see Fig.8)

1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

FINE

fine gain correction range

fine register input code = 0;
(see Fig.9)

fine register input
code = 31; (see Fig.9)

0.5

amp

amplifier gain stability as a
function of temperature

ref

= 2.5 V with

100 ppm/

C maximum

variation

200

ppm/

gain current

stab

amplifier gain adjustment
speed

HSYNC active; capacitors
on pins 8, 16 and 24 = 22 nF

mdB/

i(p-p)

input voltage range
(peak-to-peak value)

corresponding to full-scale
output

0.4

1.2

r(Vi)

input voltage rise time

= 100 MHz; square wave

2.5

f(Vi)

input voltage fall time

= 100 MHz; square wave

2.5

E(rms)

channel-to-channel gain
matching (RMS value)

maximum coarse gain;
T

amb

= 25

minimum coarse gain;
T

amb

= 25

Clamps

CLP

precision

black level noise on RGB
channels = 10 mV (max.)
(RMS value); T

amb

= 25

LSB

COR1

clamp correction time to within

10 mV

100 mV black level input

variation; clamp
capacitor = 4.7 nF

300

COR2

clamp correction time to less
than 1 LSB

100 mV black level input

variation; clamp
capacitor = 4.7 nF

lines

W(CLP)

clamp pulse width

500

2000

CLP

channel-to-channel clamp
matching

LSB

off

code clamp reference

clamp register input
code = 0

63.5

LSB

clamp register input
code = 255

LSB

Phase-locked loop

PLL(rms)

long term PLL jitter
(RMS value)

CLK

= 60 MHz; see Table 13

450

CLK

= 100 MHz;

see Table 13

360

divider ratio

100

4095

ref

reference clock frequency
range

280

kHz

PLL

output clock frequency range

100

MHz

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

COAST(max)

maximum coast mode time

lines

recap

PLL recapture time

when coast mode is aborted

lines

cap

PLL capture time

in start-up conditions

step

phase shift step

amb

= 25

11.25

deg

ADCs

maximum sampling frequency

TDA8752A/6

MHz

TDA8752A/8

100

MHz

INL

DC integral non linearity

from IC analog input to
digital output; ramp input;
f

CLK

= 100 MHz

0.5

1.5

LSB

DNL

DC differential non linearity

from IC analog input to
digital output; ramp input;
f

CLK

= 100 MHz

0.5

1.0

LSB

ENOB

effective number of bits

from IC analog input to
digital output; 10 kHz sine
wave input; ramp input;
f

CLK

= 100 MHz; note 1

7.4

bits

Signal-to-noise ratio

S/N

signal-to-noise ratio

maximum gain;
f

CLK

= 100 MHz

minimum gain;
f

CLK

= 100 MHz

Spurious free dynamic range

SFDR

spurious free dynamic range

maximum gain;
f

CLK

= 100 MHz

minimum gain;
f

CLK

= 100 MHz

Clock timing output (CKADCO, CKBO and CKAO)

ext

ADC clock duty cycle

100 MHz output

CLK(max)

maximum clock frequency

100

MHz

Clock timing input (CKEXT)

CLK(max)

maximum clock frequency

100

MHz

CPH

clock pulse width HIGH

3.6

CPL

clock pulse width LOW

4.5

d(CLKO)

delay from CKEXT to
CKADCO

INV set to LOW

13.6

14.7

15.2

INV set to HIGH

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

14.7

CLK

-----------

1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

t-t

d(CLKO

)

between samples operated in
the same supply and
temperature conditions

0.1

0.3

Data timing (see Fig.11); f

CLK

= 100 MHz; C

= 10 pF; note 2

d(s)

sampling delay time

referenced to CKADCO

d(o)

output delay time

3.3

2.6

h(o)

output hold time

4.6

5.5

3-state output delay time; (see Fig.12)

dZH

output enable HIGH

dZL

output enable LOW

dHZ

output disable HIGH

dLZ

output disable LOW

PLL clock output

LOW-level output voltage

= 1 mA

0.3

0.8

HIGH-level output voltage

1 mA

2.4

3.5

LOW-level output current

= 0.4 V

HIGH-level output current

= 2.7 V

0.4

ADC data outputs

LOW-level output voltage

= 1 mA

0.8

HIGH-level output voltage

1 mA

2.4

CCD

LOW-level output current

= 0.4 V

HIGH-level output current

= 2.7 V

0.4

TTL digital inputs (CKREF, COAST, CKEXT, INV, HSYNC and CLP)

LOW-level input voltage

0.8

HIGH-level input voltage

2.0

LOW-level input current

= 0.4 V

400

HIGH-level input current

= 2.7 V

100

input impedance

input capacitance

4.5

3-wire serial bus

rst

reset time of the chip before
3-wire communication

600

data set-up time

100

data hold time

100

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

Notes

1. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent

fundamental period. The calculation takes into account all harmonics and noise up to half clock frequency (NYQUIST
frequency). Conversion-to-noise ratio: S/N = EB

6.02 + 1.76 dB.

2. Output data acquisition is available after the maximum delay time t

d(o)

, which is the time during which the data is

available. All the timings are given for a 10 pF capacitive load. A higher load can be used but the timing must then
be rechecked.

3. The I

C-bus timings are given for a frequency of 100 kbit/s (100 kHz). This bus can be used at a frequency of

400 kbit/s (400 kHz).

C-bus; see note 3

SCL

clock frequency

100

kHz

BUF

time the bus must be free
before new transmission can
start

4.7

HD;STA

start condition hold time

4.0

SU;STA

start condition set-up time

repeated start

4.7

CKL

LOW-level clock period

4.7

CKH

HIGH-level clock period

4.0

SU;DAT

data set-up time

250

HD;DAT

data hold time

SDA and SCL rise time

for f

SCL

= 100 kHz

1.0

SDA and SCL fall time

for f

SCL

= 100 kHz

300

SU;STOP

stop condition set-up time

4.0

L(bus)

capacitive load for each bus
line

400

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Fig.11 Timing diagram.

handbook, full pagewidth

td(s)

sample N

CKADCO

MGL103

sample N

50 % = 1.4 V

1.4 V

2.4 V

0.4 V

VlN

DATA
R0 to R7, ROR
G0 to G7, GOR
B0 to B7, BOR

td(o)

th(o)

tCPH

tCPL

1999

Feb

Philips Semiconductors

Product specification

riple high-speed Analog-to-Digital

Converter (ADC)

TDA8752A

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Table 13 Examples of PLL settings and performance; note 1

Notes

1. Values measured at V

CCA

= V

DDD

= V

CCD

= V

CCO

= 5 V and T

amb

= 25

2. PLL long-term time jitter is measured at the end of the video line, where it is at its maximum.

3. Measured between 0 and 70

VIDEO

STANDARDS

ref

(kHz)

CLK

(MHz)

(MHz/V)

(nF)

(

)

LONG TIME JITTER

(2)

PLL PHASE DRIFT

(3)

(ns)

ps (RMS)

ns (p-p)

CGA: 640

200

15.75

14.3

912

150

200

1.2

VGA: 640

480

31.5

25.2

800

150

400

610

3.6

0.7

VESA: 800

600

48.08

1040

150

700

480

2.9

0.55

VESA: 1024

768

60.02

78.8

1312

100

150

700

380

2.3

0.3

SUN: 1152

900

66.67

100

1500

100

150

700

360

2.2

0.3

1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

APPLICATION INFORMATION

Fig.13 Application diagram.

All supply pins have to be decoupled, with two capacitors:
one for high frequencies (approximately 1 nF) and one for the low frequencies (approximately 100 nF or higher).

handbook, full pagewidth

CKREFO

VCCOR

OGNDR

VCCOG

OGNDG

VCCOB

n.c.

DEC2

Vref

DEC1

n.c.

RAGC

RBOT

RGAINC

RCLP

RDEC

VCCAR

RIN

AGNDR

GAGC

GBOT

GGAINC

GCLP

GDEC

VCCAG

GIN

AGNDG

BAGC

BBOT

BGAINC

BCLP

BCDEC

VCCAB

BIN

RIN

2.5 V

GIN

BIN

AGNDB

n.c.

VCCA(PLL)

AGNDPLL

VCCD

CKREF

COAST

CKEXT

INV

HSYNC

CLP

PWDWN

DGND

VCCO(PLL)

CKADCO

CKBO

OGNDPLL

CKAO

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

40 41

49 50

FCE082

TDA8752A

n.c.

4.7

1 nF

10 nF

1.5 nF

10 nF

22 nF

4.7 nF

10 nF

22 nF

4.7 nF

10 nF

22 nF

4.7 nF

10 nF

100 nF

150 nF

100 nF

or 50

100 nF

or 50

n.c.

C/3W

ADD1

ADD2

TCK

TDO

DIS

SEN

SCL

VDDD

VSSD

SDA

n.c.

GOR

n.c.

BOR

ROR

n.c.

OGNDB

or 50

1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

SOLDERING

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250

C. The top-surface temperature of the

packages should preferable be kept below 230

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint must
be placed at a 45

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE

SOLDERING METHOD

WAVE

REFLOW

(1)

BGA, SQFP

not suitable

suitable

HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO

not recommended

(5)

suitable

1999 Feb 24

Philips Semiconductors

Product specification

Triple high-speed Analog-to-Digital
Converter (ADC)

TDA8752A

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors a worldwide company

SCA62

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773

Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700

Colombia: see South America

Czech Republic: see Austria

Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905

Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920

France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300

Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 489 4339/4239, Fax. +30 1 481 4240

Hungary: see Austria

India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087

Printed in The Netherlands

545004/750/03/pp36

Date of release: 1999 Feb 24

Document order number:

9397 750 05307

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