2003 Jul 16
2
Philips Semiconductors
Objective specification
Triple 8-bit video ADC up to 270 Msps
TDA8754
CONTENTS
1
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
QUICK REFERENCE DATA
5
ORDERING INFORMATION
6
BLOCK DIAGRAM
7
PINNING
7.1
LQFP144 package
7.2
LBGA208 package
8
FUNCTIONAL DESCRIPTION
8.1
Power management
8.1.1
Standby mode
8.1.2
Power-down mode
8.2
Analog video input
8.2.1
Analog multiplexers
8.2.2
Activity detection
8.2.3
ADC
8.2.4
Clamp
8.2.5
AGC
8.3
PLL
8.4
Sync-on-green
8.5
Programmable coast
8.6
Data enable
8.7
Sync separator
8.8
3-level
9
I
2
C-BUS REGISTER DESCRIPTION
9.1
I
2
C-bus formats
9.1.1
Write 1 register
9.1.2
Write all registers
9.1.3
Read register
9.2
I
2
C-bus registers overview
9.3
Offset registers (R, G and B)
9.4
Coarse registers (R, G and B)
9.5
Fine registers (R, G and B)
9.6
SOG register
9.7
PLL control
9.8
Phase register
9.9
PLL divider registers
9.10
Horizontal sync registers
9.11
Coast register
9.12
Horizontal sync selection register
9.13
Vertical sync selection register
9.14
Clamp register
9.15
Inverter register
9.16
Output register
9.17
Output enable register 1
9.18
Output enable register 2
9.19
Clock output register
9.20
Internal oscillator register
9.21
Power management register
9.22
Read register
9.23
Version register
9.24
Sign detection register
9.25
Activity detection register 1
9.26
Activity detection register 2
10
LIMITING VALUES
11
THERMAL CHARACTERISTICS
12
CHARACTERISTICS
13
TIMING
14
APPLICATION INFORMATION
15
PACKAGE OUTLINE
16
SOLDERING
16.1
Introduction to soldering surface mount
packages
16.2
Reflow soldering
16.3
Wave soldering
16.4
Manual soldering
16.5
Suitability of surface mount IC packages for
wave and reflow soldering methods
17
DATA SHEET STATUS
18
DEFINITIONS
19
DISCLAIMERS
20
PURCHASE OF PHILIPS I
2
C COMPONENTS
2003 Jul 16
3
Philips Semiconductors
Objective specification
Triple 8-bit video ADC up to 270 Msps
TDA8754
1
FEATURES
3.3 V power supply
Triple 8-bit ADC
Analog sampling rate from 12 up to 270 Msps
Maximum data rate:
Single port mode: 140 MHz
Dual port mode: 270 MHz
3.3 V LV-TTL outputs.
PLL control via I
2
C-bus:
Low PLL drift with temperature (2 phase steps
maximum)
PLL generates the ADC sampling clock which can be
locked on the line frequency from 15 to 150 kHz
Integrated PLL divider
Programmable phase clock adjustment cells.
Three clamp circuits for programming a clamp code
from
-
32 to +136 by steps of 1 LSB (mid-scale clamping
for YUV signal)
Internal generation of clamp signal
Three independent blanking functions
Input:
450 MHz analog bandwidth
Two independent analog inputs selectable via
I
2
C-bus
Analog input from 0.5 to 1 V (p-p) to produce a
full-scale ADC input of 1 V (p-p)
Three controllable amplifiers: gain control via I
2
C-bus
to produce full-scale peak-to-peak output with a half
LSB resolution.
Synchronisation:
Frame and field detection for interlaced video signal
Parasite synchronization pulse detection and
suppression
Sync processing for composite sync, 3-level sync and
sync-on-green signals
Polarity and activity detection.
IC control via I
2
C-bus serial interface
Power-down mode.
2
APPLICATIONS
RGB/YUV high-speed digitizing
LCD panels drive
LCD projection system
New TV concept.
3
GENERAL DESCRIPTION
The TDA8754 is a complete triple 8-bit ADC with an
integrated PLL running up to 270 Msps and analog
preprocessing functions (clamp and PGA) optimized for
capturing RGB/YUV graphic signals.
The PLL generates a pixel clock from inputs HSYNC and
COAST.
The TDA8754 offers full sync processing for
sync-on-green applications. A clamp signal may be
generated internally or provided externally.
The clamp levels, gains and other settings are controlled
via the I
2
C-bus interface.
This IC supports display resolutions up to QXGA
(2048
1536) at 85 Hz.
2003 Jul 16
4
Philips Semiconductors
Objective specification
Triple 8-bit video ADC up to 270 Msps
TDA8754
4
QUICK REFERENCE DATA
5
ORDERING INFORMATION
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
V
CCA
analog supply voltage
3.0
3.3
3.6
V
V
CCD
digital supply voltage
3.0
3.3
3.6
V
V
CCO
output supply voltage
3.0
3.3
3.6
V
f
PLL
analog PLL frequency
12
-
270
MHz
ENOB
effective bits
-
7.3
-
bits
INL
DC integral non-linearity
-
1.2
2.5
LSB
DNL
DC differential non-linearity
-
0.5
tbf
LSB
P
tot
power dissipation
-
1.1
1.25
W
TYPE NUMBER
PACKAGE
SAMPLING
FREQUENCY
NAME
DESCRIPTION
VERSION
TDA8754HL/11
LQFP144
plastic low profile quad flat package;
144 leads; body 20
20
1.4 mm
SOT486-1
110 MHz
TDA8754HL/14
140 MHz
TDA8754HL/17
170 MHz
TDA8754HL/21
210 MHz
TDA8754HL/25
250 MHz
TDA8754HL/27
270 MHz
TDA8754EL/11
LBGA208
plastic low profile ball grid array package;
208 balls; body 17
17
1.05 mm
SOT774-1
110 MHz
TDA8754EL/14
140 MHz
TDA8754EL/17
170 MHz
TDA8754EL/21
210 MHz
TDA8754EL/25
250 MHz
TDA8754EL/27
270 MHz
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