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Электронный компонент: TDA8761AM/C1

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DATA SHEET
Product specification
Supersedes data of 1997 Aug 21
File under Integrated Circuits, IC02
1998 Nov 03
INTEGRATED CIRCUITS
TDA8761A
9-bit analog-to-digital converter for
digital video
1998 Nov 03
2
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
FEATURES
9-bit resolution
Sampling rate up to 40 MHz
DC sampling allowed
One clock cycle conversion only
High signal-to-noise ratio over a large analog input
frequency range (8.2 effective bits at 10 MHz full-scale
input at f
clk
= 30 MHz)
No missing codes guaranteed
In Range (IR) CMOS output
Levels TTL and CMOS compatible digital inputs
3 to 5 V CMOS digital outputs
Low-level AC clock input signal allowed
External reference voltage regulator
Power dissipation only 158 mW (typical)
Low analog input capacitance, no buffer amplifier
required
No sample-and-hold circuit required.
APPLICATIONS
Analog-to-digital conversion for:
Video data digitizing
Digital Video Broadcasting (DVB)
Cable TV.
GENERAL DESCRIPTION
The TDA8761A is a 9-bit Analog-to-Digital Converter
(ADC) for professional video and digital video set box
applications. It converts the analog input signal into 9-bit
binary-coded digital words at a maximum sampling rate of
40 MHz. Its linearity performance ensures the required
conversion accuracy in the event of 256-QAM
demodulator concept and for all symbol frequencies.
All digital inputs and outputs are TTL and CMOS
compatible, although a low-level sine wave clock input
signal is allowed.
QUICK REFERENCE DATA
Note
1. f
i
= 10 MHz and f
clk
= 30 MHz; f
i
= 8 MHz and f
clk
= 20 MHz.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CCA
analog supply voltage
4.75
5.0
5.25
V
V
CCD
digital supply voltage
4.75
5.0
5.25
V
V
CCO
output stages supply voltage
3.0
3.3
5.25
V
I
CCA
analog supply current
-
18
24
mA
I
CCD
digital supply current
-
13
18
mA
I
CCO
output stages supply current
f
clk
= 30 MHz; ramp input
-
1
2
mA
INL
integral non-linearity
f
clk
= 30 MHz; ramp input
-
0.8
1.6
LSB
AINL
AC integral non-linearity
full-scale input sine wave; note 1
-
0.75
0.9
LSB
50% full-scale input sine wave; note 1
-
0.5
0.75
LSB
DNL
differential non-linearity
f
clk
= 30 MHz; ramp input
-
0.3
0.7
LSB
ADNL
AC differential non-linearity
full-scale input sine wave; note 1
-
0.5
0.75
LSB
50% full-scale input sine wave; note 1
-
0.3
0.5
LSB
f
clk(max)
maximum clock frequency
40
-
-
MHz
P
tot
total power dissipation
-
158
173
mW
1998 Nov 03
3
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
ORDERING INFORMATION
BLOCK DIAGRAM
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TDA8761AM
SSOP28
plastic shrink small outline package; 28 leads; body width 5.3 mm
SOT341-1
Fig.1 Block diagram.
handbook, full pagewidth
12
DGND2
6
8
7
RLAD
9
VRB
VRM
VRT
V I
11
VCCD2
3
26
VCCA
21
22
23
24
20 D3
D4
D5
D6
D7
19
18
25
2
D2
D1
17 D0
D8
IN RANGE LATCH
CMOS
OUTPUTS
LATCHES
ANALOG -TO - DIGITAL
CONVERTER
CLOCK DRIVER
MBG910
CMOS OUTPUT
1
CLK
10
OE
TC
TDA8761A
13
VCCO
4
AGND
analog ground
digital grounds
27
DGND1
14
OGND
output ground
analog
voltage input
data outputs
LSB
MSB
28 VCCD1
IR
output
1998 Nov 03
4
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
PINNING
SYMBOL
PIN
DESCRIPTION
CLK
1
clock input
TC
2
two's complement input (active LOW)
V
CCA
3
analog supply voltage (5 V)
AGND
4
analog ground
n.c.
5
not connected
V
RB
6
reference voltage BOTTOM input
V
RM
7
reference voltage MIDDLE
V
I
8
analog input voltage
V
RT
9
reference voltage TOP input
OE
10
output enable input (CMOS level
input, active LOW)
V
CCD2
11
digital supply voltage 2 (5 V)
DGND2
12
digital ground 2
V
CCO
13
supply voltage for output stages
(3 to 5 V)
OGND
14
output ground
n.c.
15
not connected
n.c.
16
not connected
D0
17
data output; bit 0 (LSB)
D1
18
data output; bit 1
D2
19
data output; bit 2
D3
20
data output; bit 3
D4
21
data output; bit 4
D5
22
data output; bit 5
D6
23
data output; bit 6
D7
24
data output; bit 7
D8
25
data output; bit 8 (MSB)
IR
26
in range data output
DGND1
27
digital ground 1
V
CCD1
28
digital supply voltage 1 (5 V)
Fig.2 Pin configuration.
handbook, halfpage
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
CLK
TC
CCA
AGND
n.c.
RB
RM
I
RT
OE
CCD2
DGND2
CCO
OGND
CCD1
DGND1
IR
D8
D7
D6
D5
D4
D3
D2
D1
D0
n.c.
n.c.
V
V
V
V
V
V
V
V
TDA8761A
MBG909
1998 Nov 03
5
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1. The supply voltages V
CCA
, V
CCD
and V
CCO
may have any value between
-
0.3 and +7.0 V provided that the supply
voltage differences
V
CC
are respected.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CCA
analog supply voltage
note 1
-
0.3
+7.0
V
V
CCD
digital supply voltage
note 1
-
0.3
+7.0
V
V
CCO
output stages supply voltage
note 1
-
0.3
+7.0
V
V
CC
supply voltage differences
between
V
CCA
and V
CCD
-
1.0
+1.0
V
V
CCD
and V
CCO
-
1.0
+4.0
V
V
CCA
and V
CCO
-
1.0
+4.0
V
V
I
input voltage
referenced to AGND
-
0.3
+7.0
V
V
i(p-p)
AC input voltage for switching
(peak-to-peak value)
referenced to DGND
-
V
CCD
V
I
O
output current
-
10
mA
T
stg
storage temperature
-
55
+150
C
T
amb
operating ambient temperature
0
+70
C
T
j
junction temperature
-
+150
C
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
R
th(j-a)
thermal resistance from junction to ambient
in free air
110
K/W
1998 Nov 03
6
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
CHARACTERISTICS
V
CCA
= V
3
to V
4
= 4.75 to 5.25 V; V
CCD
= V
11
to V
12
and V
28
to V
27
= 4.75 to 5.25 V; V
CCO
= V
13
to V
14
= 3.0 to 5.25 V;
AGND and DGND shorted together; T
amb
= 0 to 70
C; typical values measured at V
CCA
= V
CCD
= 5 V and
V
CCO
= 3.3 V; V
i(p-p)
= 1.8 V; C
L
= 15 pF and T
amb
= 25
C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
CCA
analog supply voltage
4.75
5.0
5.25
V
V
CCD
digital supply voltage
4.75
5.0
5.25
V
V
CCO
output stages supply voltage
3.0
3.3
5.25
V
V
CC
supply voltage differences
between
V
CCA
and V
CCD
-
0.2
-
+0.2
V
V
CCA
and V
CCO
-
0.2
-
+2.25
V
V
CCD
and V
CCO
-
0.2
-
+2.25
V
I
CCA
analog supply current
-
18
24
mA
I
CCD
digital supply current
-
13
18
mA
I
CCO
output stages supply current
f
clk
= 30 MHz; ramp input
-
1
2
mA
Inputs
C
LOCK INPUT
CLK (
REFERENCED TO
DGND); note 1
V
IL
LOW-level input voltage
0
-
0.8
V
V
IH
HIGH-level input voltage
2
-
V
CCD
V
I
IL
LOW-level input current
V
clk
= 0.8 V
-
1
0
+1
A
I
IH
HIGH-level input current
V
clk
= 2 V
-
2
10
A
Z
i
input impedance
f
clk
= 30 MHz
-
2
-
k
C
i
input capacitance
-
2
-
pF
I
NPUTS
OE
AND
TC (
REFERENCED TO
DGND); see Table 2
V
IL
LOW-level input voltage
0
-
0.8
V
V
IH
HIGH-level input voltage
2
-
V
CCD
V
I
IL
LOW-level input current
V
IL
= 0.8 V
-
1
-
-
A
I
IH
HIGH-level input current
V
IH
= 2.0 V
-
-
1
A
V
I
(
ANALOG INPUT VOLTAGE REFERENCED TO
AGND)
I
IL
LOW-level input current
V
I
= V
RB
= 1.3 V
-
17
-
A
I
IH
HIGH-level input current
V
I
= V
RT
= 3.43 V
-
35
-
A
Z
i
input impedance
f
i
= 10 MHz
-
8
-
k
C
i
input capacitance
-
5
-
pF
1998 Nov 03
7
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
Reference voltages for the resistor ladder; see Table 1
V
RB
reference voltage BOTTOM
1.2
1.3
2.45
V
V
RT
reference voltage TOP
3.2
3.43
V
CCA
-
0.8 V
V
diff
differential reference voltage
V
RT
-
V
RB
2
2.13
3.0
V
I
ref
reference current
V
RT
-
V
RB
= 2.13 V
-
8.7
-
mA
R
LAD
resistor ladder
-
245
-
TC
RLAD
temperature coefficient of the
resistor ladder
-
1860
-
ppm
-
456
-
m
/K
V
osB
offset voltage BOTTOM
note 2
-
160
-
mV
V
osT
offset voltage TOP
note 2
-
160
-
mV
V
i(p-p)
analog input voltage
(peak-to-peak value)
note 3
1.7
1.81
2.55
V
Outputs
D
IGITAL OUTPUTS
D8
TO
D0
AND
IR (
REFERENCED TO
OGND)
V
OL
LOW-level output voltage
I
OL
= 1 mA
0
-
0.5
V
V
OH
HIGH-level output voltage
I
OH
=
-
1 mA
V
CCO
-
0.5
-
V
CCO
V
I
OZ
output current in 3-state mode
0.5 V < V
O
< V
CCO
-
20
-
+20
A
Switching characteristics
C
LOCK INPUT
CLK; see Fig.4; note 1
f
clk(max)
maximum clock frequency
40
-
-
MHz
t
CPH
clock pulse width HIGH
10
-
-
ns
t
CPL
clock pulse width LOW
10
-
-
ns
Analog signal processing
L
INEARITY
INL
integral non-linearity
f
clk
= 30 MHz; ramp input
-
0.4
1
LSB
AINL
AC integral non-linearity
full-scale input sine
wave; note 4
-
0.75
0.9
LSB
50% full-scale input sine
wave; note 4
-
0.5
0.75
LSB
DNL
differential non-linearity
f
clk
= 30 MHz; ramp input
-
0.3
0.7
LSB
ADNL
AC differential non-linearity
full-scale input sine
wave; note 4
-
0.5
0.75
LSB
50% full-scale input sine
wave; note 4
-
0.3
0.5
LSB
OFER
offset error
middle code;
V
RB
= 1.3 V;
V
RT
= 3.43 V
-
1
-
LSB
GER
gain error (from
device to device)
V
RB
= 1.3 V;
V
RT
= 3.43 V; note 5
-
0.1
-
%
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1998 Nov 03
8
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
B
ANDWIDTH
(f
clk
= 30 MH
Z
)
B
analog bandwidth
full-scale sine wave;
note 6
-
15
-
MHz
75% full-scale sine wave;
note 6
-
20
-
MHz
small signal at mid-scale;
V
I
=
10 LSB at
code 256; note 6
-
350
-
MHz
t
STLH
analog input settling time
LOW-to-HIGH
full-scale square wave;
Fig.6; note 7
-
1.5
3.0
ns
t
STHL
analog input settling time
HIGH-to-LOW
full-scale square wave;
Fig.6; note 7
-
1.5
3.0
ns
H
ARMONICS
(f
clk
= 30 MH
Z
); see Figs 7 and 8
THD
total harmonic distortion
f
i
= 10 MHz
-
-
56
-
dB
S
IGNAL
-
TO
-
NOISE RATIO
; see Figs 7 and 8; note 8
SNR
signal-to-noise ratio (full scale)
without harmonics;
f
clk
= 30 MHz;
f
i
= 10 MHz
53
55
-
dB
E
FFECTIVE BITS
; see Figs 7 and 8; note 8
ENOB
effective bits
f
clk
= 30 MHz
f
i
= 4.43 MHz
-
8.8
-
bits
f
i
= 10 MHz
-
8.2
-
bits
T
WO
-
TONE
; note 9
TTIR
two-tone intermodulation
rejection
f
clk
= 30 MHz
-
-
56
-
dB
B
IT ERROR RATE
BER
bit error rate
f
clk
= 30 MHz;
f
i
= 10 MHz;
V
I
=
16 LSB at
code 256
-
10
-
13
-
times/
sample
D
IFFERENTIAL GAIN
; note 10
G
diff
differential gain
f
clk
= 30 MHz;
PAL modulated ramp
-
0.5
-
%
D
IFFERENTIAL PHASE
; note 10
diff
differential phase
f
clk
= 30 MHz;
PAL modulated ramp
-
0.3
-
C
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1998 Nov 03
9
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.
2. Analog input voltages producing code 0 up to and including code 511:
a) V
osB
(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (V
RB
) at T
amb
= 25
C.
b) V
osT
(voltage offset TOP) is the difference between V
RT
(reference voltage TOP) and the analog input which
produces data outputs equal to code 511 at T
amb
= 25
C.
3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 511 respectively) are connected to
pins V
RB
and V
RT
via offset resistors R
OB
and R
OT
as shown in Fig.3.
a) The current flowing into the resistor ladder is
and the full-scale input range at the converter,
to cover code 0 to code 511, is
b) Since R
L
, R
OB
and R
OT
have similar behaviour with respect to process and temperature variation, the ratio
will be kept reasonably constant from device to device. Consequently variation of the output
codes at a given input voltage depends mainly on the difference V
RT
-
V
RB
and its variation with temperature and
supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the
matching between each of them is then optimized.
4. f
i
= 10 MHz and f
clk
= 30 MHz; f
i
= 8 MHz and f
clk
= 20 MHz.
5.
6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.
No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.
7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square wave signal) in order to sample the signal and obtain correct output data.
Timing (f
clk
= 30 MHz; C
L
= 15 pF); see Fig.4; note 11
t
ds
sampling delay time
-
3
-
ns
t
h
output hold time
4
-
-
ns
t
d
output delay time
V
CCO
= 4.75 V
-
10
13
ns
V
CCO
= 3.15 V
-
12
15
ns
C
L
digital output load
-
-
15
pF
3-state output delay times; see Fig.5
t
dZH
enable HIGH
-
5.5
8.5
ns
t
dZL
enable LOW
-
12
15
ns
t
dHZ
disable HIGH
-
19
24
ns
t
dLZ
disable LOW
-
12
15
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I
L
V
RT
V
RB
R
OB
R
L
R
OT
+
+
------------------------------------------
=
V
I
R
L
I
L
R
L
R
OB
R
L
R
OT
+
+
------------------------------------------
=
=
V
RT
(
V
RB
)
0.
852
V
(
RT
V
RB
)
=
R
L
R
OB
R
L
R
OT
+
+
------------------------------------------
GER
V
511
V
0
(
)
V
i(p-p)
V
i(p-p)
----------------------------------------------------
100
=
1998 Nov 03
10
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
8. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = ENOB
6.02 + 1.76 dB.
9. Intermodulation measured relative to either tone with analog input frequencies of 10.0 and 10.10 MHz. The two input
signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter.
10. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a
digital-to-analog converter.
11. Output data acquisition: the output data is available after the maximum delay time of t
d
.
Fig.3 Explanation of note 3.
handbook, halfpage
RLAD
ROT
VRT
VRM
VRB
ROB
IL
RL
code 511
code 0
7
6
9
MGD233
1998 Nov 03
11
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
Table 1
Output coding and input voltage (typical values; referenced to AGND, V
RB
= 1.3 V, V
RT
= 3.43 V)
Table 2
Mode selection
STEP
V
I(p-p)
IR
BINARY OUTPUT BITS
TWO'S COMPLEMENT OUTPUT BITS
D8
D7
D6
D5
D4
D3
D2
D1
D0
D8
D7
D6
D5
D4
D3
D2
D1
D0
U/F
<1.46
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1.46
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
.
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
510
.
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
511
3.27
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
O/F
>3.27
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
TC
OE
D8 to D0
IR
X
1
high impedance
high impedance
0
0
active; two's complement
active
1
0
active; binary
active
Fig.4 Timing diagram.
handbook, full pagewidth
ds
t
sample N + 1
sample N
CLK
MBG908
sample N + 2
50%
0 V
VCCD
50%
0 V
VCCO
V
l
DATA
D0 to D8
t d
t h
CPH
t
CPL
t
DATA
N + 1
DATA
N
DATA
N - 1
DATA
N - 2
1998 Nov 03
12
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
f
OE
= 100 kHz.
Fig.5 Timing diagram and test conditions of 3-state output delay time.
ndbook, full pagewidth
MBG907
50 %
50 %
HIGH
LOW
dZH
t
dHZ
t
50 %
HIGH
LOW
dZL
t
dLZ
t
10 %
90 %
output
data
VCCD
output
data
3.3 k
15 pF
S1
VCCD
TDA8761A
OE
OE
TEST
dLZ
t
dZL
t
dHZ
t
dZH
S1
CCD
V
CCD
V
DGND
DGND
t
Fig.6 Analog input settling-time diagram.
handbook, full pagewidth
MGC359
50 %
STLH
t
2 ns
code 0
code 511
I
50 %
0.5 ns
50 %
2 ns
STHL
t
50 %
0.5 ns
CLK
V
1998 Nov 03
13
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
Fig.7 Typical Fast Fourier Transform (f
clk
= 30 MHz; f
i
= 4.43 MHz).
Effective bits: 8.70; THD =
-
68.68 dB.
Harmonic levels (dB): 2nd =
-
78.40; 3rd =
-
72.08; 4th =
-
75.85 dB; 5th =
-
76.26; 6th =
-
80.23.
handbook, full pagewidth
0
120
0
1.25
2.50
MBG912
40
80
6.26
3.76
5.01
7.51
8.77
10.0
f (MHz)
100
20
60
amplitude
(dB)
Fig.8 Typical Fast Fourier Transform (f
clk
= 30 MHz; f
i
= 10 MHz).
Effective bits: 8.25; THD =
-
56.72 dB.
Harmonic levels (dB): 2nd =
-
62.21; 3rd =
-
58.58; 4th =
-
80.29; 5th =
-
71.71; 6th =
-
72.04.
handbook, full pagewidth
0
120
0
1.87
3.75
MBG911
40
80
9.37
5.62
7.50
11.2
13.1
15.0
f (MHz)
100
20
60
amplitude
(dB)
1998 Nov 03
14
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
Fig.9 Typical AC INL (f
clk
= 30 MHz; f
i
= 10 MHz).
handbook, full pagewidth
0.6
0.8
1
-
1
-
0.8
0
100
200
300
Code
LSB
500
400
-
0.2
0
0.2
0.4
-
0.6
-
0.4
FCE166
Fig.10 Typical AC DNL (f
clk
= 30 MHz; f
i
= 10 MHz).
handbook, full pagewidth
0.6
0.8
1
-
1
-
0.8
0
100
200
300
Code
LSB
500
400
-
0.2
0
0.2
0.4
-
0.6
-
0.4
FCE165
1998 Nov 03
15
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
INTERNAL PIN CONFIGURATIONS
Fig.11 CMOS data and in range outputs.
handbook, halfpage
MGD231
VCCO
OGND
D8 to D0
IR
Fig.12 Analog inputs.
handbook, halfpage
MGC040 - 1
AGND
V CCA
V I
Fig.13 OE (TC) input.
handbook, halfpage
MBE557
V CCO
OGND
OE
(TC)
Fig.14 V
RB
, V
RM
and V
RT
inputs.
handbook, halfpage
R
MGD232
VRB
VRM
VCCA
AGND
VRT
LAD
1998 Nov 03
16
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
Fig.15 CLK input.
handbook, halfpage
1.5 V
VCCD
DGND
CLK
MBE559 - 1
1998 Nov 03
17
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
APPLICATION INFORMATION
Fig.16 Application diagram.
The analog and digital supplies should be separated and decoupled.
The external voltage regulator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the
reference ladder voltages can be derived from a well regulated V
CCA
supply through a resistor bridge and a decoupled capacitor.
(1) V
RB
, V
RM
and V
RT
are decoupled to AGND.
(2) Pins 15 and 16 may be connected to DGND in order to prevent noise influence.
handbook, halfpage
28
27
26
25
24
23
22
21
20
19
18
17
TDA8761A
DGND1
VCCO
D2
D3
D4
D5
D6
D7
D8
D1
D0
VCCD2
VCCA
1
2
3
4
5
6
7
8
9
10
11
12
CLK
AGND
n.c.
n.c.
VRB
VRM
VRT
MBG906
16
15
13
14
100 nF
100 nF
DGND2
OGND
IR
OE
TC
VCCD1
AGND
AGND
100 nF
AGND
V I
(1)
(1)
(1)
(2)
n.c.
(2)
1998 Nov 03
18
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
PACKAGE OUTLINE
UNIT
A
1
A
2
A
3
b
p
c
D
(1)
E
(1)
(1)
e
H
E
L
L
p
Q
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
10.4
10.0
5.4
5.2
0.65
1.25
7.9
7.6
0.9
0.7
1.1
0.7
8
0
o
o
0.13
0.1
0.2
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
1.03
0.63
SOT341-1
MO-150AH
93-09-08
95-02-04
X
w
M
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
(A )
3
A
1
14
28
15
0.25
y
pin 1 index
0
2.5
5 mm
scale
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
SOT341-1
A
max.
2.0
1998 Nov 03
19
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
"Data Handbook IC26; Integrated Circuit Packages"
(order code 9398 652 90011).
Reflow soldering
Reflow soldering techniques are suitable for all SSOP
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250
C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45
C.
Wave soldering
Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
If wave soldering cannot be avoided, the following
conditions must be observed:
A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
The longitudinal axis of the package footprint must
be parallel to the solder flow and must incorporate
solder thieves at the downstream end.
Even with these conditions, only consider wave
soldering SSOP packages that have a body width of
4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260
C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150
C within
6 seconds. Typical dwell time is 4 seconds at 250
C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300
C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320
C.
1998 Nov 03
20
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
1998 Nov 03
21
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
NOTES
1998 Nov 03
22
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
NOTES
1998 Nov 03
23
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
NOTES
Internet: http://www.semiconductors.philips.com
Philips Semiconductors a worldwide company
Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
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Printed in The Netherlands
545104/750/03/pp24
Date of release: 1998 Nov 03
Document order number:
9397 750 04668