2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

FEATURES

Multistandard Vision IF (VIF) circuit with Phase-Locked
Loop (PLL) demodulator

Sound IF (SIF) amplifier with separate input for single
reference Quasi Split Sound (QSS) mode and separate
Automatic Gain Control (AGC) circuit

AM demodulator without extra reference circuit

Switchable group delay correction circuit which can be
used to compensate the group delay pre-correction of
the B/G TV standard in multistandard TV receivers

Several (I

C-bus controlled) switch outputs which can

be used to switch external circuits such as sound traps,
etc.

Flexible source selection circuit with 2 external
CVBS inputs, 2 Luminance (Y) and Chrominance (C)
(or additional CVBS) inputs and 2 independently
switchable outputs

Comb filter interface with CVBS output and Y/C input

Integrated chrominance trap circuit

Integrated luminance delay line with adjustable delay
time

Integrated chrominance band-pass filter with switchable
centre frequency

Multistandard colour decoder with 4 separate pins for
crystal connection and automatic search system

PALplus helper demodulator

Possible blanking of the helper signals for PALplus and
EDTV-2

Internal baseband delay line

Two linear RGB inputs with fast blanking; the
RGB signals are converted to YUV signals before they
are supplied to the outputs; one of the RGB inputs can
also be used as YUV input

Horizontal synchronization circuit with switchable time
constant for the PLL and Macrovision/subtitle gating

Horizontal synchronization pulse output or clamping
pulse input/output

Vertical count-down circuit

Vertical synchronization pulse output

Two-level sandcastle pulse output

C-bus control of various functions

Low dissipation.

GENERAL DESCRIPTION

The TDA9321H (see Fig.1) is an input processor for
`High-end' television receivers. It contains the following
functions:

Multistandard IF amplifier with PLL demodulator

QSS-IF amplifier and AM sound demodulator

CVBS and Y/C switch with various inputs and outputs

Multistandard colour decoder which can also decode the
PALplus helper signal

Integrated baseband delay line (64

Sync processor which generates the horizontal and
vertical drive pulses for the feature box
(100 Hz applications) or display processor
(50 Hz applications).

The supply voltage for the TDA9321H is 8 V.

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

ORDERING INFORMATION

QUICK REFERENCE DATA

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA9321H

QFP64

plastic quad flat package; 64 leads (lead length 1.95 mm);
body 14

2.8 mm

SOT319-2

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

Supply

supply voltage (pins V

and V

)

7.2

8.0

8.8

supply current (pins V

and V

)

120

Input signals

i(VIF)(rms)

VIF amplifier sensitivity (RMS value)

i(SIF)(rms)

SIF amplifier sensitivity (RMS value)

100

i(CVBS/Y)(p-p)

CVBS or Y input signal (peak-to-peak value)

1.0

i(C)(p-p)

chrominance input signal (burst amplitude) (peak-to-peak value)

0.3

i(RGB)(p-p)

RGB input signal (peak-to-peak value)

0.7

Output signals

o(VIFO)(p-p)

demodulated CVBS output signal (peak-to-peak value)

2.5

o(CVBSPIP)(p-p)

CVBS output signal for Picture-In-Picture (peak-to-peak value)

1.0

o(CVBSTXT)(p-p)

CVBS output signal for teletext (peak-to-peak value)

2.0

o(TAGC)

tuner AGC output current

o(QSS)(rms)

QSS output signal (RMS value)

100

o(AM)(rms)

demodulated AM sound output signal (RMS value)

600

o(V)(p-p)

V output signal (peak-to-peak value)

1.05

o(U)(p-p)

U output signal (peak-to-peak value)

1.33

o(Y)(b-w)

Y output signal (black-to-white value)

1.0

o(hor)

horizontal pulse output

o(ver)

vertical pulse output

o(sc)(p-p)

subcarrier output signal (peak-to-peak value)

200

2000

Sep

Philips Semiconductors

Preliminar

y specification

C-b

us controlled TV input processor

TD
A9321H

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BLOCK DIA

GRAM

MGR473

handbook, full pagewidth

VIFVCO2

VIFVCO1

TAGC

AFC

TOP

mute

Y/CVBS

helper

hue

fsc

switch control

VIF AMPLIFIER

AND PLL

DEMODULATOR

AGC/AFC

VIDEO AMPLIFIER

MUTE

SUPPLY

PULSE

GENERATOR

SOUND

TRAP

GROUP DELAY

CORRECTION

VIDEO SWITCHES

AND

CONTROL

VIFO

GDI

GDO

CVBS/Y4

SW1

CVBS/Y3

SW0

CVBS2

AV2

CVBS1

AV1

CVBSint

VIF1

VIF2 DECVIF

VCO AND

HORIZONTAL

PLL

VIDEO

IDENTIFICATION

IDENT

SYNC

SEPARATOR

AUTOMATIC

CHROMINANCE

CONTROL

CLOCHE

FILTER

VERTICAL

DIVIDER

SYNC

IN-LOCK

DETECTOR

FILTER

TUNING

C-BUS

TRANSCEIVER

Y-DELAY

Y-delay

RGB2

Y-SWITCH

AND TRAPS

SECAM

DECODER

RGB MATRIX

Y/U/V

SWITCH

BASEBAND

DELAY LINE

PAL(NTSC)/

SECAM SWITCH

Y/C

DETECTOR

BANDPASS

FILTER

subcarrier

COMB FILTER

PAL/NTSC

PLL

HUE CONTROL

SYSTEM

IDENTIFICATION

PAL/NTSC

DEMODULATOR

SIF AMPLIFIER

AGC

QSS MIXER

AM DEMODULATOR

SIF1

HA/CLP

SCO

SCL

SDA

GI1

RI1

BI1

RGB1

SIF2

DECSIF

VP1

QSS/AM

VP2 DECDIG

DECBG

VIFPLL

VERTICAL

SYNC

SEPARATOR

BI2

GI2

RI2

B-Y

R-Y

DECSEC

PH1LF

REFO

CCF

YCF

SYS2

SYS1

CVBSCF

CVBSPIP

CVBSTXT

LFBP

XTALD

XTALC

XTALB

XTALA

GND3

GND2

GND1

TDA9321H

Fig.1 Block diagram.

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

PINNING

SYMBOL

PIN

DESCRIPTION

DEC

SIF

SIF AGC decoupling

VIF1

VIF input 1

VIF2

VIF input 2

DEC

VIF

VIF AGC decoupling

QSS/AM

combined QSS and AM sound output

VIFPLL

VIF PLL filter

VIFVCO1

VIF VCO tuned circuit 1

VIFVCO2

VIF VCO tuned circuit 2

GND1

main supply ground

VIFO

VIF output

positive supply 1 (+8 V)

GDI

group delay correction input

GDO

group delay correction output

CVBS

int

internal CVBS input

AV1

AV input 1

CVBS1

CVBS input 1

AV2

AV input 2

CVBS2

CVBS input 2

SW0

switch output bit 0 (I

C-bus)

CVBS/Y3

CVBS or luminance input 3

chrominance input 3

SW1

switch output bit 1 (I

C-bus)

CVBS/Y4

CVBS or luminance input 4

chrominance input 4

SYS1

system output 1 for comb filter

CVBSCF

CVBS output for comb filter

SYS2

system output 2 for comb filter

YCF

luminance input from comb filter

CCF

chrominance input from comb filter

REFO

reference output (subcarrier)

GND2

digital supply ground

CVBSPIP

CVBS output for Picture-In-Picture

DEC

DIG

digital supply decoupling

CVBSTXT

CVBS output for teletext

DEC

band gap decoupling

RI1

red input 1

GI1

green input 1

BI1

blue input 1

RGB1

RGB insertion input 1

RGB2

RGB insertion input 2

RI2

red input 2

GI2

green input 2

BI2

blue input 2

GND3

ground 3

positive supply 2 (+8 V)

SCL

serial clock input (I

C-bus)

SDA

serial data input/output (I

C-bus)

address select input (I

C-bus)

luminance output

U-signal output

V-signal output

LFBP

loop filter burst phase detector

DEC

SEC

SECAM PLL decoupling

XTALA

crystal A (4.433619 MHz)

XTALB

crystal B (3.582056 MHz)

XTALC

crystal C (3.575611 MHz)

XTALD

crystal D (3.579545 MHz)

PH1LF

phase 1 loop filter

SCO

sandcastle pulse output

HA/CLP

horizontal pulse output or clamp pulse
input/output

vertical pulse output

TAGC

tuner AGC output

SIF1

SIF input 1

SIF2

SIF input 2

SYMBOL

PIN

DESCRIPTION

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

FUNCTIONAL DESCRIPTION

Vision IF amplifier

The VIF amplifier contains three AC-coupled control
stages with a total gain control range higher than 66 dB.
The sensitivity of the circuit is comparable with that of
modern IF-ICs.

The video signal is demodulated by a PLL carrier
regenerator, which contains a frequency detector and
a phase detector. During acquisition, the frequency
detector tunes the VCO to the correct frequency. The initial
adjustment of the oscillator is realized via the I

C-bus. The

switching between SECAM L and L' can also be realized
via the I

C-bus. After lock-in, the phase detector controls

the VCO so that a stable phase relationship between
the VCO and the input signal is achieved. The VCO
operates at twice the IF frequency. The reference signal
for the demodulator is obtained by means of a frequency
divider circuit. To get good performance for phase
modulated carrier signals, the control speed of the PLL can
be increased by bit FFI.

The AFC output is obtained by using the VCO control
voltage of the PLL and can be read via the I

C-bus. For

fast search tuning systems, the window of the AFC can be
increased with a factor 3. The setting is realized with
bit AFW.

The AGC detector operates on top sync and top white
level. The demodulation polarity is switched via the
I

C-bus. The AGC detector time constant capacitor is

connected externally: mainly because of the flexibility of
the application. The time constant of the AGC system
during positive modulation is rather long, to avoid visible
variations of the signal amplitude. To improve the speed of
the AGC system, a circuit is included that detects whether
the AGC detector is activated every frame period. When
no action is detected during three field periods, the speed
of the system is increased. For signals without peak white
information, the system automatically switches to a gated
black level AGC. Because a black level clamp pulse is
required for this mode of operation, the circuit only
switches to black level AGC in the internal mode.

The circuit contains a video identification (ident) circuit
which is independent of the synchronization circuit.
Therefore, search tuning is possible when the display
section of the receiver is used as a monitor. However, this
ident circuit cannot be made as sensitive as the slower
sync ident circuit (bit SL) and we recommend the use of
both ident outputs to obtain a reliable search system. The
ident output is supplied to the tuning system via the
I

C-bus.

The input of the ident circuit is connected to pin 14
(see Fig.3). This has the advantage that the ident circuit
can also be activated when a scrambled signal is received
(descrambler connected between the IF video output
(pins 10 and 14). A second advantage is that the ident
circuit can be used when the VIF amplifier is not used (e.g.
with built-in satellite tuners). The video ident circuit can
also be used to identify the selected CBVS or Y/C signal.
The switching between the two modes can be realized with
bit VIM.

The TDA9321H contains a group delay correction circuit
which can be switched between the BG and a flat group
delay response characteristic. This has the advantage that
no compromise has to be made in multistandard receivers
for the choice of the SAW filter. Both the input and output
of the group delay correction circuit are externally
available, so that the sound trap can be connected
between the IF video output and the group delay
correction input. The output signal of the correction circuit
can be supplied to the video processing circuit and to the
external SCART plug.

The IC has several (I

C-bus controlled) output ports which

can be used to switch sound traps or other external
components.

When the VIF amplifier is not used, the complete
VIF amplifier can be switched off with bit IFO via the
I

C-bus.

Sound circuit

The SIF amplifier is similar to the VIF amplifier and has
a gain control range of approximately 66 dB. The
AGC circuit is related to the SIF carrier levels (average
level of AM or FM carriers) and ensures a constant signal
amplitude of the AM demodulator and the QSS mixer.

The single reference QSS mixer is realized by a multiplier.
This multiplier converts the SIF signal to the intercarrier
frequency by mixing it with the regenerated picture carrier
from the VCO. The mixer output signal is supplied to the
output via a high-pass filter to attenuate the residual video
signals. With this system, a high performance hi-fi stereo
sound processing can be achieved.

The AM sound demodulator is realized by a multiplier. The
modulated SIF signal is multiplied in phase with the limited
SIF signal. The demodulator output signal is supplied to
the output via a low-pass filter to attenuate the carrier
harmonics.

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

Video switches

The circuit has three CVBS inputs (one internal and two
external inputs) and two Y/C inputs. The Y/C inputs can
also be used as additional CVBS inputs. The switch
configuration is given in Fig.3. The various sources are
selected via the I

C-bus.

The circuit can be set in a mode in which it automatically
detects whether a CVBS or a Y/C signal is supplied to the
Y/C inputs. In this mode, the TV standard is first identified
on the added Y/CVBS and the C input signal. Then, both
chrominance input signal amplitudes are checked once
and the input signal with the highest burst signal amplitude
is selected. The result of the detection can be read via the
I

C-bus.

The IC has two inputs (AV1 and AV2), which can be used
to read the status levels of pin 8 of the SCART plug. The
information is available in the output status byte 02 in
bits D0 to D3.

The three outputs of the video switch (CVBSTXT,
CVBSPIP and COMBCVBS) can be independently
switched to the various input signals. The names are just
arbitrary and it is for instance possible to use the
COMBCVBS signal to drive the comb filter and the teletext
decoder in parallel and to supply the CVBSTXT signal to
the SCART plug (via an emitter follower).

For comb filter interfacing, the circuit has the COMBCVBS
output, a third Y/C input, a reference signal output (f

) and

two control pins which switch the comb filter to the
standard of the incoming signal (as detected by the ident
circuit of the colour decoder). When the comb filter is
enabled by bit ECMB and a signal is recognized which can
be combed, the Y/C signals coming from the comb filter
are automatically selected if the original source is a CVBS
signal, indicated via the CMB-bit in output status
byte 02 (D5). For signals which cannot be combed (like
SECAM or Black-to-White signals) and for Y/C input
signals, the Y/C signals coming from the comb filter are not
selected.

Chrominance and luminance processing

The circuits contain a chrominance bandpass, a SECAM
cloche filter and a chrominance trap circuit. The filters are
realized by means of gyrator circuits and they are
automatically calibrated by comparing the tuning
frequency with the crystal frequency of the decoder. The
luminance delay line is also realized by means of gyrator
circuits. The centre frequency of the chrominance
bandpass filter is switchable via the I

C-bus so that the

performance can be optimized for `front-end' signals and
external CVBS signals.

The luminance output signal which is derived from the
incoming CVBS or Y/C signal can be varied in amplitude
by means of a separate gain setting control via the I

C-bus

control bits GAI1 and GAI0. The gain variation which can
be realized with these bits is

1 to +2 dB.

Colour decoder

The colour decoder can decode PAL, NTSC and SECAM
signals. The PAL/NTSC decoder contains an
alignment-free crystal oscillator with four separate crystal
pins, a killer circuit and two colour difference
demodulators. The 90

phase shift for the reference signal

is made internally.

Because it is possible to connect four different crystals to
the colour decoder, all colour standards can be decoded
without external switching circuits. Which crystals are
connected to the decoder must be indicated via the
I

C-bus. The crystal connection pins that are not used

must be left open circuit.

The horizontal oscillator is calibrated by means of the
crystal frequency of the colour PLL. For a reliable
calibration, it is very important that crystal indication
bits XA to XD are not corrupted. For this reason, the
crystal bits can be read in the output bytes so that the
software can check the I

C-bus transmission.

The ICs contain an Automatic Colour Limiting (ACL)
circuit, which can be switched via the I

C-bus and which

prevents oversaturation occurring when signals with a high
chrominance-to-burst ratio are received. The ACL circuit is
designed such that it only reduces the chrominance signal
and not the burst signal. This has the advantage that the
colour sensitivity is not affected by this function. The
ACL function is mainly intended for NTSC signals but it
can also be used for PAL signals. For SECAM signals, the
ACL function should be switched off.

The SECAM decoder contains an auto-calibrating
PLL demodulator which has two references: the 4.43 MHz
sub-carrier frequency (which is obtained from the crystal
oscillator which is used to tune the PLL to the desired
free-running frequency) and the bandgap reference (to
obtain the correct absolute value of the output signal). The
VCO of the PLL is calibrated during each vertical blanking
period, when the IC is in search or SECAM mode.

The circuit can also decode the PALplus helper signal and
can insert the various reference signals, set-ups and
timing signals which are required for the PALplus decoder
ICs.

The baseband delay line (TDA4665 function) is integrated.

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

RGB switch and matrix

The IC has two RGB inputs with fast switching. The
switching of the various sources is controlled via the
I

C-bus and the condition of the switch inputs can be read

from the I

C-bus status bytes. If the RGB signals are not

synchronous with the selected decoder input signal, an
external clamp pulse has to be supplied to the HA/CLP
input. The IC must be set in this mode via the I

C-bus. In

this case, the VA pulse is suppressed by switching the
VA output to a high impedance OFF state.

When an external RGB signal is mixed into the internal
YUV signal, it is necessary to switch-off the PALplus
demodulation. To detect the presence of a fast blanking,
a circuit is added which forces the MACP and HD bits to
zero if a blanking pulse is detected in two consecutive
lines. This system is chosen to prevent switching off at
every spike that is detected on the fast blanking input.

The IC can use input RGB1 as YUV input. This function
can be enabled by bit YUV in subaddress 0A (D3). When
switched to the YUV input, the input signals must have the
same amplitude and polarity as the YUV output signals.
The Y signal has to be supplied to the G1 input, the
U signal to the B1 input and the V signal to the R1 input.

Synchronization circuit

The sync separator is preceded by a controlled amplifier
that adjusts the sync pulse amplitude to a fixed level.
These pulses are fed to the slicing stage, which operates
at 50% of the amplitude. The separated sync pulses are
fed to the phase detector and to the coincidence detector.
This detector detects whether the line oscillator is
synchronized and can also be used for transmitter
identification. This circuit can be made less sensitive by
means of bit STM. This mode can be used during search
tuning to avoid the tuning system from stopping at very
weak input signals. The PLL has a very high static
steepness so that the phase of the picture is independent
of the line frequency.

Two conditions are possible for the horizontal output
pulse:

An HA pulse which has a phase and width that are
identical to the incoming horizontal sync pulse

A Clamp Pulse (CLP) which has a phase and width that
are identical to the clamp pulse in the sandcastle pulse.

Signal HA/CLP is generated by an oscillator that runs at
a frequency of 440

. Its frequency is divided by 440 to

lock the first loop to the incoming signal. The time constant
of the loop can be forced by the I

C-bus (fast or slow).

If required, the IC can select the time constant, depending
on the noise content of the incoming video signal.

The free-running frequency of the oscillator is determined
by a digital control circuit, which is locked to the reference
signal of the colour decoder. When the IC is switched on,
the HA/CLP is suppressed and the oscillator is calibrated
as soon as all sub-address bytes have been sent. When
the frequency of the oscillator is correct, the HA/CLP signal
is switched on again.

When the coincidence detector indicates an out-of-lock
situation, the calibration procedure is repeated.

The VA pulse is obtained via a vertical countdown circuit.
This circuit has various windows, depending on the
incoming signal (50 or 60 Hz standard or no standard).
The countdown circuit can be forced to various modes by
means of the I

C-bus. To obtain short switching times of

the countdown circuit during a channel change, the divider
can be forced in the search window by means of bit NCIN.

C-BUS SPECIFICATION

The slave addresses of the ICs are given in Table 1. The
circuit operates up to clock frequencies of 400 kHz.

Table 1

Slave addresses

Bit A1 is controlled via pin 48 (AS). When the pin is
connected to ground, it is a logic 0; when connected to the
positive supply line, it is a logic 1. When this pin is left
open, it is connected to ground via an internal resistor.

Start-up procedure

Read the status bytes until POR = logic 0 and send all
subaddress bytes. Check the bus transmission by reading
output status bits SXA to SXD. This ensures good
operation of the calibration system of the horizontal
oscillator. The horizontal output signal is switched on when
the oscillator is calibrated.

Read the status bytes each time before the data in the IC
is refreshed. If POR = logic 1, the procedure mentioned
above must be carried out to restart the IC. When this
procedure is not followed, the horizontal frequency may be
incorrect after power-up or after a power dip.

The 00 to 0E subaddresses are valid. The
FE and FF subaddresses are reserved for test purposes.
The auto-increment mode is available for subaddresses.

R/W

1/0

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

Inputs and outputs

Table 2

Input status bits

FUNCTION

SUBADDRESS

(HEX)

DATA BYTE

Colour decoder 0

CM3

CM2

CM1

CM0

Colour decoder 1

MACP

HOB

HBC

FCO

ACL

BPS

Luminance

GAI1

GAI0

YD3

YD2

YD1

YD0

Hue control

Spare

Synchronization 0

FORF

FORS

FOA

FOB

VIM

POC

VID

Synchronization 1

BSY

EMG

NCIN

Spare

Video switches 0

ECMB

DEC3

DEC2

DEC1

DEC0

Video switches 1

PIP2

PIP1

PIP0

TXT2

TXT1

TXT0

RGB switch

YUV

ECL

IE2

IE1

Output switches

OS1

OS0

Vision IF

FFI

IFO

MOD

AFW

IFS

STM

VSW

Tuner takeover

Adjustment IF-PLL

L'FA

NPUT CONTROL BITS

Table 3

Colour decoder mode

Table 4

Crystal indication

Note

1. When a comb filter is used, the various crystals must

be connected to the IC as indicated in the pinning
diagram. This is required because the ident system
switches automatically to the comb filter when a signal
is identified which can be combed (correct
combination of colour standard and crystal frequency).
For applications without comb filter only the crystal on
pin XTALA is important (4.43 MHz); to pins XTALB to
XTALD an arbitrary 3.5 MHz crystal can be connected.

CM3 CM2 CM1 CM0

DECODER MODE

XTAL

PAL/NTSC/SECAM

PAL/NTSC

PAL

NTSC

SECAM

PAL/NTSC

PAL

NTSC

PAL/NTSC/SECAM A/B/C/D

PAL/NTSC

PAL

NTSC

PAL/NTSC

A/B/C/D

PAL/NTSC

PAL

NTSC

XA to XD

CONDITION

crystal not present

crystal present; note 1

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

Table 5

Motion Adaptive Colour Plus (MACP)

Note

1. The black set-up will only be present in a norm sync

condition.

Table 6

Helper output blanking (PALplus/EDTV-2)

Note

1. X = don't care.

Table 7

PALplus helper demodulation active

Note

1. Black and helper set-up will only be present in a norm

sync condition.

Table 8

Forced colour on

Table 9

Automatic colour limiting

Table 10 Chrominance band-pass centre frequency

Table 11 Bypass of chrominance baseband delay line

Table 12 Gain luminance channel

Table 13 Y-delay adjustment; notes 1 and 2

Notes

1. For an equal delay of the luminance and chrominance

signal the delay must be set at a value of 280 ns
(YD3 to YD0 = 1011). This is only valid for a CVBS
signal without group delay distortions.

2. The total Y-delay is the addition of:

YD3 + YD2 + YD1 + YD0.

Table 14 Forced field frequency

Note

1. When switched to this mode the divider will directly

switch to forced 60 Hz only.

MACP

MODE

internal 4.43 MHz trap used

external MACP chrominance filtering used;
4.43 MHz trap bypassed and black set-up
200 mV; note 1

HOB

HBC

SNR

BLANKING

(1)

off

(1)

off

CONDITIONS

off

on; PALplus mode with helper set-up 400 mV
and black set-up 200 mV; note 1

FCO

MODE

not active

active

ACL

COLOUR LIMITING

not active

active

CENTRE FREQUENCY

1.1

BPS

DELAY LINE MODE

active

bypassed

GAI1

GAI0

GAIN SETTING

1 dB

0 dB

+1 dB

+2 dB

YD0 to YD3

Y-DELAY

YD3

160 ns

YD2

160 ns

YD1

80 ns

YD0

40 ns

FORF

FORS

FIELD FREQUENCY

auto (60 Hz when line not
synchronized)

forced 60 Hz; note 1

keep last detected field frequency

auto (50 Hz when line not
synchronized)

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

Table 23 Video switch control

Notes

1. When bit ECMB = 1 the subcarrier frequency is present on pin 30. The YCF and CCF signals coming from the comb

filter are only switched on when a signal is received that can be combed.

2. X = don't care.

3. AUTO YC means the decoder switches between CVBS and Y/C depending on the presence of the burst signal on

these signals.

4. AUTO COMB means the decoder switches to Y/C mode if the burst is present on the C input and to the comb filter

output if the burst is present on the CVBS signal.

ECMB

(1)

DEC3

DEC2

DEC1

DEC0

SELECTED SIGNAL

SIGNAL TO COMB

(2)

CVBS

int

CVBS

int

CVBS1

CVBS2

CVBS3

Y3/C3

Y3 + C3

CVBS4

Y4/C4

Y4 + C4

AUTO Y3/C3; note 3

CVBS3 or Y3 + C3

AUTO Y4/C4; note 3

CVBS4 or Y4 + C4

(2)

YCF/CCF

CVBS

int

YCF/CCF

CVBS1

YCF/CCF

CVBS2

YCF/CCF

CVBS3

YCF/CCF

CVBS4

AUTO COMB3; note 4

CVBS3 or Y3 + C3

AUTO COMB4; note 4

CVBS4 or Y4 + C4

Table 24 Video switch outputs

Table 25 Enable YUV input (on RGB1 input)

Table 26 External RGB clamp mode

TXT2

PIP2

TXT1

PIP1

TXT0

PIP0

OUTPUT SIGNAL TXT

OUTPUT SIGNAL PIP

CVBS

int

CVBS1

CVBS2

CVBS3

Y3 + C3

CVBS4

Y4 + C4

YUV

MODE

RGB1 input active

YUV input active

ECL

MODE

off; internal clamp pulse used

on; external clamp pulse has to be supplied to
pin HA/CLP

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

Table 27 Enable fast blanking RGB1

Table 28 Enable fast blanking RGB2

Table 29 Output switches OS0 and OS1

Table 30 Fast filter IF-PLL

Table 31 IF circuit not active

Table 32 Group delay correction

Table 33 Modulation standard

Table 34 AFC window

Table 35 IF sensitivity

Table 36 Search tuning mode

Table 37 Video mute

Table 38 PLL demodulator frequency shift

IE1

FAST BLANKING

not active

active

IE2

FAST BLANKING

not active

active

OS0;

OS1

CONDITIONS

output = LOW

output = HIGH

FFI

CONDITIONS

normal time constant

fast time constant

IFO

MODE

normal operation of IF amplifier

IF amplifier switched off

GROUP DELAY CHARACTERISTIC

flat

according to BG standard

MOD

MODULATION

negative

positive

AFW

AFC WINDOW

normal

enlarged

IFS

IF SENSITIVITY

normal

reduced

STM

MODE

normal operation

reduced sensitivity of video ident circuit

VSW

STATE

normal operation

VIF signal switched off

L'FA

MODE

normal IF frequency

frequency shift for L' standard

Table 39 Output status bits

Note

1. X = don't care.

FUNCTION

SUBADDRESS

(HEX)

DATA BYTE

Output status bytes

POR

(1)

SNR

FSI

IVW

CD3

CD2

CD1

CD0

SXD

SXC

SXB

SXA

IN1

IN2

CMB

S2A

S2B

S1A

S1B

ID3

ID2

ID1

ID0

IFI

AFA

AFB

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

UTPUT CONTROL BITS

Table 40 Power-on reset

Table 41 Signal-to-noise ratio of sync signal

Table 42 Field frequency indication

Table 43 Phase 1 (

) lock indication

Table 44 Condition vertical divider

Table 45 Crystal indication (SXA to SXD)

POR

MODE

normal

power-down

SNR

SIGNAL-TO-NOISE RATIO

S/N > 20 dB

S/N < 20 dB

FSI

FREQUENCY

50 Hz

60 Hz

INDICATION

not locked

locked

IVW

STANDARD VIDEO SIGNAL

no standard video signal

standard video signal in `narrow window' or
standard TV norm (525 or 625 lines)

SXA to

SXD

CONDITIONS

no crystal connected

crystal connected

Table 46 Colour decoder mode

Note

1. This mode is generated when trying (e.g. via software control) to force the decoder to a standard with a crystal which

is not connected to the IC.

CD3

CD2

CD1

CD0

STANDARD

XTAL

no colour standard identified

A/B/C/D

NTSC

PAL

NTSC

PAL

NTSC

PAL

NTSC

PAL

SECAM

illegal forced mode; note 1

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

Table 47 Indication RGB1/RGB2 insertion

Table 48 Condition YCF/CCF inputs from comb filter

Table 49 Input signal condition; note 1

Note

1. During the search mode for the colour system, bit YC

will indicate logic 1.

Table 50 Condition of AV1 and AV2 inputs

Table 51 Output video identification

Table 52 In-lock indication IF-PLL

Table 53 AFC output

Table 54 IC version indication

IN1;

IN2

RGB INSERTION

no insertion

full insertion

CMB

CONDITION YCF/CCF INPUTS

not selected

selected

CONDITIONS

CVBS signal available

Y/C signal available

S1A;

S2A

S1B;

S2B

CONDITIONS

no external source

external source with 4 : 3 input
signal

external source with 16 : 9 input
signal

IFI

VIDEO SIGNAL

no video signal identified

video signal identified

CONDITIONS

PLL not locked

PLL locked

AFA

AFB

CONDITIONS

outside window; too low

outside window; too high

in window; below reference

in window; above reference

ID3

ID2

ID1

ID0

IC TYPE

TDA9321HN1

TDA9321HN2

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).

Notes

1. All pins are protected against ESD by means of internal clamping diodes.

2. Human Body Model (HBM): R = 1.5 k

; C = 100 pF.

3. Machine Model (MM): R = 0

; C = 200 pF.

THERMAL CHARACTERISTICS

QUALITY SPECIFICATION

Quality specification in accordance with

"SNW-FQ-611E".

Latch-up performance

At an ambient temperature of 70

C all pins meet the following specification:

Positive stress test: I

trigger

100 mA or V

1.5

P(max)

Negative stress test: I

trigger

100 mA or V

0.5

P(max)

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

supply voltage on pins V

and V

9.0

stg

storage temperature

+150

amb

operating ambient temperature

sld

soldering temperature

for 5 s

260

junction temperature

150

electrostatic handling on all pins

notes 1 and 2

3000

+3000

notes 1 and 3

300

+300

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th(j-a)

thermal resistance from junction to ambient

in free air

K/W

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

CHARACTERISTICS
V

= 8 V; T

amb

= 25

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply (pins V

and V

); note 1

supply voltage (pins V

and V

)

7.2

8.0

8.8

supply current (pins V

and V

)

120

140

tot

total power dissipation

960

Vision IF circuit

ISION

AMPLIFIER INPUTS

(

PINS

VIF1

AND

VIF2)

i(rms)

input sensitivity (RMS value)

note 2

i(VIF)

= 38.90 MHz

200

i(VIF)

= 45.75 MHz

200

i(VIF)

= 58.75 MHz

200

i(max)(rms)

maximum input signal (RMS value)

150

200

i(dif)

differential input resistance

note 3

i(dif)

differential input capacitance

note 3

voltage gain control range

PLL

DEMODULATOR

(PLL

FILTER ON PIN

VIFPLL); note 4

PLL

PLL frequency range

MHz

cr(PLL)

PLL catching range

2.0

2.7

3.3

MHz

acq(PLL)

PLL acquisition time

VCO

VCO frequency dependency with
temperature

notes 5 and 6

300

kHz/K

tune(VCO)

VCO tuning frequency range

via I

C-bus

3.0

3.7

4.2

MHz

DAC

frequency variation per step of the
DAC (A0 to A6)

kHz

shift

frequency shift

with bit L'FA

5.5

MHz

IDEO AMPLIFIER OUTPUT

(

VIFO); note 7

o(z)

zero signal output level

note 8

negative modulation

4.6

4.7

4.8

positive modulation

1.9

2.0

2.1

o(ts)

top-sync level

negative modulation

1.9

2.0

2.1

o(w)

white level

positive modulation

4.4

4.5

4.6

difference in amplitude between
negative and positive modulation

o(v)

video output impedance

bias(int)

internal bias current of NPN
emitter follower output transistor

1.0

source(max)

maximum source current

3dB)

3 dB bandwidth of demodulated

output signal

MHz

dif

differential gain

note 9

1.5

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

dif

differential phase

notes 6 and 9

2.5

deg

vid

video non-linearity

note 10

clamp

white spot clamping level

6.0

clamp

noise inverter clamping level

note 11

1.5

ins

noise inverter insertion level
(identical to black level)

note 11

2.7

blue

intermodulation at `blue'

notes 6 and 12

f = 0.92 or 1.1 MHz

f = 2.66 or 3.3 MHz

yellow

intermodulation at `yellow'

notes 6 and 12

f = 0.92 or 1.1 MHz

f = 2.66 or 3.3 MHz

S/N

weighted signal-to-noise ratio

notes 6 and 13

S/N

unweighted signal-to-noise ratio

notes 6 and 13

residual carrier signal

note 6

5.5

rc(2H)

2nd harmonic of residual carrier
signal

note 6

2.5

PSRR

power supply ripple rejection

at the output

VIF

AND TUNER

AGC; note 14

Timing of VIF-AGC with a 2.2

F capacitor (pin DEC

VIF

)

MVI

modulated video interference

60% AM for 1 to 100 mV;
0 to 200 Hz; system B/G

res

response time

VIF input signal amplitude
increase of 52 dB; positive
and negative modulation

VIF input signal amplitude
decrease of 52 dB

negative modulation

positive modulation

100

leakage current of the capacitor on
pin 4

negative modulation

positive modulation

200

o(v)

change in video output signal
amplitude over 1 vertical period for
peak white AGC at positive
modulation

capacitor on pin 4 is 0.5

Tuner takeover point adjustment (via I

C-bus)

strt(min)(rms)

minimum start level (RMS value)

0.4

0.8

strt(max)(rms)

maximum start level (RMS value)

100

150

max

maximum variation with
temperature

amb

= 0 to 70

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

Tuner control output (pin TAGC)

o(max)

maximum output voltage

maximum tuner gain; note 3

o(sat)

output saturation voltage

minimum tuner gain;
I

= 2 mA

300

o(max)

maximum output current swing

leakage current

for RF AGC

input signal variation

for complete tuner control

0.5

AFC

OUTPUT

(

VIA

C-

BUS

); note 15

RES

AFC

AFC resolution

bits

window sensitivity

normal window mode

kHz

enlarged window mode

175

195

270

kHz

IDEO IDENTIFICATION OUTPUT

(

VIA

C-

BUS

)

delay time

for identification after the
AGC has stabilized on a new
transmitter

Sound IF circuit

OUND

AMPLIFIER

(

PINS

SIF1

AND

SIF2)

i(rms)

input sensitivity (RMS value)

FM mode (

3 dB)

100

140

AM mode (

3 dB)

200

300

i(max)(rms)

maximum input signal (RMS value) FM mode

AM mode

140

i(dif)

differential input resistance

note 3

i(dif)

differential input capacitance

note 3

voltage gain control range

ct(SIF-VIF)

crosstalk between inputs SIF
and VIF

QSS

AND

SOUND OUTPUT

(

QSS/AM)

General

output resistance

250

DC output voltage

3.3

bias(int)

internal bias current of emitter
follower

0.7

1.0

sink(max)

maximum AC and DC sink current

0.7

source(max)

maximum AC and DC source
current

2.0

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

QSS output signal

o(rms)

output signal amplitude
(RMS value)

SC1 on; SC2 off

110

3dB

3 dB bandwidth

7.5

MHz

r(SC)(rms)

residual IF sound carrier
(RMS value)

S/N

weighted signal-to-noise ratio
(SC1/SC2)

ratio of PC/SC1 at VIF input
of 40 dB or higher; note 16

black picture

53/48

58/55

white picture

52/47

55/53

6 kHz sine wave
(black-to-white modulation)

44/42

48/46

250 kHz sine wave
(black-to-white modulation)

44/25

48/30

SC subharmonics
(f = 2.75 MHz

3 kHz)

45/44

51/50

SC subharmonics
(f = 2.87 MHz

3 kHz)

46/45

52/51

AM output signal

o(rms)

output signal amplitude
(RMS value)

54% modulation

500

600

700

THD

total harmonic distortion

0.5

1.0

3dB

3 dB bandwidth

100

125

kHz

S/N

weighted signal-to-noise ratio

Video switches and comb filter interface

IDEO SWITCHES FOR

CVBS, Y

AND

SIGNALS

Signal on pins CVBS

int

, CVBS1, CVBS2, CVBS/Y3 and CVBS/Y4

i(n)(p-p)

input voltage (peak-to-peak value)

note 17

1.0

1.43

i(n)

input current

source(max)

maximum source impedance

1.0

sup(n)

suppression of non-selected
signals

= 0 to 5 MHz; note 6

Signal on pins C3 and C4

i(n)(p-p)

input voltage (peak-to-peak value)

notes 3 and 18

0.3

1.0

i(n)

input impedance

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

Signal on pin CVBSTXT

o(p-p)

output signal amplitude
(peak-to-peak value)

1.6

2.0

2.4

black level

2.6

black level dependency with
temperature

mV/K

output impedance

250

Signal on pin CVBSPIP

o(p-p)

output signal amplitude
(peak-to-peak value)

0.8

1.0

1.2

black level

3.6

black level dependency with
temperature

mV/K

output impedance

250

OMB FILTER INTERFACE

; note 19

Signal on pin CVBSCF

o(p-p)

output signal amplitude
(peak-to-peak value)

0.8

1.0

1.2

output impedance

250

black level

3.6

black level dependency with
temperature

mV/K

Signal on pin YCF

i(p-p)

input voltage (peak-to-peak value)

1.0

1.43

input current

Signal on pin CCF

input voltage

burst amplitude

0.3

1.0

input impedance

Reference signal output (pin REFO); note 20

o(p-p)

output signal amplitude
(peak-to-peak value)

= 15 pF

0.2

0.25

0.3

O(en)

DC output level to enable
comb filter

4.0

4.2

4.6

O(dis)

DC output level to disable comb
filter

0.1

1.4

Switching levels of SYS1 and SYS2 outputs (pins SYS1 and SYS2); note 21

HIGH-level output voltage

4.0

5.0

5.5

LOW-level output voltage

0.1

0.4

o(sink)

output sink current

o(source)

output source current

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

ETECTION OF STATUS LEVELS OF

SCART

PLUG PIN

8; note 22

det(int-ext)

detection voltage between internal
and external (16 : 9) source

2.0

2.2

2.4

det(ext-ext)

detection voltage between external
(16 : 9) and external (4 : 3) source

5.3

5.5

5.7

input resistance

100

Chrominance and luminance filters and delay lines

HROMINANCE TRAP CIRCUIT

; note 23

trap

trap frequency

osc

MHz

during SECAM reception

4.3

1.5%

MHz

3dB

3 dB bandwidth

= 3.58 MHz

2.6

2.8

3.0

MHz

= 4.43 MHz

3.2

3.4

3.6

MHz

during SECAM reception

2.9

3.1

3.3

MHz

CSR

colour subcarrier rejection

HROMINANCE BAND

PASS CIRCUIT

centre frequency

bit CB = 0

osc

MHz

bit CB = 1

1.1f

osc

MHz

band-pass quality factor

LOCHE FILTER

centre frequency

4.26

4.29

4.31

MHz

bandwidth

241

268

295

kHz

Y-

DELAY LINE

delay time

bits YD3 to YD0 = 1011;
note 6

crystal A

490

520

550

crystal B, C or D

530

560

590

d(tr)

tuning range delay time

with respect to 520/560 ns;
12 settings; see Table 13

280

+160

bandwidth

note 6

MHz

ROUP DELAY CORRECTION

(

PINS

GDI

AND

GDO); note 24

i(GDI)(p-p)

input signal amplitude on pin GDI
(peak-to-peak value)

2.0

i(GDI)

input current on pin GDI

0.1

1.0

o(GDO)(p-p)

output signal amplitude on
pin GDO (peak-to-peak value)

1.8

2.0

2.2

o(GDO)

output top-sync level on pin GDO

2.4

o(GDO)

top-sync level on pin GDO
variation with temperature

mV/K

o(GDO)

output impedance on pin GDO

250

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

Colour demodulation part

HROMINANCE AMPLIFIER

ACC

ACC control range

note 25

o(CRACC)

change in amplitude of the output
signals over CR

ACC

ck(on)

threshold colour killer ON

colour killer from OFF to ON

hys

ck(off)

hysteresis colour killer OFF

note 6

strong signal; S/N

40 dB

noisy input signals

ACL

CIRCUIT

; note 26

C/C

ACL

ACL chrominance burst ratio

when the ACL starts to
operate

3.0

EFERENCE PART

Phase-locked loop; note 27

catching range

360

600

phase shift

for a

400 Hz deviation of the

oscillator frequency; note 6

deg

Oscillator

fosc

temperature coefficient of oscillator
frequency

note 6

Hz/K

osc

oscillator frequency variation with
respect to the supply voltage

= 8 V

10%; note 6

neg(min)

minimum negative resistance

1.0

L(max)

maximum load capacitance

UE CONTROL

; note 28

hue

hue control range

63 steps; see Fig.4

deg

hue/

hue dependency with respect to
the supply voltage

10%; note 6

deg

hue/

hue dependency with temperature

amb

= 0 to 70

C; note 6

deg

EMODULATORS

General

spread of signal amplitude ratio
between standards

note 6

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

PAL/NTSC demodulator

(B-Y)(R-Y)

gain between both demodulators
(B

Y) and (R

1.60

1.78

1.96

3dB(dem)

3 dB bandwidth of demodulators

note 29

650

kHz

o(rc)(p-p)

residual carrier output
(peak-to-peak value)

f = f

osc

; (R

Y) output

f = f

osc

; (B

Y) output

f = 2f

osc

; (R

Y) output

f = 2f

osc

; (B

Y) output

H/2(p-p)

H/2 ripple rejection (peak-to-peak
value)

at (R

Y) output

output voltage variation with
temperature

note 6

0.1

%/K

output voltage variation with
respect to the supply voltage

note 6

0.3

dB/V

phase error in the demodulated
signals

note 6

deg

SECAM demodulator

blos

black level offset frequency

kHz

blos

black level offset frequency
variation with temperature

Hz/K

pole frequency of de-emphasis

kHz

ratio pole and zero frequency

non-linearity

cal

calibration voltage

Baseband delay line

variation of output signal

for adjacent time samples at
constant input signals

0.1

r(clk)(p-p)

residual clock signal (peak-to-peak
value)

delay

delayed signal

63.94

64.0

64.06

non-delayed signal

difference in output amplitude

when delay line is bypassed
or not (with bit BPS)

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

PALplus helper demodulator

o(helper)(p-p)

helper output voltage
(peak-to-peak value)

610

686

770

su(helper)

helper set-up amplitude

only helper lines 22 and 23

380

400

420

d(g)

group delay

within pass band

e(dem)

demodulation phase error

including H/2 phase error

deg

sup

suppression

for modulated helper in
demodulated 0 to 1 MHz
signal

residual signal

at 4.43 MHz signal

THD

total harmonic distortion

in ACC

o(helper-Y)

helper output timing to Y output

offset

offset voltage

for demodulated mid grey to
inserted mid grey level;
mid grey line 23 to line 22

W(su)(helper)

helper set-up pulse width

52.8

delay between mid sync of input
and start of helper set-up

bits YD3 to YD0 = 1011;
note 30

8.6

delay between start of black set-up
and start of helper set-up

only lines 22 and 23

30.8

helper(

3dB)

3 dB bandwidth of helper

baseband

2.6

MHz

RGB switch and YUV switch

RGB

SWITCH

(

PINS

RI1

BI1

AND

RI2

BI2)

i(p-p)

input signal amplitude
(peak-to-peak value)

0.7

1.0

source(max)

maximum source impedance

1.0

bl(int-ext)

difference between black level of
internal and external signals at the
outputs

input current

no clamping; note 3

0.1

delay difference between the three
channels

note 6

SYMBOL

PARAMETER

CONDITIONS

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TYP.

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2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

YUV

INPUTS

(

WHEN ACTIVATED

)

i(Y)(p-p)

Y input signal amplitude
(peak-to-peak value)

1.0

i(U)(p-p)

U input signal amplitude
(peak-to-peak value)

1.33

i(V)(p-p)

V input signal amplitude
(peak-to-peak value)

1.05

source(max)

maximum source impedance

1.0

bl(int-ext)

difference between black level of
internal and external signals at the
outputs

input current

no clamping; note 3

0.1

AST BLANKING

(

PINS

RGB1

AND

RGB2)

input voltage

no data insertion

0.4

data insertion

0.9

i(max)

maximum input pulse

3.5

input current

0.2

d(blank-RGB)

delay difference between blanking
and RGB signals

note 6

tbf

sup(int)

suppression of internal YUV
signals

data insertion;
f

= 0 to 5 MHz; note 6

sup(ext)

suppression of external RGB
signals

no data insertion;
f

= 0 to 5 MHz; note 6

d(blank-YUV)

delay between blanking input and
YUV outputs

tbf

UMINANCE OUTPUT

(

YO); note 31

o(p-p)

output signal amplitude
(peak-to-peak value)

black-to-white

1.0

output voltage during PALplus

black-to-white

0.8

bl(YUV-RGB)

difference in black level between
YUV and RGB mode

output impedance

250

output DC voltage level

black level

2.8

3.0

3.2

RGB(

3dB)

3 dB bandwidth of the RGB

switch circuit

MHz

S/N

signal-to-noise ratio

= 0 to 5 MHz

su(bl)

black set-up amplitude

bit MACP = 1 or bit HD = 1

190

200

210

W(su)(bl)

black set-up pulse width

52.8

delay between mid sync at input
and black set-up

note 30

8.8

offset

offset voltage

to re-inserted black

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

(Y/CVBS-YO)

gain from internal Y/CVBS to YO

1.35

1.43

1.50

bit MACP = 1 or bit HD = 1

1.08

1.14

1.20

AND

SIGNAL OUTPUTS

(

PINS

AND

VO)

o(VO)(p-p)

output voltage on pin VO
(peak-to-peak value)

standard EBU colour bar

0.88

1.05

1.25

o(UO)(p-p)

output voltage on pin UO
(peak-to-peak value)

standard EBU colour bar

1.12

1.33

1.58

output impedance

250

output DC voltage level

2.2

2.4

2.6

bl(YUV-RGB)

difference in black level between
YUV and RGB mode

OLOUR

ATRIX FROM

RGB

YUV

gain

from RI to YO

0.40

0.43

0.46

from GI to YO

0.79

0.84

0.90

from BI to YO

0.15

0.16

0.17

from RI to UO

0.40

0.43

0.46

from GI to UO

0.79

0.84

0.90

from BI to UO

1.19

1.27

1.35

from RI to VO

0.94

1.00

1.07

from GI to VO

0.79

0.84

0.90

from BI to VO

0.15

0.16

0.17

Horizontal and vertical synchronization

YNC VIDEO INPUTS

sync

sync pulse amplitude

note 3

300

350

hor

slicing level for horizontal sync

note 32

vert

slicing level for vertical sync

note 32

ORIZONTAL OSCILLATOR

free-running frequency

15625

spread on free-running frequency

frequency dependency with
respect to the supply voltage

= 8.0 V

10%; note 6

0.2

0.5

max

frequency variation with
temperature

amb

= 0 to 70

C; note 6

IRST CONTROL LOOP

(

PH1LF); note 33

hr(PLL)

PLL holding range

0.9

1.2

kHz

cr(PLL)

PLL catching range

note 6

0.6

0.9

kHz

S/N

signal-to-noise ratio

for the video input signal at
which the time constant is
switched

hys

hysteresis at the switching point

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

sigma value of phase jitter

in automatic mode;

ORIZONTAL PULSE OUTPUT AND CLAMP PULSE INPUT

OUTPUT

(

HA/CLP)

Switched to HA output (bit HO = 1)

HIGH-level output voltage

o(source)

= 2 mA

4.0

5.0

5.5

LOW-level output voltage

o(sink)

= 2 mA

0.2

0.4

o(sink)

output sink current

o(source)

output source current

pulse width

at nominal horizontal
frequency

4.6

4.7

4.8

delay between mid sync of input
and mid HA pulse

note 30

0.3

0.45

0.6

Switched to CLP output (bit HO = 0)

pulse width

at nominal horizontal
frequency

3.5

3.6

3.7

delay between start of CLP pulse
to start of black set-up

bit HD = 1 or bit MACP = 1;
bits YD3 to YD0 = 1011; at
nominal horizontal frequency

5.2

5.3

5.4

delay between mid sync of input
and start CLP pulse

note 30

3.0

3.2

3.4

Switched to CLP input (bit ECL = 1)

LOW-level input voltage

0.6

HIGH-level input voltage

2.4

5.5

W(clamp)

clamping pulse width

1.8

3.5

(clamp)(n)

clamping offset between pins UO
and VO

input impedance

ERTICAL OSCILLATOR

; note 34

free-running frequency

50 Hz mode

60 Hz mode

lock

frequency locking range

64.5

D/D

divider ratio

not locked

625/525

lines

locking range

488

722

lines/
frame

ERTICAL PULSE OUTPUT

(

VA)

HIGH-level output voltage

o(source)

= 2 mA

4.0

5.0

5.5

LOW-level output voltage

o(sink)

= 2 mA

0.2

0.4

o(sink)

output sink current

o(source)

output source current

pulse width

= 50 Hz

2.5

lines

= 60 Hz

3.0

lines

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

Notes to the characteristics

1. The two supply pins V

and V

must be decoupled separately but they must be connected to a single power supply

to avoid too big differences between them.

2. On set AGC.

3. This parameter is not tested during production and is just given as application information for the designer of the

television receiver.

delay between start of vertical sync
of input and positive edge of
vertical pulse on pin VA

note 35

37.7

output impedance

bit ECL = 1

ANDCASTLE OUTPUT

(

SCO)

General

zero level voltage

0.5

1.0

o(sink)

output sink current

0.5

Horizontal/vertical blanking

output voltage level

2.2

2.5

2.8

o(source)

output source current

0.7

W(h)

horizontal blanking pulse width

delay between start horizontal
blanking and start clamping pulse

6.4

Clamping pulse

output voltage level

4.2

4.5

4.8

o(source)

output source current

0.7

pulse width

3.6

delay between mid sync of input
and start of clamping pulse

note 30

3.0

3.2

3.4

C-bus control

SCL

AND

SDA

INPUTS

OUTPUTS

(

PINS

SCL

AND

SDA)

input voltage range

5.5

LOW-level input voltage

1.5

HIGH-level input voltage

3.5

LOW-level input current

= 0 V

HIGH-level input current

= 5.5 V

OL(SDA)

LOW-level output voltage on
pin SDA

OL(SDA)

= 3 mA

0.4

SW0

AND

SW1

OUTPUTS

(

PINS

SW0

AND

SW1); note 36

HIGH-level output voltage

4.0

5.0

5.5

LOW-level output voltage

0.2

0.4

O(sink)

output sink current

O(source)

output source current

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

4. Loop filter bandwidth B

lpf

= 60 kHz (natural frequency f

= 15 kHz; damping factor d = 2; calculated with top sync

level as f

PLL

input signal level). LC-VCO circuit between pins 7 and 8: Q

= 60; C

int

= 30 pF.

5. The optimum temperature stability of the PLL can be obtained when a TOKO coil as given in Table 55 is applied.

6. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix

batches which are made in the pilot production period.

7. Measured at 10 mV (RMS) top sync input signal.

8. So called projected zero point, i.e. with switched demodulator.

9. Measured in accordance with the test line given in Fig.5. For the differential phase test the peak white setting is

reduced to 87%.

The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and
smallest value relative to the subcarrier amplitude at blanking level.

The differential phase is defined as the difference in degrees between the largest and smallest phase angle.

10. This figure is valid for the complete video signal amplitude (peak white-to-black). See Fig.6.

11. The noise inverter is only active in the `strong signal mode' (no noise detected in the incoming signal).

12. The input conditions and test set-up are given in Figs 8 and 9. The figures are measured with an input signal of

10 mV (RMS).

13. Measured at an input signal of 10 mV (RMS). The S/N is the ratio of black-to-white amplitude with respect to the black

level noise voltage (RMS value). B = 5 MHz. Weighted in accordance with CCIR 567.

14. The AGC response time also depends on the acquisition time of the PLL demodulator. The values given are valid

when the PLL is in lock.

15. The AFC control voltage is obtained from the control voltage of the VCO of the PLL demodulator. The tuning

information is supplied to the tuning system via the I

C-bus. Two bits are reserved for this function. The AFC value

is valid only when bit PL = 1.

16. The weighted S/N ratio is measured under the following conditions:

a) The VIF modulator must meet the following specifications:

Incidental phase modulation for black-to-white jumps less than 0.5 degrees.

QSS AF performance, measured with the television-demodulator AMF2 (audio output, weighted S/N ratio)
better than 60 dB (deviation 27 kHz) for 6 kHz sine wave black-to-white modulation.

Picture-to-sound carrier ratio: PC/SC1 = 13 dB (transmitter).

b) The measurements must be carried out with the Siemens SAW filters G3962 for VIF and G9350 for SIF.

Input level for SIF at 10 mV (RMS) with 27 kHz deviation.

c) The PC/SC ratio at the VIF input is calculated as the addition of the TV transmitter ratio and the SAW filter PC/SC

ratio. This PC/SC ratio is necessary to achieve the S/N

values as indicated.

17. Signal with negative-going sync. Amplitude includes sync pulse amplitude.

18. Indicated is a signal for a colour bar with 75% saturation (chrominance to burst amplitude ratio = 2.2 : 1).

19. When a signal is identified which can be combed (correct combination of colour standard and reference crystal) the

comb filter is switched to that mode via pins 25 and 27 and then the filter is activated by switching on the reference
carrier signal and connecting the output signals of the comb filter (pins 28 and 29) to the video processing circuits.

20. The subcarrier output signal can be used as a reference signal for external comb filter ICs (e.g. SAA4961). When

bit ECMB = 0 the subcarrier signal is suppressed and the DC level is LOW. When bit ECMB = 1 the output level is
HIGH and the subcarrier signal is present.

21. The outputs SYS1 and SYS2 can be used to switch the comb filter to the different colour standards (e.g. PAL-M,

PAL-N, PAL-B/G and NTSC-M) and are controlled by the colour decoder identification circuit.

The setting of the outputs for the various standards is given in Table 56.

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

22. For the detection of the status of the incoming SCART signal a voltage divider with a ratio of 2 : 3 has to be connected

between pin 8 of the SCART plug and the detection input. The impedance of the voltage divider should not be too
high-ohmic because of the input impedance of 100 k

23. When the decoder is forced to a fixed subcarrier frequency (via bits XA to XD or bit CM) the chrominance trap is

always switched on, also when no colour signal is identified. When 2 crystals are active the chrominance trap is
switched off if no colour signal is identified.

24. The typical group delay characteristic for the B/G standard is given in Fig.7.

25. At a chrominance input voltage of 660 mV (p-p) [colour bar with 75% saturation i.e. burst signal amplitude

300 mV (p-p)] the dynamic range of the ACC is +6 and

20 dB.

26. The ACL function can be activated by bit ACL. The ACL circuit reduces the gain of the chrominance amplifier for input

signals with a C/C

ACL

which exceeds a value of 3.0.

27. All frequency variations are referenced to 3.58 or 4.43 MHz carrier frequency. All oscillator specifications are

measured with the Philips crystal series 9922 520 with a series capacitance C

= 18 pF. The oscillator circuit is rather

insensitive to the spurious responses of the crystal. As long as the resonance resistance of the third overtone is
higher than that of the fundamental frequency the oscillator will operate at the correct frequency. The typical crystal
parameters for the crystal series are:

a) Load resonance frequencies f

: 4.433619, 3.579545, 3.582056 and 3.575611 MHz; C

= 20 pF.

b) Motional capacitance C

mot

= 20.6 fF (4.43 MHz crystal) or C

mot

= 14.7 fF (3.58 MHz crystal).

c) Parallel capacitance C

= 5.0 pF.

The minimum detuning range can only be specified if both the IC and the crystal tolerances are known and therefore
the figures regarding catching range are only valid for the specified crystal series. In this figure tolerances of the
crystal with respect to the nominal frequency, motional capacitance and ageing have been taken into account and
have been counted for gaussic addition. Whenever different typical crystal parameters are used the following
equation might be helpful for calculating the impact on the tuning capabilities:

Detuning range =

The resulting detuning range should be corrected for temperature shift and supply voltage deviation of both the IC
and the crystal. To guarantee a catching range of

300 Hz on 4.43 MHz the minimum motional capacitance of the

crystal must have a value 13.2 fF or higher. For a catching range of 250 Hz with the 3.58 MHz crystal the minimum
motional capacitance must have a value of 9 fF.
Note: SMD-type crystals do not fulfil these requirements.
The actual series capacitance in the application should be C

= 18 pF to account for parasitic capacitances on-chip

and off-chip.

28. The hue control is active for NTSC on the demodulated colour difference signals and for PALplus on the demodulated

helper signal.

29. This parameter indicates the bandwidth of the complete chrominance circuit including the chrominance band-pass

filter. The bandwidth of the low-pass filter of the demodulator is approximately 1 MHz.

30. This delay is partially caused by the low-pass filter at the sync separator input.

31. The internal luminance signal (signal which is derived from the incoming CVBS or Y/C signals) has a separate gain

control setting (controlled by the I

C-bus bits GAI1 and GAI0 and with a gain variation between

1 and +2 dB) which

can be used to get an optimal input signal amplitude for the feature box.

32. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing

level and the black level (back porch). When the amplitude of the sync pulse exceeds the value of 350 mV the sync
separator will slice the sync pulse at a level of 175 mV above top sync. The maximum sync pulse amplitude is 4 V
(peak-to-peak value).

mot

-------

-------------------------

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

33. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is

switched depending on the input signal condition and the condition of the I

C-bus. Therefore the circuit contains a

noise detector and the time constant is switched to the slow mode when too much noise is present in the signal. In the
fast mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to
head-switching of the VCR are corrected as soon as possible. Switching between the two modes can be automatic
or overruled by the I

C-bus.

The circuit contains a video identification circuit which is independent of the first control loop. This identification circuit
can be used to close or open the first control loop when a video signal is present or not present on the input. This
enables a stable On Screen Display (OSD) when just noise is present at the input. The coupling of the video
identification circuit with the first control loop can be revoked via the I

C-bus.

To prevent the horizontal synchronization being disturbed by anti copy signals such as Macrovision the phase
detector is gated during the vertical retrace period from line 11 to 17 (60 Hz signal) or from line 11 to 22 (50 Hz
signal) so that pulses during scan have no effect on the output voltage. The width of the gate pulse is approximately
22

s. During weak signal conditions (noise detector active) the gating is active during the complete scan period and

the width of the gate pulse is reduced to 5.7

s so that the effect of noise is reduced to a minimum.

The output current of the phase detector in the various conditions is shown in Table 57.

34. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit.

This divider circuit has 3 modes of operation:

a) Search mode large window.

This mode is switched on when the circuit is not synchronized or when a non-standard signal [number of lines
per frame outside the range between 311 and 314 (50 Hz mode) or between 261 and 264 (60 Hz mode)] is
received. In the search mode the divider can be triggered between line 244 and line 361 (approximately
43.3 to 64.5 Hz).

b) Standard mode narrow window.

This mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window.
When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp
generator is started at the end of the window. Consequently, the disturbance of the picture is very small.
The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are
found within the window.

c) Standard TV-norm [divider ratio 525 (60 Hz) or 625 (50 Hz)].

When the system is switched to the narrow window a check is performed to establish whether the incoming
vertical sync pulses are in accordance with the TV-norm. When 15 standard TV-norm pulses are counted the
divider system is switched to the standard divider ratio mode. In this mode the divider is always reset at the
standard value even if the vertical sync pulse is missing.

When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this
window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window.

The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of the
divider is required during channel-switching the system can be forced to the search window by means of bit NCIN in
subaddress 06.

35. The delay between the positive edge of VA and the positive edge of CLP (

negative edge of HA) after VA is 32.0

for field 1 and 0

s for field 2. Especially for PALplus signals the regenerated VA pulses must have a fixed and known

phase relation to the undisturbed VA pulses of the incoming video signal. This relationship must remain correct as
long as the vertical divider is in the standard mode (indirect sync mode). Therefore the coincidence window used
here must be a half line window. With a well defined phase relationship of the generated VA pulses to the generated
HA pulses a correct field identification and all the required timing signals referring to a certain line in each frame can
be generated externally in the PALplus decoder environment.

36. Pins 19 and 22 are for general purpose outputs that can be used to switch external circuits e.g. sound traps, etc.

They are controlled via the I

C-bus by bits OS0 (pin 19) and OS1 (pin 22).

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

Table 55 Coil data for the VIF-PLL demodulator (approximated coil values)

Table 56 Switching conditions of pins SYS1 and SYS2

Table 57 Output current of the phase detector in the various conditions

Note

1. Only during vertical retrace, pulse width 22

s and provided that bit EMG = 1 and IVW readout bit = 1. In the other

FOA FOB conditions with gating, the pulse width is 5.7

s and the gating is continuous.

VIF

(MHz)

VCO

(MHz)

(nH)

TOKO SAMPLE NUMBER

REMARKS

38.9

77.8

150

P369INAS-159HM

5 mm; 5 km long; TC = 30

100 ppm/

45.75

91.5

100

P369INAS-160HM

58.75

117.5

P369INAS-161HM

COLOUR STANDARD

SYS1

SYS2

ACTIVE CRYSTAL

PAL-M

LOW

PAL-B, G, H, D and I

LOW

HIGH

NTSC-M

HIGH

LOW

PAL-N

HIGH

C-BUS COMMANDS

IC CONDITIONS

-1 CURRENT/MODE

VID

POC

FOA

FOB

IDENT

COIN

NOISE

SCAN

V-RETR

GATING

MODE

yes

180

270

yes

(1)

auto

yes

auto

yes

180

270

auto

yes

slow

yes

180

270

slow

yes

180

270

yes

fast

yes

slow

180

270

yes

(1)

fast

OSD

off

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

SOLDERING

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250

C. The top-surface temperature of the

packages should preferable be kept below 230

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint must
be placed at a 45

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE

SOLDERING METHOD

WAVE

REFLOW

(1)

HLQFP, HSQFP, HSOP, SMS

not suitable

(2)

suitable

PLCC

(3)

, SO

suitable

LQFP, QFP, TQFP

not recommended

(3)(4)

suitable

SQFP

not suitable

suitable

SSOP, TSSOP, VSO

not recommended

(5)

suitable

2000 Sep 25

Philips Semiconductors

Preliminary specification

C-bus controlled TV input processor

TDA9321H

DATA SHEET STATUS

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

DATA SHEET STATUS

PRODUCT

STATUS

DEFINITIONS

(1)

Objective specification

Development

This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.

Preliminary specification

Qualification

This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.

Product specification

Production

This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

DEFINITIONS

Short-form specification

The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition

Limiting values given are in

accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information

Applications that are

described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.

DISCLAIMERS

Life support applications

These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes

Philips Semiconductors

reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

PURCHASE OF PHILIPS I

C COMPONENTS

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Internet: http://www.semiconductors.philips.com

2000

Philips Semiconductors a worldwide company

For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773

Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700

Colombia: see South America

Czech Republic: see Austria

Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905

Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920

France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300

Hungary: see Austria

India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811

Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341

Pakistan: see Singapore

Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001

Portugal: see Spain

Romania: see Italy

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382

Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263

Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
Tel. +66 2 361 7910, Fax. +66 2 398 3447

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 3341 299, Fax.+381 11 3342 553

Printed in The Netherlands

753504/02/pp

Date of release:

2000 Sep 25

Document order number:

9397 750 07032

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA9321H/N1

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA9321H/N1