DATA SHEET
Product specification
Supersedes data of 1995 Mar 21
File under Integrated Circuits, IC02
1998 Jul 03
INTEGRATED CIRCUITS
TDA9840
TV and VTR stereo/dual sound
processor with digital identification
and I
2
C-bus control
1998 Jul 03
2
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
FEATURES
Supply voltage 5 to 8 V
De-emphasis
Source selector
Level and stereo matrix adjustment possible via the
I
2
C-bus
I
2
C-bus transceiver
AF inputs for NICAM or AM sound (standard L)
AF outputs for Main and SCART
AF input and output signals selectable via the I
2
C-bus
Information for identified transmission mode is readable
via I
2
C-bus
Software is compatible with the TDA8415/16/17
Quartz oscillator and clock generator
Three digital PLL, alignment-free
Two digital integrators, alignment-free
Stabilizer circuit for ripple rejection and constant output
signals
ESD protection of all pins.
GENERAL DESCRIPTION
The TDA9840 is a stereo/dual sound processor for TV and
VTR sets. Its identification ensures safe operation by using
internal digital PLL technique with extremely small
bandwidth, synchronous detection and digital integration
(switching time maximum 2.3 s; identification concerning
the main functions).
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TDA9840
DIP20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
TDA9840T
SO20
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
1998 Jul 03
3
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
P
supply voltage (pin 18)
4.5
5
8.8
V
I
P
supply current (pin 18)
15.5
16.5
20.5
mA
V
i(rms)
nominal input signal voltage (V
i 1
, V
i 2
, V
i 3
)
(RMS value)
54% modulation
-
250
-
mV
V
o(rms)
nominal output signal voltage (RMS value)
THD
0.3%
54% modulation
-
500
-
mV
V
o(rms)
clipping level of the output signal voltages
(RMS value)
THD
1.5%
V
P
= 5 V
1.4
1.6
-
V
V
P
= 8 V
2.4
2.65
-
V
G
v
stereo control range for V
i 1
(0.1 dB steps)
+2.4
+2.5
+2.6
dB
-
2.3
-
2.4
-
2.5
dB
level control range for V
i 2
(0.5 dB steps)
+2.4
+2.5
+2.6
dB
-
1.9
-
2.0
-
2.1
dB
V
i pil
input voltage sensitivity of pilot frequency
unmodulated
5
-
100
mV
S/N(W)
weighted signal-to-noise ratio
"CCIR468-3"
66
75
-
dB
THD
total harmonic distortion
-
0.2
0.3
%
T
amb
operating ambient temperature range
0
-
+70
C
f
ident
identification window width
normal mode
STEREO
2.0
-
2.0
Hz
DUAL
2.3
-
2.3
Hz
fast mode
STEREO
3.8
-
3.8
Hz
DUAL
5.8
-
5.8
Hz
t
ident(on)
total identification time ON
normal mode
STEREO
0.35
-
2.3
s
DUAL
0.35
-
2.0
s
fast mode
STEREO
0.175
-
1.1
s
DUAL
0.175
-
1.0
s
V
i tuner
identification voltage sensitivity
-
28
-
dB
V
f
pil
pull-in frequency range of pilot PLL
f
= 10.008 MHz
lower side
-
296
-
-
296
Hz
upper side
302
-
302
Hz
1998
Jul
03
4
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
BLOCK DIAGRAMS
a
ndbook, full pagewidth
TDA9840
mute
LEVEL AND
STEREO
ADJUSTMENT
DIGITAL
PLL
OSCILLATOR
V
i 1
DIGITAL PLL
AND
DEMODULATOR
DIGITAL PLL
AND
DEMODULATOR
DIGITAL
INTEGRATOR
DIGITAL
INTEGRATOR
GENERATION
OF
REFERENCE
VOLTAGES
I C-BUS
CONTROL
2
CONTROL
LOGIC
1
20
SCL
SDA
11
12
13
14
MAIN
SCART
500 mV RMS
500 mV RMS
500 mV RMS
500 mV RMS
5 k
5 k
15 17
9 10
10 nF
10 nF
10 k
10 k
40 k
40 k
7
8
250 mV RMS
(from 1st SC)
2.2
F
2.2
F
30 k
47 pF
3.3 nF
2.5 mH
100 nF
10
F
10 nF
5
4
2
3
25 k
25 k
V
ref
19
6 18
16
100
F /
16 V
10 MHz
DUAL bit
STEREO
bit
L
R/B
250 mV RMS
L/A/MONO
250 mV RMS
2.2
F
2.2
F
500 mV RMS
250 mV RMS
(from 2nd SC)
C
AGC
C
LP
C
DCL
C
D1
C
D2
1/2 V
GND
XTAL
P
V
i 2
V
i pil
V
o 1
V
i 3
V
i 4
V
o 2
V
o 3
V
o 4
0 to 4.5 dB
stereo
level
V
P
C
ref
10 k
-
2 dB
-
2 dB
0 to 4.5 dB
10 k
0 to
-
0.4 dB
A/MONO
6 dB
6 dB
6 dB
6 dB
25 k
25 k
25 k
25 k
POWER-ON
RESET
L+R
2
, A
R, B
5%
5%
Q
0
= 70
tan
0.002
MBE457
Input and output levels are nominal values.
They are related to the SCART norm.
(AM: m = 0.54, FM:
f =
27 kHz).
Fig.1 Block diagram of the bipolar TV/VTR-stereo decoder.
1998
Jul
03
5
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
Fig.2 Block diagram of the bipolar TV/VTR-stereo decoder with fixed coil (alignment-free).
o
k, full pagewidth
TDA9840
mute
LEVEL AND
STEREO
ADJUSTMENT
DIGITAL
PLL
OSCILLATOR
V
i 1
DIGITAL PLL
AND
DEMODULATOR
DIGITAL PLL
AND
DEMODULATOR
DIGITAL
INTEGRATOR
DIGITAL
INTEGRATOR
GENERATION
OF
REFERENCE
VOLTAGES
I C-BUS
CONTROL
2
CONTROL
LOGIC
1
20
SCL
SDA
11
12
13
14
MAIN
SCART
500 mV RMS
500 mV RMS
500 mV RMS
500 mV RMS
5 k
5 k
15
17
9 10
10 k
10 k
40 k
40 k
7
8
250 mV RMS
(from 1st SC)
2.2
F
2.2
F
27 k
180 pF
1.8 nF
2%
4.7 mH
5%
100 nF
10
F
10 nF
5
4
2
3
25 k
25 k
V
ref
19
6 18
16
100
F /
16 V
10 MHz
DUAL bit
STEREO
bit
L
R/B
250 mV RMS
L/A/MONO
250 mV RMS
2.2
F
2.2
F
500 mV RMS
250 mV RMS
(from 2nd SC)
C
AGC
C
LP
C
DCL
V
i 2
V
o 1
V
i 3
V
i 4
V
o 2
V
o 3
V
o 4
0 to 4.5 dB
stereo
level
V
P
C
ref
10 k
-
2 dB
-
2 dB
0 to 4.5 dB
10 k
0 to
-
0.4 dB
A/MONO
6 dB
6 dB
6 dB
6 dB
25 k
25 k
25 k
25 k
POWER-ON
RESET
L+R
2
, A
R, B
10 nF
C
D1
5%
10 nF
C
D2
5%
Q
0
= 25
tan
0.01
1/2 V
GND
XTAL
P
V
i pil
MBE458
Input and output levels are nominal values.
They are related to the SCART norm.
(AM: m = 0.54, FM:
f =
27 kHz).
The components of the external LC band-pass filter have the
following order-No.:
Philips Germany only No: 4312 020 17525 or Fastron Sdn.
Bha., Malaysia type SMCC 472 J for L = 4.7 mHz (
5%)
Philips Components No: 2222 429 71802, C = 1.8 nF (
2%)
.
1998 Jul 03
6
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
PINNING
SYMBOL
PIN
DESCRIPTION
SDA
1
I
2
C-bus data input/output
C
AGC
2
AGC capacitor of pilot frequency amplifier
C
LP
3
identification low-pass capacitor
C
DCL
4
DC loop capacitor
V
i pil
5
pilot frequency input voltage
C
ref
6
capacitor of reference voltage (
1
/
2
V
P
)
V
i 1
7
AF input signal V
i 1
(from 1st sound carrier)
V
i 2
8
AF input signal V
i 2
(from 2nd sound carrier)
V
i 3
9
AF input signal V
i 3
(NICAM or AM sound (standard L))
V
i 4
10
AF input signal V
i 4
(NICAM)
V
o 4
11
AF output signal V
o 4
(SCART)
V
o 3
12
AF output signal V
o 3
(SCART)
V
o 2
13
AF output signal V
o 2
(main)
V
o 1
14
AF output signal V
o 1
(main)
C
D1
15
50
s de-emphasis capacitor of AF Channel 1
GND
16
ground (0 V)
C
D2
17
50
s de-emphasis capacitor of AF Channel 2
V
P
18
supply voltage (+5 to +8 V)
XTAL
19
10 MHz crystal input
SCL
20
I
2
C-bus clock input
Fig.3 Pin configuration.
fpage
TDA9840
MBE459
1
2
3
4
5
6
7
8
9
10
SDA
C
C
C
V
C
V
V
V
20
19
18
17
16
15
14
13
12
11
SCL
XTAL
V
C
GND
C
V
V
AGC
LP
DCL
i pil
ref
i 1
i 2
i 3
Vi 4
P
D2
D1
o 1
o 2
V
V
o 3
o 4
1998 Jul 03
7
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
FUNCTIONAL DESCRIPTION
The TDA9840 (see Fig.1) receives the signals from the
FM-demodulators in a TV two sound-carrier system. The
circuit is realized by the H00485 bipolar process.
The IC is intended for use in economic TV and VTR
receivers. Therefore optimum relationship between
integration of functions and use of external components
has been striven for. Additionally a new type of
identification circuit has been developed.
AF signal handling
The input AF signals, derived from the two sound carriers,
are processed in analog form using operational
amplifiers.The circuit incorporates level- and
stereo-adjustment to correct the spreading in the FM
detector output levels. Dematrixing uses the technique of
two amplifiers processing the AF signals. Finally, a source
selector provides the facility to route the mono signal
through to the outputs (`forced mono').
De-emphasis is performed by two RC low-pass filter
networks with internal resistors and external capacitors.
This provides a frequency response with the tolerances
given in Fig.4.
A source selector, controlled via the I
2
C-bus, allows
selection of the different modes of operation in accordance
with the transmitted signal. The device was designed for a
nominal input signal (FM: 54% modulation is equivalent to
f =
27 kHz / AM: m = 0.54) of 250 mV RMS (V
i 1
, V
i 2
),
respectively 500 mV RMS (V
i 3
,V
i 4
). A nominal gain of
6 dB for V
i 1
and V
i 2
signals and 0 dB for V
i 3
and V
i 4
signals is built-in. By using rail-to-rail operational
amplifiers, the clipping level (THD
1.5%) is 1.6 V RMS for
V
P
= 5 V and 2.65 V RMS for V
P
= 8 V at outputs V
o 1
,
V
o 2
,V
o 3
and V
o 4
. Care has been taken to minimize
switching plops. Also total harmonic distortion and random
noise are considerably reduced.
Identification
The pilot signal is fed via an external RC high-pass filter
and single tuned LC band-pass filter to the input of a gain
controlled amplifier. The external LC band-pass filter in
combination with the external RC high-pass filter should
have a loaded Q-factor of about 40 to 50 to ensure the
highest identification sensitivity. By using a fixed coil (
5%)
to save the alignment (see Fig.2), a Q-factor of about 12 is
proposed. This may cause a loss in sensitivity of about
2 to 3 dB. A digital PLL circuit generates a reference
carrier, which is synchronized with the pilot carrier.
This reference carrier and the gain controlled pilot signal
are fed to the AM-synchronous demodulator. The
demodulator detects the identification signal, which is fed
through a low-pass filter with external capacitor C
LP
(pin 3)
to a Schmitt-trigger for pulse shaping and suppression of
low level spurious signal components. This is a measure
against mis-identification.
The identification signal is amplified and fed through an
AGC low-pass filter with external capacitor C
AGC
(pin 2) to
obtain the AGC voltage for controlling the gain of the pilot
signal amplifier.
The identification stages consist of two digital PLL circuits
with digital synchronous demodulation and digital
integrators to generate the stereo or dual sound
identification bits which can be read out via the I
2
C-bus.
A 10 MHz quartz crystal oscillator provides the reference
clock frequency. The corresponding detection bandwidth
is larger than
50 Hz for the pilot carrier signal, so that
f
p
-variations from the transmitter can be tracked in case of
missing synchronisation with the horizontal frequency f
H
.
However the detection bandwidth for the identification
signal is made small (approximately
1 Hz) to reduce
mis-identification.
Figure 2 shows an example of the alignment-free f
p
band-pass filter. To achieve the required Q
L
of
approximately 12, the Q
0
at f
p
of the coil was chosen to be
approximately 25 (effective Q
0
including PCB influence).
Using coils with other Q
0
, the RC-network (R
FP
, C
FP
) has
to be adapted accordingly. It is assumed that the loss
factor tan
of the resonance capacitor is
0.01 at f
p
.
Copper areas under the coil might influence the loaded Q
and have to be taken into account. Care has also to be
taken in environments with strong magnetic fields when
using coils without magnetic shielding.
I
2
C-bus transceiver
The complete IC is controlled by a microcomputer via the
I
2
C-bus. The built-in I
2
C-bus transceiver transmits the
identification result to the I
2
C-bus and receives the control
data for the source selector and level control. The I
2
C-bus
protocol is given in Tables 2 to 12 respectively.
The data transmission between the microcontroller and
the other I
2
C-bus controlled ICs is not disturbed, when the
supply voltage of the TDA9840 is not connected or when
powering up or down. Finally, a Schmitt-trigger is built-in
the SDA/SCL interface to suppress spikes from the
I
2
C-bus.
1998 Jul 03
8
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
Power supply
The different supply voltages and currents required for the
analog and digital circuits are derived from an internal
band-gap reference circuit. The AF reference voltage is
1
/
2
V
P
. For a fast setting to
1
/
2
V
P
an internal start-up circuit
is added. A good ripple rejection is achieved with the
external capacitor C
ref
= 100
F/16 V in conjunction with
the high ohmic input of the
1
/
2
V
P
pin (pin 6). Additional
DC-load on this pin is prohibited.
Power-on reset
When a power-on reset is activated by switching on the
supply voltage or because of a supply voltage breakdown,
the 117/274 Hz DPLL, the 117/274 Hz integrator and the
registers will be reset. Both AF channels
(Main and SCART) are muted.
Fast mode / test mode
The TDA9840 has a fast mode (test mode) to reduce the
integration time of the 117/274 Hz integrator from
approximately 1 to 0.5 s.
ESD protection
All pins are ESD protected. The protection circuits
represent the latest state of the art.
Internal circuit
The internal pin loading diagram is given in Fig.7.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1. Charge device model class B: discharging a 200 pF capacitor through a 0
series resistor.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
P
supply voltage (pin 18)
-
0.3
10
V
V
i
voltage at pins 1 and 20
-
0.3
5.5
V
V
i
voltage at pins 2 to 15, 17 and 19
-
0.3
V
P
V
T
stg
storage temperature
-
25
+150
C
T
amb
operating ambient temperature
0
+70
C
V
esd
electrostatic handling for all pins
note 1
-
300
V
SYMBOL
PARAMETER
VALUE
UNIT
R
th j-a
thermal resistance from junction to ambient in free air
DIP20
73
K/W
SO20
90
K/W
1998 Jul 03
9
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
CHARACTERISTICS
V
P
= 5 V; T
amb
= +25
C; nominal input signal V
i 1, 2
= 0.25 V RMS value (FM: 54% modulation is equivalent to
f =
27 kHz); nominal input signal V
i 3, 4
= 0.5 V RMS value (AM: m = 0.54); nominal output signal V
o 1, 2, 3, 4
= 0.5 V
RMS value; f
AF
= 1 kHz; V
i pil
= 16 mV RMS value; f
pil
= 54.6875 kHz (identification frequencies: stereo = 117.48 Hz,
dual = 274.12 Hz), 50
s pre-emphasis; noise measurement in accordance with
"CCIR468-3", working oscillator
frequency f
= 10.008 MHz; currents into the IC positive; measured in test circuit according to Fig.5; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
V
P
supply voltage (pin 18)
4.5
5
8.8
V
I
P
supply current (pin 18)
15.5
16.5
20.5
mA
P
tot
total power dissipation
69.75
82.5
180.4
mW
V
n(DC)
DC voltage
(pins 7 to 15 and 17)
1
/
2
V
P
-
0.1
1
/
2
V
P
1
/
2
V
P
+ 0.1
V
V
ref(DC)
DC reference voltage (pin 6)
1
/
2
V
P
-
0.1
1
/
2
V
P
1
/
2
V
P
+ 0.1
V
l
L(DC)
DC leakage current (pin 6)
-
-
1
A
AF Inputs; V
i 1
and V
i 2
(pins 7 and 8)
V
i(rms)
nominal input signal voltage
(RMS value)
54% modulation
-
0.25
-
V
V
i(rms)
clipping voltage level
(RMS value)
THD
1.5%; note 1
V
P
= 5 V
0.625
0.715
-
V
V
P
= 8 V
1.050
1.200
-
V
THD
1.5%; note 2
V
P
= 5 V
0.780
0.900
-
V
V
P
= 8 V
1.300
1.500
-
V
G
v
AF signal voltage gain
G = V
o
/V
i
; note 3
5
6
7
dB
G
v
(V
o1
) stereo control range
only at pin 7
+2.4
+2.5
+2.6
dB
-
2.3
-
2.4
-
2.5
dB
nominal step
maximum 49 steps
-
0.1
-
dB
G
v
(V
o2
) level control range
only at pin 8
+2.4
+2.5
+2.6
dB
-
1.9
-
2.0
-
2.1
dB
nominal step
maximum 9 steps
-
0.5
-
dB
R
i
input resistance
40
50
60
k
R
deem
internal de-emphasis resistor
(pins 15 and 17)
see Fig.4
4.25
5.0
5.75
k
Additional AF input pin (pins 9 and 10)
V
i(rms)
nominal input signal voltage
(RMS value)
54% modulation
-
0.5
-
V
V
i(rms)
clipping voltage level
(RMS value)
THD
1.5%
V
P
= 5 V
1.25
1.40
-
V
V
P
= 8 V
2.10
2.35
-
V
G
v
AF signal voltage gain
G = V
o
/V
i
; note 3
-
1
0
1
dB
R
i
input resistance
40
50
60
k
1998 Jul 03
10
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
AF outputs (pins 11 to 14)
V
o(rms)
nominal output signal voltage
(RMS value)
THD
0.3%;
54% modulation
-
0.5
-
V
V
o(rms)
clipping voltage level
(RMS value)
THD
1.5%
V
P
= 5 V
1.4
1.6
-
V
V
P
= 8 V
2.4
2.65
-
V
R
o
output resistance
150
250
350
C
L
load capacitor on output
-
-
1.5
nF
R
L
load resistor on output
(AC-coupled)
10
-
-
k
B
frequency response
(bandwidth)
f
i
= 40 to 20000 Hz;
note 4
-
0.5
-
+0.5
dB
B
-
3 dB
frequency response
-
3 dB; note 4
300
350
400
kHz
THD
total harmonic distortion
note 3
-
0.2
0.3
%
S/N(W)
weighted signal-to-noise ratio
"CCIR468-3"
(quasi-peak)
66
75
-
dB
cr
crosstalk attenuation for
notes 3 and 5
DUAL
Z
s
1 k
70
75
-
dB
STEREO
Z
s
1 k
40
45
-
dB
mute
mute attenuation
Z
s
1 k
; note 3
76
80
-
dB
V
DC
change of DC level output
voltage between any two
modes of operation
after switching
-
-
10
mV
PSRR
power supply ripple rejection
f
r
= 70 Hz; see Fig.6
50
65
-
dB
I
O(DC)
DC output current
-
-
20
A
I2C
noise from I
2
C-bus
note 6
-
90
80
dB
10 MHz crystal oscillator (pin 19)
f
r
series resonant frequency of
crystal (fundamental mode)
C
L
= 20 pF
9.995
10.008
10.021
MHz
f
working oscillator frequency
(running in parallel resonance
mode)
over operating
temperature range
including ageing and
influence of drive
circuit
9.988
10.008
10.028
MHz
R
r
equivalent crystal series
resistance
even at extremely low
drive level (<1 pW)
over operating
temperature range
with C
0
= 6 pF
-
60
200
R
n
crystal series resistance of
unwanted mode
2
R
r
-
-
C
0
crystal parallel capacitance
with R
r
100
-
6
10
pF
C
1
crystal motional capacitance
-
25
50
fF
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1998 Jul 03
11
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
P
XTAL
level of drive in operation
-
-
5
W
V
OSC(p-p)
oscillator operating voltage
(peak-to-peak value)
500
550
600
mV
Pilot processing
V
i pil(rms)
pilot input voltage level at pin 5
(RMS value)
unmodulated
5
-
100
mV
R
i pil
pilot input resistance
500
1000
-
k
m
modulation depth
AM
25
50
75
%
f
pil
pilot PLL pull-in frequency
range (referred to
f
pil
= 54.6875 kHz)
f
= 9.988 MHz
lower side
-
405
-
-
405
Hz
upper side
192
-
192
Hz
f
= 10.008 MHz
lower side
-
296
-
-
296
Hz
upper side
302
-
302
Hz
f
= 10.028 MHz
lower side
-
188
-
-
188
Hz
upper side
411
-
411
Hz
t
pil
pilot PLL pull-in time
0
-
1.7
ms
f
LP
low-pass frequency response
-
3 dB
450
600
750
Hz
R
3
low-pass output resistance
18.75
25
31.25
k
V
4(rms)
identification threshold voltage
(RMS value)
-
-
70
mV
Q
L
loaded quality factor of
resonance circuit
high sensitivity
40
-
50
loaded quality factor of
resonance circuit with fixed
coil
sensitivity loss
2 to 3 dB; see Fig.2
-
12
-
t
acqui AGC
AGC acquisition time
V
i pil(rms)
switched from
0 to 100 mV RMS
value
-
-
0.1
s
Identification (internal functions)
V
i tuner
identification voltage sensitivity
(pin 5)
note 7
-
28
-
dB
V
C/N
pilot carrier-to-noise ratio for
start of identification
note 8
-
33
-
dB/Hz
H
hysteresis
note 7
-
-
2
dB
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1998 Jul 03
12
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
f
det
pull-in frequency range of
identification PLL (referred to
f
det STEREO
= 117.48 Hz and
f
det DUAL
= 274.12 Hz)
normal mode
lower side
STEREO
-
0.38
-
-
0.38
Hz
DUAL
-
0.69
-
-
0.69
Hz
normal mode
upper side
STEREO
0.69
-
0.69
Hz
DUAL
0.69
-
0.69
Hz
fast mode lower side
STEREO
-
0.89
-
-
0.89
Hz
DUAL
-
2.05
-
-
2.05
Hz
fast mode upper side
STEREO
1.15
-
1.15
Hz
DUAL
2.05
-
2.05
Hz
t
det
pull-in time of identification
PLL (referred to
f
det STEREO
= 117.48 Hz and
f
det DUAL
= 274.12 Hz)
normal mode
STEREO
0
-
1.35
s
DUAL
0
-
0.72
s
fast mode
STEREO
0
-
0.57
s
DUAL
0
-
0.25
s
f
ident
identification window
frequency width (referred to
f
det STEREO
= 117.48 Hz and
f
det DUAL
= 274.12 Hz)
normal mode; note 9
STEREO
2.0
-
2.0
Hz
DUAL
2.3
-
2.3
Hz
fast mode; note 9
STEREO
3.8
-
3.8
Hz
DUAL
5.8
-
5.8
Hz
t
integr
integrator time constant
normal mode
0.94
-
0.94
s
fast mode
0.47
-
0.47
s
t
ident(on)
total identification time on
normal mode; note 10
STEREO
0.35
-
2.3
s
DUAL
0.35
-
2.0
s
fast mode; note 10
STEREO
0.175
-
1.1
s
DUAL
0.175
-
1.0
s
t
ident(off)
total identification time off
normal mode; note 11
STEREO
0.6
-
1.6
s
DUAL
0.6
-
1.6
s
fast mode; note 11
STEREO
0.3
-
0.8
s
DUAL
0.3
-
0.8
s
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1998 Jul 03
13
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
Notes
1. Input control amplifiers with
G
v
= 0 dB.
2. Input control amplifiers with
G
v
=
-
2 dB.
3. V
o
= 0.5 V RMS value; f = 1 kHz; input control amplifiers with
G
v
= 0 dB.
4. Without de-emphasis capacitors with respect to nominal gain.
5. In dual mode: A (B)-signal into B (A) channel.
In stereo mode: R-signal into left channel; L-signal = 0.
6. Test procedure tbf (same as TDA9855).
7. Tuner input signal, measured with PCALH reference front end (
1
/
2
EMF, 75
, 2T/20T/white bar, 100% video) and
PC/SC
1
= 13 dB; PC/SC
2
= 20 dB. The pilot band-pass has to be aligned.
8. Bandwidth of the pilot BP-filter B
-
3 dB
= 1.2 kHz. V
i 2
input driven with identification-modulated pilot carrier and white
noise.
9. Identification window is defined as total pull-in frequency range (lower plus upper side) of identification PLL (steady
detection) plus window increase due to integrator (fluctuating detection).
10. The maximum total system identification time ON is equal to t
ident(on)
plus t
acqui AGC
plus t
I2C read-out
.
11. The maximum total system identification time OFF is equal to t
ident(off)
plus t
I2C read-out
.
I
2
C-bus transceiver (pins 1 and 20)
f
CI
clock frequency
0
-
100
kHz
I
2
C-bus: SCL (pin 20)
V
IL
LOW level input voltage
-
0.3
-
1.5
V
V
IH
HIGH level input voltage
3.0
-
5.5
V
t
low
timing LOW period
4.7
-
-
s
t
high
timing HIGH period
4.0
-
-
s
t
r
rise time
-
-
1
s
t
f
fall time
-
-
0.3
s
I
IL
LOW level input current
-
-
-
10
A
I
IH
HIGH level input current
-
-
10
A
I
2
C-bus: SDA (pin 1)
V
IL
LOW level input voltage
-
0.3
-
1.5
V
V
IH
HIGH level input voltage
3.0
-
5.5
V
t
r
rise time
-
-
1
s
t
f
fall time
-
-
0.3
s
t
su
data set-up time
0.25
-
-
s
I
IL
LOW level input current
-
-
-
10
A
I
OL
LOW level output current
-
3
-
-
mA
I
IH
HIGH level input current
-
-
10
A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1998 Jul 03
14
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
I
2
C-BUS PROTOCOL FOR THE TV AND VTR
STEREO/DUAL SOUND PROCESSOR TDA9840
The TDA9840 has an I
2
C-bus interface with five registers:
status, test, switch, level and stereo adjustment register
controlled by a microcontroller via I
2
C-bus. The status
register can be read and the other registers are write
registers. The status byte represents the transmitter status
detected by the identification circuit and the power-on
reset status. The switch register controls the source
selectors of the AF signal part, and the level and stereo
adjustment register set the input level and stereo
adjustment stage. Additionally, a test register is built-in to
reduce the detection time of the identification circuit (test
mode, fast mode respectively).
I
2
C-bus transceiver and data-handling
(bus specification)
The TDA9840 is controlled by a microcomputer via the
bidirectional 2-line I
2
C-bus. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor. Data
transfer may be initiated only when the bus is not busy.
When the bus is free, both lines are HIGH. The data on the
SDA line must be stable during the HIGH period of the
clock. The HIGH or LOW state of the data line can only
change, when the clock signal on the SCL line is LOW.
The set-up and hold times are specified in the
Chapter "Characteristics".
A HIGH-to-LOW transition of the SDA line, while SCL is
HIGH, is defined as the start condition. A LOW-to-HIGH
transition of the SDA line, while SCL is HIGH, is defined as
the stop condition. The bus transceiver will be reset on the
reception of a start condition. The bus is considered to be
busy after the start condition. The bus is considered to be
free again after a stop condition.
Data format transmitter mode
For the data transmission no subaddress is to be
transmitted, because there is only one read register
implemented. So the total number of bytes reduces from
three to two. The second byte represents the status of
the IC.
Status register (see Table 4)
The bit D7 (PONRES) represents the status of the IC and
indicates whether the power-on reset was activated by
switching-on the supply voltage or a supply voltage
breakdown. If so, the I
2
C-bus transceiver, the digital PLLs
and integrators are initialized and the PONRES bit is set to
HIGH. After a successful reading of the status register, the
bit D7 will be reset to LOW.
The bits D5 and D6 represent the transmitter status
detected by the identification circuit (stereo, dual or mono
transmission). The other bits are set to 0 (default).
Data format for the receiver
Table 1
Registers for receiver mode (see Table 6)
The port register is without function, because this IC has
no control ports as TDA8415/6/7. A data byte for the
subaddress (01)
HEX
will not be stored in any register. An
acknowledge will be sent to the microcontroller.
The first byte of the data transmission is the slave address
and the second byte is the subaddress indicating the data
register in which the data shall be stored. Starting from
subaddress (00)
HEX
the n-th data byte will automatically be
stored under subaddress n
-
1.
All 8 bits of the subaddress are decoded by the device.
The subaddresses from (04)
HEX
to (FF)
HEX
are forbidden
for the user. If the I
2
C-bus transceiver receives
subaddresses from (05)
HEX
to (FF)
HEX
, no acknowledge
will be sent back to the microcontroller.
Switch register
The source selector is controlled by the switch register.
Table 7 shows the modes of operation. Note, that in the
event of the external operation mode, no further selection
is possible.
REGISTER
VALUE
Switch register
(00)
HEX
Port register
(01)
HEX
(without function)
Level adjustment register
(02)
HEX
Stereo adjustment register
(03)
HEX
Test register
(04)
HEX
1998 Jul 03
15
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
Level adjustment register
The information about the level adjustment of the AF
channel V
i 2
(pin 8) is stored in the level adjustment
register (see Table 10). There are 10 steps (positions) of
the AF level adjustment stage. The level range is from
2.5 dB up to
-
2.0 dB in 0.5 dB steps.
After a power-on reset, the data byte of the level
adjustment register will be set to (00)
HEX
: 0 dB gain at the
AF input V
i 2
.
Stereo adjustment register
The information about the stereo adjustment of the
AF channel V
i 1
(pin 7) is stored in the stereo adjustment
register (see Table 11). There are 50 steps (positions) of
the AF stereo adjustment stage. The stereo range is from
2.5 dB up to
-
2.4 dB in 0.1 dB steps.
After a power-on reset, the data byte of the stereo
adjustment register will be set to (00)
HEX
: 0 dB gain at the
AF input V
i 1
.
Test register (also used for fast mode)
Table 12 shows the meaning of the test register. The
integration time of the integrator is approximately 1 s
(normal mode, default). If the data byte of this register is
set to HIGH, the integration time is reduced from
approximately 1 to approximately 0.5 s (fast mode, test
mode). The pull-in ranges of the identification PLLs are
changed to:
Stereo:
-
0.89/+1.15 Hz
Dual:
2.05 Hz.
If the integration time of the integrator is switched from one
mode to the other (i.e. from fast mode/test mode to normal
mode), the status register bits D5 and D6 might set to zero
internally (MONO). Therefore, the previous status register
information has to be stored by the microcontroller until the
transmitter status is detected again by the identification
circuit (now in the new mode) the first time.
The data byte of the test register can be reset in two
different ways to (00)
HEX
: integration time approximately
1 s, normal mode:
after a power-on reset, for instance by switching the
power supply V
p
off and on again
data transmission via I
2
C-bus for the test register
(see Table 12).
Level and stereo adjustment
For the level and stereo adjustment of both AF channels
V
i 1
and V
i 2
, the following procedure will be recommended.
Level adjustment of the AF channel V
Feeds AF signal at the input V
i 2
Sets the data byte of the switch register (dual mode)
to (1A)
HEX
Measures the signal at the outputs V
o 2
or V
o 4
Adjusts the output level with the level adjustment
register.
Stereo adjustment of the AF channel V
i 1
Feeds AF stereo signals at the inputs V
i 1
((L+R)/2) and
V
i 2
(R)
Sets the data byte of the switch register (stereo mode)
to (2A)
HEX
Measures the crosstalk attenuation between V
o 1
and
V
o 2
or V
o 3
and V
o 4
Adjusts the crosstalk attenuation with the stereo
adjustment register.
During the stereo adjustment the data byte of the level
adjustment register does not change.
After the level and stereo adjustment, the bytes of the level
and stereo adjustment register must be stored by the
microcontroller in a memory. (To avoid mis-adjustment it
would be wise to compare the stored bytes with the proper
adjustment bytes). If the PONRES bit of the status register
will be set to HIGH (see status register) the data bytes for
these both registers must be sent out of the memory to the
TDA9840 via I
2
C-bus. Also the data byte of the switch
register (see Table 7) must be changed, because the
AF outputs are muted.
1998 Jul 03
16
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
I
2
C-BUS FORMAT
X is the read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read (the circuit is slave
transmitter). If more than 1 byte of DATA is transmitted, then auto-increment of the significant subaddress is performed.
Table 2
I
2
C-bus; SLAVE ADDRESS/SUBADDRESS/DATA format
Table 3
Explanation of Table 2
Table 4
I
2
C-bus; SLAVE ADDRESS/DATA to read the status byte (X = 1 in the address byte)
Table 5
Explanation of Table 4
S
SLAVE ADDRESS
A
SUBADDRESS
A
DATA
P
BIT
FUNCTION
S
start condition
SLAVE ADDRESS
1000 010X
A
acknowledge, generated by the slave
SUBADDRESS
dual sound A/B
DATA
data byte; see Table 6
P
stop condition
FUNCTION
SLAVE
ADDRESS
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Status byte
1000 0101
PONRES
ST
DS
0
0
0
0
0
BIT
FUNCTION
PONRES = 0
after a successful reading of the status register
PONRES = 1
after power-on reset or after supply breakdown
ST = 0; DS = 0
MONO sound identified
ST = 0; DS = 1
DUAL sound identified
ST = 1; DS = 0
STEREO sound identified
ST = 1; DS = 1
incorrect identification
1998 Jul 03
17
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
Table 6
I
2
C-bus; SUBADDRESS/DATA for writing (X = 0 in the address byte)
Note
1. This byte is acknowledged by the TDA9840.
Function of the bits:
SW6 to SW0 input and output AF selection; see Table 7
LV3 to LV0 level adjustment; see Table 10
ST5 to ST0 stereo adjustment; see Table 11.
Table 7
Data byte to select AF inputs and AF outputs [subaddress (00)
HEX
]
FUNCTION
SUBADDRESS
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Switching
0000 0000
0
SW6
SW5
SW4
SW3
SW2
SW1
SW0
Without function
(note 1)
0000 0001
0
0
0
0
0
0
0
0
Level adjustment
0000 0010
0
0
0
0
LV3
LV2
LV1
LV0
Stereo adjustment
0000 0011
0
0
ST5
ST4
ST3
ST2
ST1
ST0
TRANSMISSION
MODE
INPUT SIGNAL
OUTPUT SIGNAL
DATA
ST/DS/M
EXT
MAIN
SCART
V
i 1
PIN
7
V
i 2
PIN
8
V
i 3
PIN
9
V
i 4
PIN
10
V
o 1
PIN
14
V
o 2
PIN
13
V
o 3
PIN
12
V
o 4
PIN
11
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Sound mute
-
-
-
-
-
no signal
0
0
0
0
0
0
0
0
00
MONO
M
M
-
-
-
M
M
M
M
0
0
0
1
0
0
0
0
10
STEREO
ST
S
R
-
-
S
S
S
S
0
0
0
1
0
0
0
0
10
S
R
-
-
L
R
L
R
0
0
1
0
1
0
1
0
2A
DUAL
DS
A
B
-
-
A
B
A
A
0
0
0
1
0
0
1
0
12
A
B
-
-
A
B
A
B
0
0
0
1
1
0
1
0
1A
A
B
-
-
A
B
B
A
0
0
0
1
0
1
1
0
16
A
B
-
-
A
B
B
B
0
0
0
1
1
1
1
0
1E
External
-
-
-
C
D
C
D
C
D
0
1
1
1
1
0
1
0
7A
Table 8
Explanation of Table 7
SIGNAL
DESCRIPTION
R
right
L
left
S
A and B
dual sound A/B
L
R
+
(
)
2
--------------------
C
NICAM or AM sound (standard L)
D
NICAM
M
mono sound
DS
dual sound
ST
stereo sound
SIGNAL
DESCRIPTION
1998 Jul 03
18
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
Table 9
AF switch configuration
Table 10 Data byte to select level adjustment [subaddress (02)
HEX
]
INPUT
OUTPUT
TRANSMITTER STATUS
SIGNAL
MAIN
SCART
MONO
M
M
M
M
M
STEREO
L
L or M
L or M
R
R or M
R or M
DUAL
A
A
A or B
B
B
A or B
External
C
C
C
D
D
D
G
V
(dB)
DATA
D7
D6
D5
D4
D3
D2
D1
D0
HEX
+2.5
0
0
0
0
1
1
0
1
0D
+2.0
0
0
0
0
1
1
0
0
0C
+1.5
0
0
0
0
1
0
1
1
0B
+1.0
0
0
0
0
1
0
1
0
0A
+0.5
0
0
0
0
1
0
0
1
09
0
0
0
0
0
0
0
0
0
00
-
0.5
0
0
0
0
0
0
0
1
01
-
1.0
0
0
0
0
0
0
1
0
02
-
1.5
0
0
0
0
0
0
1
1
03
-
2.0
0
0
0
0
0
1
0
0
04
1998 Jul 03
19
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
Table 11 Data byte to select stereo adjustment
[subaddress (03)
HEX
]
G
V
(dB)
DATA
D7
D6
D5
D4
D3
D2
D1
D0
HEX
+2.5
0
0
1
1
1
0
0
1
39
+2.4
0
0
1
1
1
0
0
0
38
+2.3
0
0
1
1
0
1
1
1
37
+2.2
0
0
1
1
0
1
1
0
36
+2.1
0
0
1
1
0
1
0
1
35
+2.0
0
0
1
1
0
1
0
0
34
+1.9
0
0
1
1
0
0
1
1
33
+1.8
0
0
1
1
0
0
1
0
32
+1.7
0
0
1
1
0
0
0
1
31
+1.6
0
0
1
1
0
0
0
0
30
+1.5
0
0
1
0
1
1
1
1
2F
+1.4
0
0
1
0
1
1
1
0
2E
+1.3
0
0
1
0
1
1
0
1
2D
+1.2
0
0
1
0
1
1
0
0
2C
+1.1
0
0
1
0
1
0
1
1
2B
+1.0
0
0
1
0
1
0
1
0
2A
+0.9
0
0
1
0
1
0
0
1
29
+0.8
0
0
1
0
1
0
0
0
28
+0.7
0
0
1
0
0
1
1
1
27
+0.6
0
0
1
0
0
1
1
0
26
+0.5
0
0
1
0
0
1
0
1
25
+0.4
0
0
1
0
0
1
0
0
24
+0.3
0
0
1
0
0
0
1
1
23
+0.2
0
0
1
0
0
0
1
0
22
+0.1
0
0
1
0
0
0
0
1
21
0
0
0
0
0
0
0
0
0
00
-
0.1
0
0
0
0
0
0
0
1
01
-
0.2
0
0
0
0
0
0
1
0
02
-
0.3
0
0
0
0
0
0
1
1
03
-
0.4
0
0
0
0
0
1
0
0
04
-
0.5
0
0
0
0
0
1
0
1
05
-
0.6
0
0
0
0
0
1
1
0
06
-
0.7
0
0
0
0
0
1
1
1
07
-
0.8
0
0
0
0
1
0
0
0
08
-
0.9
0
0
0
0
1
0
0
1
09
-
1.0
0
0
0
0
1
0
1
0
0A
-
1.1
0
0
0
0
1
0
1
1
0B
-
1.2
0
0
0
0
1
1
0
0
0C
-
1.3
0
0
0
0
1
1
0
1
0D
-
1.4
0
0
0
0
1
1
1
0
0E
-
1.5
0
0
0
0
1
1
1
1
0F
-
1.6
0
0
0
1
0
0
0
0
10
-
1.7
0
0
0
1
0
0
0
1
11
-
1.8
0
0
0
1
0
0
1
0
12
-
1.9
0
0
0
1
0
0
1
1
13
-
2.0
0
0
0
1
0
1
0
0
14
-
2.1
0
0
0
1
0
1
0
1
15
-
2.2
0
0
0
1
0
1
1
0
16
-
2.3
0
0
0
1
0
1
1
1
17
-
2.4
0
0
0
1
1
0
0
0
18
G
V
(dB)
DATA
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Table 12 Data byte to select integration time [subaddress (04)
HEX
]
Function of the bits:
INTFU = 0 integrator function enabled
INTFU = 1 integrator function disabled
INT1SN = 0 integration time approximately 1 s (default)
INT1SN = 1integration time approximately 0.5 s.
FUNCTION
SUBADDRESS
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Test byte
0000 0100
X
X
X
X
X
X
INTFU
INT1SN
1998 Jul 03
20
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
Fig.4
Tolerance scheme of AF frequency response; de-emphasis with C
D1
, C
D2
= 10 nF (
5%),
R
internal
= 5 k
(
15%).
-
2
+
1
+
2
-
1
10
5
MED647
10
4
10
3
10
2
10
0
VoAF
(dB)
foAF (Hz)
R:
-
15%;
C:
-
5%
R:
+
15%;
C:
+
5%
1998 Jul 03
21
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
handbook, full pagewidth
MBE460
TDA9840
10
F
CAGC
1
2
3
4
5
6
7
8
9
10
SDA
3.3
nF
2.5
mH
C LP
Cref
C DCL
10 nF
100 nF
1/2 VP
2.2
F
2.2
F
2.2
F
47 pF
30 k
V i 2
V i 1
V i 3
AF from 5.5 MHz
AF from 5.742 MHz
from external sound source C
2.2
F
V i 4
from external sound source D
20
19
18
17
16
15
14
13
12
11
Vo 4
Vo 3
scart
Vo 2
Vo 1
main
50
s
de-emphasis
5%
CD2
10 nF
50
s
de-emphasis
5%
CD1
10 nF
10
F
CVP
VP
10 MHz
XTAL
SCL
100
F/16 V
Fig.5 Test circuit of the stereo decoder TDA9840.
Fig.6 Test circuit for measurement of ripple rejection.
handbook, full pagewidth
100
F /
16 V
TDA9840
100
F
6 7
8
9
10 16
18
5 V modulated
with 200 mV (p-p)
70 Hz
100
F
10 k
V
B
V
P
11
12
13
14
measurements
on outputs
V
o 1
o 2
o 3
o 4
V
V
V
MBE462
1998 Jul 03
22
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
INTERNAL CIRCUITRY
Fig.7 Internal circuits.
handbook, full pagewidth
2 k
+
+
25 k
+
1
2
3
68
A
40
A
+
5 k
5 k
40
A
+
60
A
4
5
1/2 V
P
1/2 V
P
1/2 V
P
1/2 V
P
1/2 V
P
6
I
7
I
B
8
I
B
9
I
B
10
I
B
B
5 k
2 k
+
+
5 k
3 pF
13 k
20
19
18
+
+
5 k
17
16
+
+
5 k
15
+
200
A
+
200
A
+
200
A
+
200
A
14
13
12
11
TDA9840
AF outputs
AF inputs
V
P
GND
SDA
C
AGC
C
LP
C
DCL
V
i pil
C
ref
V
i 1
V
i 2
V
i 3
V
i 4
V
o 1
V
o 2
V
o 3
V
o 4
C
D1
C
D2
SCL
XTAL
25 k
2 dB
22.5 k
25 k
+
10 k
40 k
10 k
2 dB
40 k
25 k
6 dB
25 k
25 k
6 dB
25 k
+
+
+5 V
ESD protection diode
for pins 2 to 15, 17 and 19
zener diode protection
for pins 1, 18 and 20
V
P
5 k
MBE461
1998 Jul 03
23
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
PACKAGE OUTLINES
UNIT
A
max.
1
2
b
1
c
D
E
e
M
H
L
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT146-1
92-11-17
95-05-24
A
min.
A
max.
b
Z
max.
w
M
E
e
1
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
6.40
6.22
3.60
3.05
0.254
2.54
7.62
8.25
7.80
10.0
8.3
2.0
4.2
0.51
3.2
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
0.25
0.24
0.14
0.12
0.01
0.10
0.30
0.32
0.31
0.39
0.33
0.078
0.17
0.020
0.13
SC603
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w
M
b
1
e
D
A
2
Z
20
1
11
10
b
E
pin 1 index
0
5
10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
(1)
(1)
(1)
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
1998 Jul 03
24
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
UNIT
A
max.
A
1
A
2
A
3
b
p
c
D
(1)
E
(1)
(1)
e
H
E
L
L
p
Q
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
inches
2.65
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
1.27
10.65
10.00
1.1
1.0
0.9
0.4
8
0
o
o
0.25
0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
1.1
0.4
SOT163-1
10
20
w
M
b
p
detail X
Z
e
11
1
D
y
0.25
075E04
MS-013AC
pin 1 index
0.10
0.012
0.004
0.096
0.089
0.019
0.014
0.013
0.009
0.51
0.49
0.30
0.29
0.050
1.4
0.055
0.419
0.394
0.043
0.039
0.035
0.016
0.01
0.25
0.01
0.004
0.043
0.016
0.01
0
5
10 mm
scale
X
A
A
1
A
2
H
E
L
p
Q
E
c
L
v
M
A
(A )
3
A
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
95-01-24
97-05-22
1998 Jul 03
25
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
"Data Handbook IC26; Integrated Circuit Packages"
(order code 9398 652 90011).
DIP
S
OLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260
C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
stg max
). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
R
EPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300
C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400
C, contact may be up to 5 seconds.
SO
R
EFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250
C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45
C.
W
AVE SOLDERING
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
The longitudinal axis of the package footprint must be
parallel to the solder flow.
The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260
C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150
C within
6 seconds. Typical dwell time is 4 seconds at 250
C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
R
EPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300
C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320
C.
1998 Jul 03
26
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I
2
C COMPONENTS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Purchase of Philips I
2
C components conveys a license under the Philips' I
2
C patent to use the
components in the I
2
C system provided the system conforms to the I
2
C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 Jul 03
27
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor
with digital identification and I
2
C-bus control
TDA9840
NOTES
Internet: http://www.semiconductors.philips.com
Philips Semiconductors a worldwide company
Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
Switzerland: Allmendstrasse 140, CH-8027 ZRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Talatpasa Cad. No. 5, 80640 GLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,
Fax. +43 160 101 1210
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 0044
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580920
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Germany: Hammerbrookstrae 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Printed in The Netherlands
545104/00/03/pp28
Date of release: 1998 Jul 03
Document order number:
9397 750 03999
PDF 
ZIP