2004 Nov 02

Philips Semiconductors

Product specification

DVB selective AGC amplifier

TDA9888TS; TDA9889TS

FEATURES

Applicable for terrestrial and cable TV reception

70 dB variable gain wide-band Intermediate Frequency
(IF) amplifier (AC-coupled)

Gain control via external control voltage (0 to 3 V)

2 V (p-p) differential low IF (downconverted) output for
direct Analog-to-Digital Converter (ADC) interfacing

Digital Video Broadcast (DVB) downconversion with
integrated selectivity (allows to use one SAW filter
applications)

Integrated anti-aliasing tracking low-pass filter

Fully integrated synthesizer controlled oscillator with
excellent phase noise performance

Synthesizer frequencies for a wide range of world wide
DVB standards (for IF centre frequencies of 36, 44
and 57 MHz) with different channel bandwidths
(6, 7 and 8 MHz) are possible; see Tables 1 and 2

4 MHz reference frequency input [signal from
Phase-Locked Loop (PLL) tuning system] or operating
as crystal oscillator

Tuner Automatic Gain Control (TAGC) detector for
independent tuner gain control loop applications

TAGC operating as peak-sync detector, fast reaction
time due to additional speed-up detector

TAGC switch for feed-through of TAGC signal from
analog TV demodulator (e.g. TDA9886) in case of
hybrid (analog and digital TV demodulation) application

Stabilizer circuit for ripple rejection and to achieve
constant output signals

Electrostatic discharge (ESD) protection for all pins.

GENERAL DESCRIPTION

The TDA9888TS; TDA9889TS is an AGC amplifier circuit
with integrated selectivity. The device provides
downconversion and filtering without alignment for all DVB
standards. The filtering considers the tough neighbouring
channel conditions.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA9888TS

SSOP16

plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

TDA9889TS

2004 Nov 02

Philips Semiconductors

Product specification

DVB selective AGC amplifier

TDA9888TS; TDA9889TS

QUICK REFERENCE DATA

Note

1. Some parameters can be decreased at V

= 4.5 V.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

supply voltage

note 1

4.5

5.5

supply current

o(LIF)(p-p)

typical low IF operating output
voltage (peak-to-peak value)

IF(max)

maximum conversion gain

output peak-to-peak level to
input RMS level ratio

IF(cr)

IF gain control range

see Fig.3

osc

synthesizer controlled oscillator
frequencies

see Tables 1 and 2

MHz

31.5

MHz

N(synth)

synthesizer phase noise
performance

at 1 kHz

dBc

at 10 kHz

dBc

at 100 kHz

102

dBc

LIF

low IF band amplitude characteristic

0 dB at middle of band
(standard independent)

0.9

+0.9

low-pass filter attenuation

8 MHz band; at 15.75 MHz

N+1

suppression of IF input frequencies
below wanted band at low IF output

input frequency between
21 and 31 MHz; referenced
to 36 MHz

C/N

carrier-to-noise ratio at low IF

f > 1 MHz; see Fig.5

112

116

dBc/Hz

PSRR

power supply ripple rejection
[residual ripple AM, modulation
factor m at 2 V (p-p) low IF signal]

ripple

= 70 Hz; see Fig.7

1.4

2004 Nov 02

Philips Semiconductors

Product specification

DVB selective AGC amplifier

TDA9888TS; TDA9889TS

PINNING

SYMBOL

PIN

DESCRIPTION

logic switch S0 input (frequency
select)

REF

4 MHz crystal or reference input

logic switch S2 input (AGC select)

LFS

loop filter synthesizer PLL

LFLP

loop filter low-pass control PLL

AGC

AGC control voltage input

LIF1

low IF differential output 1

LIF2

low IF differential output 2

TADJ

tuner AGC TakeOver Point (TOP)
adjustment

TAGC

tuner AGC output

TAGCEXT

external tuner AGC voltage input

supply voltage (+5 V)

logic switch S1 input (frequency
select)

GND

ground supply

IF1

IF differential input 1

IF2

IF differential input 2

handbook, halfpage

TDA9888TS
TDA9889TS

MHC093

REF

LFS

LFLP

AGC

LIF1

LIF2

IF2

IF1

GND

TAGCEXT

TAGC

TADJ

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION

Figure 1 shows the simplified block diagram of the device.
The integrated circuit contains the following functional
blocks:

1. Gain controlled IF amplifier

2. Tuner AGC

3. Reference generation

4. Synthesizer for downconversion

5. Downconversion and complex filtering

6. Tracking low-pass filter with reference control

7. Low IF differential output stage

8. Logic control

9. Internal voltage stabilizer.

Gain controlled IF amplifier

The IF amplifier consists of three AC-coupled differential
stages. Gain control is performed by emitter degeneration.
Total gain control range is 70 dB (typ.). The differential
input impedance is typical 2 k

in parallel with 3 pF.

Tuner AGC

The tuner AGC is realized by a TakeOver Point (TOP)
network and a peak-level detector. The threshold level of
the peak detector can be adjusted by an external
potentiometer connected to pin TADJ. For IF signals
above this threshold the level detector provides a
discharge current to pin TAGC. An additional current
source is internally connected to this pin providing charge
current to the external tuner AGC capacitor. For IF signals
of 8 dB below the threshold voltage this current will be
increased by a factor of approximately 40 for faster AGC
reaction. The ratio of discharge to charge current is
normally approximately 2000 and approximately 50 for
fast mode.

For use of the device in different applications the charge
current can be switched off, for hybrid applications the
signal at pin TAGCEXT can be fed via a transmission gate
to pin TAGC (TDA9888TS; TDA9889TS combined with
analog IF), controlled by the 3-state input pin S2. With an
activated transmission gate all internal currents are off.
In the event that the tuner AGC is not needed (e.g. TAGC
from channel decoder or from an analog IF in hybrid
chassis), pin TADJ should be left open-circuit and
therefore all internal AGC currents will be switched off.

2004 Nov 02

Philips Semiconductors

Product specification

DVB selective AGC amplifier

TDA9888TS; TDA9889TS

Reference generation

The 4 MHz crystal is the reference for the downconversion
synthesizer and the filter synthesizer.

The downconverted DVB frequency and the frequency
adjustment of the integrated filters are dependent on the
precision of the reference signal at pin REF. An operation
as crystal oscillator is possible as well as connecting this
input via a serial capacitor to another low-ohmic reference
frequency source.

The integrated divider-by-8 generates the internally
needed 500 kHz reference frequency for the DVB
synthesizer and the reference filter.

Synthesizer for downconversion

The PLL synthesizer for downconversion consists of a
Voltage Controlled Oscillator (VCO), a divider with a
standard dependent divider factor, a frequency phase
detector (constructed as a digital 3-state comparator) and
a charge pump.

The VCO operates as an integrated low radiation
relaxation oscillator at double the conversion frequency.
For downconversion the VCO frequency is divided-by-2 to
provide two differential square wave signals with exactly
90 degrees phase difference, independent of the VCO
frequency.

The frequency phase detector compares the down-divided
oscillator signal with the 500 kHz reference frequency
signal and controls, via the charge pump, the control
voltage at the external loop filter connected to pin LFS,
which is required to tune the VCO exactly to the wanted
frequency.

The divider, the frequency phase detector and the
reference frequency divider are constructed in a low
radiation technique to optimize the synthesizer spurious
suppression in the downconverted output signal.

Downconversion and complex filtering

The gain controlled IF signal from the IF amplifier is fed to
two identical linear mixers, operating in the `in phase' and
`quadrature' mode in accordance to the 0 and 90 degree
VCO signal from the synthesizer. With this, the
downconverted DVB low IF signal is available as an
I and Q signal in the frequency band from 1 to 9 MHz.
These signals are fed to the complex filter section. As a
result of adding both signals, the unwanted mirror signal
will be attenuated (approximately 34 dB). The unwanted
frequency components below 1 MHz are attenuated in a
high-pass filter. This signal is then fed through a
group-delay equalizer circuit.

Tracking low-pass filter with reference control

The low-pass filter is controlled by a reference signal
[generated by a frequency synthesizer and can be
switched by the standard selection (S0 and S1)].

The tracking low-pass filter is designed as a
Tschebyscheff filter to guarantee sufficient suppression for
the neighbouring picture carrier. An all-pass filter corrects
the characteristic to obtain a flat (equivalent ripple) group
delay behaviour.

Low IF differential output stage

The output amplifier consists of two identical differential
operational amplifiers with a high common mode (DC)
rejection ratio, to provide a constant DC voltage at the
output stage. The amplified Low IF (LIF) signal is available
as a differential signal with an amplitude of 2 V (p-p) and
DC level of 2 V (typ.) between the output terminals of both
amplifiers.

Logic control

The logic control provides an easy selection of the most
common standards for Europe, USA and Japan with the
two switches S0 and S1 (frequency selection different for
TDA9888TS and TDA9889TS) and controls all internal
standard dependent stages.

The five available tuner AGC modes can be set via the
3-state input pin S2 and R

TOP

connection (at pin TADJ).

Internal voltage stabilizer

The band gap circuit generates a voltage of approximately
2.4 V, independent of the supply voltage and the
temperature. A voltage regulator circuit, controlled by this
voltage, produces a constant voltage of 3.55 V which is
used as an internal reference voltage.

2004 Nov 02

Philips Semiconductors

Product specification

DVB selective AGC amplifier

TDA9888TS; TDA9889TS

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).

Notes

1. Machine model (class B; SNW-FQ-302B): discharging a 200 pF capacitor via a 0.75

H inductance.

2. Human body model (class 2; SNW-FQ-302A): discharging a 100 pF capacitor via a 1.5 k

series resistor.

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

supply voltage

= 64 mA; T

amb

= 70

maximum chip temperature of
125

C; R

th(j-a)

= maximum

5.5

i(n)

input voltage at pins 1 to 11, 13, 15 and 16

short-circuit time to ground or V

stg

storage temperature

+150

amb

ambient temperature

+70

electrostatic handling voltage for all pins

note 1

200

+200

note 2

2500

+2500

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th(j-a)

thermal resistance from junction to ambient

in free air

136

K/W

2004 Nov 02

Philips Semiconductors

Product specification

DVB selective AGC amplifier

TDA9888TS; TDA9889TS

CHARACTERISTICS
V

= 5 V; T

amb

= 25

C; 8 MHz system; see Tables 1 or 2, CW test input signal is used for specification;

i(IF)(rms)

= 10 mV frequency f

= 36 MHz for low IF output of 5 MHz; IF input from 50

via broadband transformer

1 : 1; gain controlled amplifier adjusted to low IF differential output of 2 V (p-p); measurements taken in test circuit of
Fig.11 with external 4 MHz reference signal of 140 mV (RMS); unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply; pin V

supply voltage

note 1

4.5

5.5

supply current

tot

total power dissipation

275

352

IF amplifier; pins IF1 and IF2; differential

IF(max)

maximum conversion gain

output peak-to-peak level to
input RMS level ratio

IF(min)

minimum conversion gain

IF(cr)

IF gain control range

see Fig.3

IF(

3dB)(ll)

lower limit

3 dB IF bandwidth

note 2

MHz

IF(

3dB)(ul)

upper limit

3 dB IF bandwidth

note 2

MHz

i(dif)

differential input resistance

note 2

i(dif)

differential input capacitance

note 2

DC input voltage

1.9

Low IF output signal; pins LIF1 and LIF2; differential; see Fig.8

o(LIF)(p-p)

typical low IF operating output
voltage (peak-to-peak value)

clip(u)

upper clipping voltage level
(single-ended)

2.9

clip(l)

lower clipping voltage level
(single-ended)

0.6

o(diff)

output resistance (differential)

note 2

150

DC output voltage

bias(int)

internal DC bias current for
emitter-follower (single-ended)

0.8

o(source)(max)

maximum AC and DC output
source current (single-ended)

2.5

o(sink)(max)

maximum AC and DC output
sink current (single-ended)

note 3

0.6

L(diff)

differential load impedance

note 2

1.7

LIF

low IF band amplitude
characteristic

0 dB at middle of band
(standard independent)

0.9

+0.9

d(g)(LIF)

low IF band group delay ripple

from 1 MHz to 2 MHz

150

from 2 MHz to end of band

100

low-pass filter attenuation

6 MHz band; at 11.75 MHz

7 MHz band; at 13.75 MHz

8 MHz band; at 15.75 MHz

27MHz

low-pass filter attenuation

any band; at 27 MHz

2004 Nov 02

Philips Semiconductors

Product specification

DVB selective AGC amplifier

TDA9888TS; TDA9889TS

N+1

suppression of IF input
frequencies below wanted
band at low IF output

input frequency between
21 and 31 MHz; referenced
to 36 MHz

C/N

carrier-to-noise ratio at low IF

f = 4.9 MHz; note 4a;

see Fig.5

112

116

dBc/Hz

f = 4.9 MHz; note 4b;

see Fig.5

100

dBc/Hz

intermodulation at
f

LIF1

= 4.1 MHz or

LIF2

= 5.9 MHz

IF1

= f

osc

+ 4.7 MHz and

IF2

= f

osc

+ 5.3 MHz;

see Fig.6

in-band harmonics
low IF = multiple of 1.31 MHz
up to 7.86 MHz

IF1

= f

osc

+ 1.31 MHz

H(spur)

in-band spurious elements
(1 to 9 MHz)

AC load: Z

L(diff)

> 1.7 k

out-band spurious elements
(>9 MHz)

PSRR

power supply ripple rejection
[residual ripple FM, peak
deviation

f at 2 V (p-p) low IF

signal]

ripple

= 70 Hz; see Fig.7

ripple

= 1 kHz; see Fig.7

ripple

= 10 kHz; see Fig.7

1400

2000

ripple

= 100 kHz; see Fig.7

2700

4000

power supply ripple rejection
[residual ripple AM, modulation
factor m at 2 V (p-p) low IF
signal]

ripple

= 70 Hz; see Fig.7

1.4

IF AGC control; pin AGC

i(sink)(max)

maximum input sink current

i(max)

maximum allowable input
voltage

gain control voltage range

AGC

negative control steepness

con

= 0.8 to 2.2 V

dB/V

Tuner AGC; pin TAGC, operating as current output; see Figs 3 and 4

i(IF)(min)(p-p)

minimum controlled IF input
signal voltage between
pins IF1 and IF2
(peak-to-peak value)

TOP

= 22 k

;

TAGC(sink)

= 100

i(IF)(max)(p-p)

maximum controlled IF input
signal voltage between
pins IF1 and IF2
(peak-to-peak value)

TOP

= 0

;

TAGC(sink)

= 100

102

106

i(IF)

variation of AGC controlled IF
input voltage with temperature

TOP

= 8.2 k

;

TAGC(sink)

= 100

0.07

dB/K

sink

sink current (tuner AGC
discharge current)

TAGC

= 1 V

400

500

600

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2004 Nov 02

Philips Semiconductors

Product specification

DVB selective AGC amplifier

TDA9888TS; TDA9889TS

source(1)

source current (tuner AGC
charge current)

normal mode

0.21

0.27

0.33

source(2)

fast mode activated by
internal level detector

sat(ul)

upper limit saturation voltage

pin operating as current
output

0.3

sat(ll)

lower limit saturation voltage

0.3

level loss threshold of internal
detector for activating fast
AGC

0 dB corresponds to R

TOP

alignment

det(off)

fast AGC detection off time

all signal events below

External tuner AGC; electronic switch operation; pin TAGC connected to pin TAGCEXT

resistance between pins TAGC
and TAGCEXT in operation

900

1200

op(I/O)

I/O operating voltage range

Tuner AGC takeover point adjust and TAGC operating mode settings; pin TADJ; see Table 3

RTOP

alignment voltage

TOP

at pin

TADJ = 0 to 22 k

TADJ

voltage at pin TADJ

pin open-circuit

3.5

TOP

resistor connected between
pin TADJ and GND

for LOW: R

TOP

at pin TADJ

for HIGH: pin open-circuit

Low-pass control PLL; pin LFLP

LFLP

loop filter operating range

VCO steepness:

VCO

LFS

note 5

MHz/V

phase frequency detector
steepness:

LFLP

A/rad

lf(int)

internal loop filter resistor

3.75

4.7

5.65

sink/source

phase frequency detector I/O
current

Synthesizer PLL; pin LFS

LFS

loop filter operating range

VCO steepness:

VCO

LFS

note 5

MHz/V

phase frequency detector
steepness:

LFS

A/rad

sink/source

phase frequency detector I/O
current

100

N(synth)

synthesizer phase noise
performance

at 1 kHz

dBc/Hz

at 10 kHz

dBc/Hz

at 100 kHz

102

dBc/Hz

at 1.4 MHz

115

119

dBc/Hz

spur

synthesizer spurious
performance

multiple of

f = 500 kHz

dBc

leak(lf)

loop filter leakage current

synthesizer spurious
performance > 50 dBc

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2004 Nov 02

Philips Semiconductors

Product specification

DVB selective AGC amplifier

TDA9888TS; TDA9889TS

Standard switch S0 and S1; pins S0 and S1; see Tables 1 or 2

input voltage

for LOW

for HIGH

2.5

fr(S0,S1)

free-running voltage at pin S0
or pin S1

pin open-circuit;
I

fr(S0,S1)

< 0.1

3.5

input resistance

Standard switch S2; pin S2; see Table 3

input voltage

for LOW

0.8

for MID

1.3

for HIGH

2.5

fr(S2)

free-running voltage at pin S2

pin open-circuit;
I

fr(S2)

< 0.1

1.65

input resistance

Reference input; pin REF; note 6

DC input voltage

2.3

2.6

2.9

input resistance

1.5

2.5

input capacitance

xtal

resonance resistance of crystal operation as crystal oscillator

200

pull-up/down capacitance

note 7

depends on crystal type

ref

frequency of reference signal

MHz

ref

tolerance of reference
frequency

note 8

100

ref(p-p)

amplitude of reference signal
source (peak-to-peak value)

operation as input terminal

230

1100

o(ref)

allowed output resistance of
external reference source

4.7

decoupling capacitance to
external reference source

operation as input terminal

100

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2004 Nov 02

Philips Semiconductors

Product specification

DVB selective AGC amplifier

TDA9888TS; TDA9889TS

Notes

1. Some parameters can be decreased at V

= 4.5 V.

2. This parameter is not tested during production and is only given as application information.

3. For a higher AC load a resistor application is possible.

4. Measured without input signal but AGC adjusted corresponding to following input level

a) 10 mV (RMS)

b) 0.5 mV (RMS).

5. Calculation of the PLL loop filter by using following formulae, valid under the condition for the damping factor

and

with the following parameters

= VCO steepness (rad/V) or (2

Hz/V),

= phase frequency detector steepness (

A/rad),

LFS

= synthesizer loop filter serial resistor (

LFS

= synthesizer loop filter serial capacitor (F),

3dB

= loop filter bandwidth at

3 dB amplitude (Hz),

d = damping factor
n = divider factor; see Table 4.

6. The reference input at pin S2 is able to operate as a one-pin crystal oscillator as well as an input terminal with

external reference signal, e.g. from the tuning system.

7. The value of C

determines the accuracy of the resonance frequency of the crystal and depends on the crystal type.

8. The tolerance of the reference frequency determines the accuracy of the low IF. The tolerance of f

osc

is given by

and the tolerance of f

LIF

is given by

LIF

osc

Table 1

Standard switch settings for TDA9889TS

IF(centre)

(MHz)

osc

(MHz)

CHANNEL

BANDWIDTH

(MHz)

REGION

HIGH

Europe

HIGH

LOW

31.5

Europe

LOW

HIGH

USA

LOW

Europe

1.2

3 dB

-------

------- K

LFS

1
2

--- R

LFS

------- K

LFS

osc

ref

----------- f

osc

2004 Nov 02

Philips Semiconductors

Product specification

DVB selective AGC amplifier

TDA9888TS; TDA9889TS

Table 2

Standard switch settings for TDA9888TS

Table 3

AGC mode settings

Table 4

Synthesizer PLL loop filter dimensions for different standards; see note 5 of Chapter "Characteristics"

IF(centre)

(MHz)

osc

(MHz)

CHANNEL

BANDWIDTH

(MHz)

REGION

HIGH

Europe

HIGH

LOW

31.5

Europe

LOW

HIGH

USA

LOW

Japan

TOP

FUNCTION (PIN TADJ)

LOW

connected

all currents off; voltage from pin TAGCEXT switched to pin TAGC

MID

charge currents disabled; discharge current enabled

HIGH

all charge and discharge currents enabled

MID/HIGH

open-circuit

all currents off; pin TAGC high-ohmic

LOW

all currents off; voltage from pin TAGCEXT switched to pin TAGC

IF(centre)

(MHz)

osc

(MHz)

3dB

(kHz)

LFS

)

LFS

(nF)

P(LFS)

(pF)

36.1

1.22

5.6

4.7

31.5

35.6

1.21

1.20

1.31

6.8

106

34.4

1.52

9.1

2004 Nov 02

Philips Semiconductors

Product specification

DVB selective AGC amplifier

TDA9888TS; TDA9889TS

handbook, halfpage

120

300

600

200

500

100

400

MHC095

100

Vi(IF)(p-p) (dB

VTAGC

(V)

ITAGC

(

(2)

(3)

(4)

(1)

Fig.3 Typical IF and tuner AGC characteristic.

(1) IF AGC voltage.

(2) I

tuner

; R

TOP

= 22 k

(3) I

tuner

; R

TOP

= 8.2 k

(4) I

tuner

; R

TOP

= 0

handbook, halfpage

120

100

MHC096

Vi(IF)(rms)

(dB

RTOP (k

)

Fig.4

Typical tuner takeover point as a function of
R

TOP

handbook, halfpage

110

120

110

100

MHC097

Vi(IF)(rms) (dB

C/N

(dBc/Hz)

Fig.5

Typical C/N ratio as a function of IF input
voltage.

handbook, halfpage

input conditions

fosc

fIF

(MHz)

31.0

35.7

output signal

MHC098

fLIF

(MHz)

4.1

4.7

5.3

5.9

36.3

74 dB

1 V (p-p)

handbook, halfpage

input conditions

fIF

(MHz)

fLIF

(MHz)

fosc

31.0 32.31

output signal

MHC105

1.31

2.62 3.93 5.24 6.55 7.86 9.17

Fig.6 Intermodulation and harmonics.

Intermodulation

Harmonics

2004 Nov 02

Philips Semiconductors

Product specification

DVB selective AGC amplifier

TDA9888TS; TDA9889TS

handbook, halfpage

TDA9888TS
TDA9889TS

V = VP + Vripple

VP (V)

5.050

5.000

4.950

t (s)

MHC099

Fig.7 Ripple rejection condition.

handbook, halfpage

100

150

200

f (MHz)

(1)

(2)

(3)

(2)

MHC100

VLIF

(dB)

tolerance scheme:

(3)

td(g)(LIF)

(ns)

Fig.8

Detailed low IF amplitude and group delay
pass band tolerance scheme.

(1) Channel bandwidth = 6 MHz.

(2) Channel bandwidth = 7 MHz.

(3) Channel bandwidth = 8 MHz.

handbook, halfpage

MHC101

f (MHz)

tolerance scheme:

(3)

(2)

(1)

(2)

(3)

VLIF

(dB)

Fig.9

Low IF amplitude stop band tolerance
scheme.

(1) Channel bandwidth = 6 MHz.

(2) Channel bandwidth = 7 MHz.

(3) Channel bandwidth = 8 MHz.

handbook, halfpage

MHC102

f (MHz)

tolerance scheme:

(3)
(2)
(1)

(1)

(2)

(3)

VLIF

(dB)

Fig.10 Low IF amplitude pass band tolerance

scheme.

(1) Channel bandwidth = 6 MHz.

(2) Channel bandwidth = 7 MHz.

(3) Channel bandwidth = 8 MHz.

2004 Nov 02

Philips Semiconductors

Product specification

DVB selective AGC amplifier

TDA9888TS; TDA9889TS

PACKAGE OUTLINE

UNIT

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

0.21
0.05

1.80
1.65

0.25

0.38
0.25

0.20
0.09

6.4
6.0

5.4
5.2

0.65

1.25

7.9
7.6

1.03
0.63

0.9
0.7

1.00
0.55

8
0

0.13

0.2

0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT338-1

99-12-27
03-02-19

(1)

detail X

(A )

MO-150

pin 1 index

2.5

5 mm

scale

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

max.

2004 Nov 02

Philips Semiconductors

Product specification

DVB selective AGC amplifier

TDA9888TS; TDA9889TS

SOLDERING

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex
technology. A more in-depth account of soldering ICs can
be found in our

"Data Handbook IC26; Integrated Circuit

Packages" (document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine
pitch SMDs. In these situations reflow soldering is
recommended.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package
placement. Driven by legislation and environmental
forces the worldwide use of lead-free solder pastes is
increasing.

Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 seconds and 200 seconds
depending on heating method.

Typical reflow peak temperatures range from
215

C to 270

C depending on solder paste material.

The top-surface temperature of the packages should
preferably be kept:

below 225

C (SnPb process) or below 245

C (Pb-free

process)

for all BGA, HTSSON..T and SSOP..T packages

for packages with a thickness

2.5 mm

for packages with a thickness < 2.5 mm and a

volume

350 mm

so called thick/large packages.

below 240

C (SnPb process) or below 260

C (Pb-free

process) for packages with a thickness < 2.5 mm and a
volume < 350 mm

so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit
boards with a high component density, as solder bridging
and non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by
a smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint
must be placed at a 45

angle to the transport direction

of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side
corners.

During placement and before soldering, the package
must be fixed with a droplet of adhesive. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time of the leads in the wave ranges from
3 seconds to 4 seconds at 250

C or 265

C, depending

on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 seconds to 5 seconds
between 270

C and 320

2004 Nov 02

Philips Semiconductors

Product specification

DVB selective AGC amplifier

TDA9888TS; TDA9889TS

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. For more detailed information on the BGA packages refer to the

"(LF)BGA Application Note" (AN01026); order a copy

from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account

be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217

C measured in the atmosphere of the reflow oven. The package body peak temperature

must be kept as low as possible.

4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder

cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.

5. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

6. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not

suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted

on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar
soldering process. The appropriate soldering profile can be provided on request.

9. Hot bar soldering or manual soldering is suitable for PMFP packages.

PACKAGE

(1)

SOLDERING METHOD

WAVE

REFLOW

(2)

BGA, HTSSON..T

(3)

, LBGA, LFBGA, SQFP, SSOP..T

(3)

, TFBGA,

VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN, HVSON, SMS

not suitable

(4)

suitable

PLCC

(5)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(5)(6)

suitable

SSOP, TSSOP, VSO, VSSOP

not recommended

(7)

suitable

CWQCCN..L

(8)

, PMFP

(9)

, WQCCN..L

(8)

not suitable

2004 Nov 02

Philips Semiconductors

Product specification

DVB selective AGC amplifier

TDA9888TS; TDA9889TS

DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

LEVEL

DATA SHEET

STATUS

(1)

PRODUCT

STATUS

(2)(3)

DEFINITION

Objective data

Development

This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.

Preliminary data Qualification

This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.

III

Product data

Production

This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).

DEFINITIONS

Short-form specification

The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition

Limiting values given are in

accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information

Applications that are

described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.

DISCLAIMERS

Life support applications

These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes

Philips Semiconductors

reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status `Production'), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.

SCA76

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Philips Semiconductors a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

Printed in The Netherlands

R25/03/pp

Date of release:

2004 Nov 02

Document order number:

9397 750 14249

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA9888

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA9888

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA9888