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Электронный компонент: TDF8704T

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DATA SHEET
Product specification
Supersedes data of April 1993
File under Integrated Circuits, IC02
June 1994
INTEGRATED CIRCUITS
Philips Semiconductors
TDF8704
8-bit high-speed analog-to-digital
converter
June 1994
2
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
FEATURES
8-bit resolution
Sampling rate up to 50 MHz
Extended temperature range (
-
40 to +85
C)
High signal-to-noise ratio over a large analog input
frequency range (7.4 effective bits at 4.43 MHz full-scale
input and at f
clk
= 50 MHz)
Binary 3-state TTL outputs
Overflow/underflow 3-state TTL output
TTL compatible digital inputs
Low-level AC clock input signal allowed
Stable internal reference voltage regulator included
Power dissipation only 380 mW (typical)
Low analog input capacitance, no buffer amplifier
required
No sample-and-hold circuit required.
APPLICATIONS
General purpose high-speed analog-to-digital
conversion for extended temperature applications
Automotive
RF, satellite and GPS (Global Positioning System)
Medical
General industrial
Digital video (VCR, TV and satellite).
GENERAL DESCRIPTION
The TDF8704T is an 8-bit high-speed analog-to-digital
converter (ADC) for general industrial applications. It
converts the analog input signal into 8-bit binary-coded
digital words at a maximum sampling rate of 50 MHz. All
digital inputs and outputs are TTL compatible, although a
low-level AC clock input signal is allowed.
QUICK REFERENCE DATA
Note
1. Full-scale sine wave (f
i
= 4.43 MHz; f
clk
= 50 MHz).
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CCA
analog supply voltage
4.75
5.0
5.25
V
V
CCD
digital supply voltage
4.75
5.0
5.25
V
V
CCO
output stages supply voltage
4.75
5.0
5.25
V
I
CCA
analog supply current
-
37
46
mA
I
CCD
digital supply current
-
23
35
mA
I
CCO
output stages supply current
-
16
21
mA
ILE
DC integral linear error
-
0.4
1
LSB
DLE
DC differential linearity error
-
0.2
0.5
LSB
AILE
AC integral linearity error
note 1
-
-
2
LSB
f
clk(max)
maximum clock frequency
50
-
-
MHz
P
tot
total power dissipation
-
380
535
mW
TYPE NUMBER
PACKAGE
SAMPLING
FREQUENCY
PINS
PIN POSITION
MATERIAL
CODE
TDF8704T/2
24
SO24L
plastic
SOT137-1
20 MHz
TDF8704T/4
24
SO24L
plastic
SOT137-1
40 MHz
TDF8704T/5
24
SO24L
plastic
SOT137-1
50 MHz
June 1994
3
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
4
8
9
VRB
VI
VRT
7
VCCA
23
15
13
24 D2
D3
D4
D5
D6
1
2
12
D1
D0
D7
TTL OUTPUTS
CLOCK DRIVER
16
CLK
TDF8704
analog
voltage input
overflow / underflow
output
data outputs
LSB
MSB
14
ANALOG - TO - DIGITAL
CONVERTER
LATCHES
MSA685
17
DGND
6
AGND
analog ground
digital ground
18
VCCD
11
22
CE
STABILIZER
TTL OUTPUT
OVERFLOW / UNDERFLOW
LATCH
5
DEC
19
V
CCO1
21
V
CCO2
20
output ground
OGND
June 1994
4
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
PINNING
SYMBOL
PIN
DESCRIPTION
D1
1
data output; bit 1
D0
2
data output; bit 0 (LSB)
n.c.
3
not connected
V
RB
4
reference voltage BOTTOM
(decoupling)
DEC
5
decoupling input (internal
stabilization loop decoupling)
AGND
6
analog ground
V
CCA
7
analog supply voltage (+5 V)
V
I
8
analog input voltage
V
RT
9
reference voltage TOP (decoupling)
n.c.
10
not connected
O/UF
11
overflow/underflow data output
D7
12
data output; bit 7 (MSB)
D6
13
data output; bit 6
D5
14
data output; bit 5
D4
15
data output; bit 4
CLK
16
clock input
DGND
17
digital ground
V
CCD
18
digital supply voltage (+5 V)
V
CCO1
19
supply voltage for output stages 1
(+5 V)
OGND
20
output ground
V
CCO2
21
supply voltage for output stages 2
(+5 V)
CE
22
chip enable input (TTL level input,
active LOW)
D3
23
data output; bit 3
D2
24
data output; bit 2
Fig.2 Pin configuration.
handbook, halfpage
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
TDF8704
MSA686
D1
D0
n.c.
V RB
DEC
AGND
V CCA
VRT
n.c.
O/UF
D7
D6
D5
D4
CLK
VCCD
VCCO1
OGND
D3
D2
CE
DGND
VCCO2
V I
June 1994
5
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC134).
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CCA
analog supply voltage
-
0.3
+7.0
V
V
CCD
digital supply voltage
-
0.3
+7.0
V
V
CCO
output stages supply voltage
-
0.3
+7.0
V
V
CC
supply voltage differences between V
CCA
and V
CCD
-
1.0
+1.0
V
V
CC
supply voltage differences between V
CCO
and V
CCD
-
1.0
+1.0
V
V
CC
supply voltage differences between V
CCA
and V
CCO
-
1.0
+1.0
V
V
I
input voltage
referenced to AGND
-
0.3
+7.0
V
V
clk(p-p)
AC input voltage for switching (peak-to-peak value)
referenced to DGND
-
V
CCD
V
I
O
output current
-
10
mA
T
stg
storage temperature
-
55
+150
C
T
amb
operating ambient temperature
-
40
+85
C
T
j
junction temperature
-
+150
C
SYMBOL
PARAMETER
VALUE
UNIT
R
th j-a
thermal resistance from junction to ambient in free air
75
K/W
June 1994
6
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
CHARACTERISTICS (see Tables 1 and 2)
V
CCA
= V
7
to V
6
= 4.75 to 5.25 V; V
CCD
= V
18
to V
17
= 4.75 to 5.25 V; V
CCO
= V
19
and V
21
to V
20
= 4.75 to 5.25 V; AGND
and DGND shorted together; V
CCA
to V
CCD
=
-
0.25 to +0.25 V; V
CCO
to V
CCD
=
-
0.25 to +0.25 V;
V
CCA
to V
CCD
=
-
0.25 to +0.25 V; T
amb
=
-
40 to +85
C; typical readings taken at V
CCA
= V
CCD
= 5 V and T
amb
= 25
C;
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
V
CCA
analog supply voltage
4.75
5.0
5.25
V
V
CCD
digital supply voltage
4.75
5.0
5.25
V
V
CCO
output stages supply voltage
4.75
5.0
5.25
V
I
CCA
analog supply current
-
37
46
mA
I
CCD
digital supply current
-
23
35
mA
I
CCO
output stages supply current
all outputs LOW
-
16
21
mA
Inputs
C
LOCK INPUT
CLK (
REFERENCED TO
DGND)
V
IL
LOW level input voltage
0
-
0.8
V
V
IH
HIGH level input voltage
2.0
-
V
CCD
V
I
IL
LOW level input current
V
clk
= 0.4 V
-
400
-
-
A
I
IH
HIGH level input current
V
clk
= 2.7 V
-
-
100
A
V
clk
= V
CCD
-
-
300
A
Z
I
input impedance
f
clk
= 50 MHz
-
2
-
k
C
I
input capacitance
f
clk
= 50 MHz
-
4.5
-
pF
V
I
(
ANALOG INPUT VOLTAGE REFERENCED TO
AGDN;
SEE FIGS
3
AND
4
AND TABLE
1)
V
I(B)
input voltage (BOTTOM)
1.21
1.25
1.29
V
V
I(0)
input voltage
output code = 0
1.42
1.48
1.51
V
V
os(B)
offset voltage (BOTTOM)
V
I(0)
to V
I(B)
210
225
240
V
V
I(T)
input voltage (TOP)
3.37
3.46
3.58
V
V
I(255)
input voltage
output code = 255
3.14
3.22
3.30
V
V
os(T)
offset voltage (TOP)
V
I(T)
to V
I(255)
225
240
255
V
V
I(p-p)
input voltage amplitude
(peak-to-peak value)
1.69
1.74
1.79
V
I
L
load current on V
RT
and V
RB
-
300
-
+300
A
I
IL
LOW level input current
V
I
= 1.25 V
-
0
-
A
I
IH
HIGH level input current
V
I
= 3.46 V
40
150
400
A
Z
I
input impedance
f
i
= 4.43 MHz
-
10
-
k
C
I
input capacitance
f
i
= 4.43 MHz
-
14
-
pF
June 1994
7
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
I
NPUT
CE (
REFERENCED TO
DGND)
SEE TABLE
2
V
IL
LOW level input voltage
0
-
0.8
V
V
IH
HIGH level input voltage
2.0
-
V
CCD
V
I
IL
LOW level input current
V
IL
= 0.4 V
-
400
-
-
A
I
IH
HIGH level input current
V
IH
= 2.7 V
-
-
20
A
Reference resistance
R
ref
reference resistance
V
RT
to V
RB
-
200
-
Outputs
D
IGITAL OUTPUTS
D7
TO
D0 (
REFERENCED TO
DGND)
V
OL
LOW level output voltage
I
O
= 1 mA;
T
amb
= 0 to +85
C
0
-
0.4
V
I
O
= 1 mA;
T
amb
= 0 to
-
40
C
-
-
0.6
V
V
OH
HIGH level output voltage
I
O
=
-
0.4 mA
2.7
-
V
CCD
V
I
OZ
output current in 3-state
mode
0.4 V < V
O
< V
CCD
-
20
-
+20
A
Switching characteristics
C
LOCK INPUT
CLK (
NOTE
1;
SEE
F
IG
.15)
f
clk(max)
maximum clock frequency
TDF8704T/2
20
-
-
MHz
TDF8704T/4
40
-
-
MHz
TDF8704T/5
50
-
-
MHz
t
CPH
clock pulse width HIGH
7
-
-
ns
t
CPL
clock pulse width LOW
7
-
-
ns
Analog signal processing
L
INEARITY
ILE
DC integral linearity error
-
0.4
1.0
LSB
DLE
DC differential linearity error
-
0.2
0.5
LSB
AILE
AC integral linearity error
note 2
-
-
2.0
LSB
B
ANDWIDTH
(f
clk
= 40 MH
Z
)
B
-
0.5 dB analog bandwidth
(note 3)
full-scale sine wave
-
12
-
MHz
75% full-scale sine wave
-
16
-
MHz
t
STLH
analog input settling time
LOW-to-HIGH
full-scale square wave;
Fig.8; note 4
-
2.5
3.5
ns
t
STHL
analog input settling time
HIGH-to-LOW
full-scale square wave;
Fig.8; note 4
-
3.0
4.0
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
June 1994
8
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
H
ARMONICS
(f
clk
= 40 MH
Z
)
h
1
fundamental harmonics
(full scale)
f
i
= 4.43 MHz
-
-
0
dB
h
all
harmonics (full scale);
all components
f
i
= 4.43 MHz
second harmonics
-
-
64
-
60
dB
third harmonics
-
-
58
-
55
dB
THD
total harmonic distortion
f
i
= 4.43 MHz
-
-
56
-
dB
S
IGNAL
-
TO
-
NOISE RATIO
S/N
signal-to-noise ratio
without harmonics;
f
clk
= 40 MHz;
f
i
= 4.43 MHz
46
48
-
dB
E
FFECTIVE BITS
;
NOTE
5;
SEE FIGS
9, 10
AND
11
EB
effective bits
TDF8704T/2
f
clk
= 20 MHz
f
i
= 1.25 MHz
-
7.8
-
bits
f
i
= 4.43 MHz
-
7.6
-
bits
effective bits
TDF8704T/4
f
clk
= 40 MHz
f
i
= 4.43 MHz
-
7.5
-
bits
f
i
= 7.5 MHz
-
7.3
-
bits
f
i
= 10 MHz
-
7.0
-
bits
effective bits
TDF8704T/5
f
clk
= 50 MHz
f
i
= 4.43 MHz
-
7.4
-
bits
f
i
= 7.5 MHz
-
7.2
-
bits
f
i
= 10 MHz
-
6.9
-
bits
T
WO
-
TONE
(
NOTE
6)
TTIR
two-tone intermodulation
rejection
f
clk
= 40 MHz
-
-
56
-
dB
B
IT ERROR RATE
BER
bit error rate
f
clk
= 40 MHz;
f
i
= 4.43 MHz;
V
I
=
16 LSB at code 128
-
10
-
11
-
times/
samples
D
IFFERENTIAL GAIN
(
NOTE
7)
G
diff
differential gain
f
clk
= 20 MHz;
f
i
= 4.43 MHz
-
0.6
-
%
D
IFFERENTIAL PHASE
(
NOTE
7)
diff
differential phase
f
clk
= 40 MHz;
f
i
= 4.43 MHz
-
0.8
-
deg
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
June 1994
9
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must be less than 1 ns.
2. Full-scale sine wave (f
i
= 4.43 MHz; f
clk
= 50 MHz).
3. Determined by beat frequency method on a reconstructed sine wave signal for no missing codes and no glitches.
4. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.
5. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 4K acquisition points per period. The
calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency).
Conversion to signal-to-noise ratio: S/N = EB
6.02 + 1.76 dB.
6. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.
7. Measurement taken using video analyser VM700A.
8. Output data acquisition: the output data is available after the maximum delay time of t
d
.
Timing (note 8; see Figs 5 and 7; f
clk
= 50 MHz)
t
ds
sampling delay time
-
-
2
ns
t
h
output hold time
5
-
-
ns
t
d
output delay time
-
12
15
ns
3-state output delay times (see Figs 6 and 7)
t
dZH
enable HIGH
-
6
10
ns
t
dZL
enable LOW
-
12
16
ns
t
dHZ
disable HIGH
-
50
54
ns
t
dLZ
disable LOW
-
10
14
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Fig.3
Influence of T
amb
on V
I(T)
and V
I(B)
under
5 V supply.
handbook, halfpage
60
3.49
3.43
3.45
3.47
MBD868
1.29
1.23
1.25
1.27
V I (T)
(V)
VI (B)
(V)
20
20
60
100
T ( C)
o
0.1 mV/K
0.05 mV/K
VI (T)
VI (B)
amb
Fig.4
Influence of supply voltage on V
I(T)
and
V
I(B)
under T
amb
= 25
C.
andbook, halfpage
4.25
4.75
5.75
3.44
3.38
3.40
3.42
MSA689
5.25
1.28
1.22
1.24
1.26
V I (T)
(V)
V I (B)
(V)
17 mV/V
7 mV/V
V (V)
CC
VI (T)
V I (B)
June 1994
10
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
Table 1
Output coding and input voltage (typical values; referenced to AGND).
Table 2
Mode selection.
STEP
V
I(p-p)
O/UF
BINARY OUTPUT BITS
D7
D6
D5
D4
D3
D2
D1
D0
Underflow
<
1.48
1
1
0
0
0
0
0
0
0
0
1.48
0
0
0
0
0
0
0
0
0
1
-
0
0
0
0
0
0
0
0
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
254
.
0
1
1
1
1
1
1
1
0
255
3.46
0
1
1
1
1
1
1
1
1
Overflow
>
3.46
1
1
1
1
1
1
1
1
1
CE
D7 TO D0
O/UF
1
high impedance
high impedance
0
active; binary
active
Fig.5 Timing diagram for data output.
handbook, full pagewidth
ds
t
sample N 1
N
sample N
CLK
MSA688 - 1
sample N 2
1.4 V
V l
DATA
D0 to D7
t h
CPH
t
CPL
t
t d
2.4 V
0.4 V
1.4 V
DATA
N 1
DATA
N
DATA
N 1
DATA
N 2
June 1994
11
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
handbook, full pagewidth
MLB880
50 %
50 %
HIGH
LOW
dZH
t
dHZ
t
50 %
HIGH
LOW
dZL
t
dLZ
t
10 %
90 %
output
data
CE
VCCD
output
data
3.3 k
15 pF
S1
VCCD
TDF8704
CE
Fig.6 Timing diagram and test conditions of 3-state output delay time.
TEST
S1
t
dLZ
V
CCD
t
dZL
V
CCD
t
dHZ
GND
t
dZH
GND
f
CE
= 100 kHz.
Fig.7 Load circuit for timing measurement.
handbook, halfpage
MBB956 - 1
D0 to D7
15 pF
June 1994
12
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
Fig.8 Analog input settling-time diagram.
handbook, full pagewidth
MBD869
50 %
STLH
t
2 ns
code 0
code 255
I
50 %
0.5 ns
50 %
2 ns
STHL
t
50 %
0.5 ns
CLK
V
Fig.9 Fast Fourier Transform (f
clk
= 20 MHz; f
i
= 1.25 MHz).
Effective bits: 7.89; THD =
-
61.05 dB.
Harmonic levels (dB): 2nd =
-
84.07; 3rd =
-
62.50; 4th =
-
92.01; 5th =
-
66.56; 6th =
-
101.15.
handbook, full pagewidth
3.74
0
120
0
1.25
2.49
MBD870
40
80
8.72
4.98
6.23
7.47
9.96
f (MHz)
100
20
60
amplitude
(dB)
June 1994
13
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
Fig.10 Fast Fourier Transform (f
clk
= 40 MHz; f
i
= 4.43 MHz).
Effective bits: 7.61; THD =
-
57.11 dB.
Harmonic levels (dB): 2nd =
-
68.53; 3rd =
-
58.36; 4th =
-
74.89; 5th =
-
65.37; 6th =
-
76.08.
handbook, full pagewidth
7.44
0
120
0
2.48
4.96
MBD871
40
80
17.4
9.93
12.4
14.9
19.9
f (MHz)
100
20
60
amplitude
(dB)
Fig.11 Fast Fourier Transform (f
clk
= 50 MHz; f
i
= 10 MHz).
Effective bits: 6.91; THD =
-
46.13 dB.
Harmonic levels (dB): 2nd =
-
59.66; 3rd =
-
46.67; 4th =
-
70.80; 5th =
-
57.96; 6th =
-
72.16.
handbook, full pagewidth
9.35
0
120
0
3.12
6.24
MBD872
40
80
21.8
12.5
15.6
18.7
24.9
f (MHz)
100
20
60
amplitude
(dB)
June 1994
14
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
INTERNAL PIN CONFIGURATIONS
Fig.12 TTL data and overflow/underflow outputs.
handbook, halfpage
MLB036
DGND
D7 to D0
O/UF
VCCO2
VCCO1
Fig.13 Analog inputs.
handbook, halfpage
MLB037
AGND
V CCA
(x 90)
V I
Fig.14 CE (3-state) input.
book, halfpage
MLB038
DGND
VCCO1
CE
June 1994
15
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
Fig.15 V
RB,
V
RT
and DEC.
handbook, full pagewidth
VRB
VRT
V CCA
DEC
AGND
MSA687
Fig.16 CLK input.
handbook, full pagewidth
30 k
30 k
V
VCCD
CLK
DGND
MCD189 - 1
ref
June 1994
16
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
APPLICATION INFORMATION
Fig.17 Application diagram.
The analog and digital supplies should be separated and decoupled.
(1) V
RB
and V
RT
are decoupling pins for the internal reference ladder; do not draw current from these pins in order to achieve good linearity.
(2) Pins 3 and 10 should be connected to DGND in order to prevent noise influence.
handbook, halfpage
MSA684
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
D0
D1
D2
D3
D4
D5
D6
OGND
CLK
n.c.
DEC
O / UF
D7
n.c.
DGND
CE
V
RB
VRT
VI
V
CCA
V
CCD
AGND
V
CCO1
47 pF
10 nF
AGND
AGND
100 nF
AGND
V
CCO2
TDF8704
(1)
(1)
(2)
(2)
June 1994
17
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
PACKAGE OUTLINE
Fig.18 Plastic small outline package; 24 leads; large body; SOT137-1.
Dimensions in mm.
handbook, full pagewidth
7.6
7.4
10.65
10.00
A
MBC235 - 1
0.3
0.1
2.45
2.25
1.1
0.5
0.32
0.23
1.1
1.0
0 to 8
o
2.65
2.35
detail A
S
15.6
15.2
0.1 S
1
12
13
24
pin 1
index
0.9
0.4
(4x)
0.25 M
(24x)
0.49
0.36
1.27
June 1994
18
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
SOLDERING
Plastic small-outline packages
B
Y WAVE
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Maximum permissible solder temperature is 260
C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150
C within 6 s.
Typical dwell time is 4 s at 250
C.
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
B
Y SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250
C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45
C.
R
EPAIRING SOLDERED JOINTS
(
BY HAND
-
HELD SOLDERING
IRON OR PULSE
-
HEATED SOLDER TOOL
)
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300
C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320
C. (Pulse-heated soldering is not recommended
for SO packages.)
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
June 1994
19
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
NOTES
Philips Semiconductors
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SCD31
Philips Electronics N.V. 1994
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Printed in The Netherlands
533061/1500/03/pp20
Date of release: June 1994
Document order number:
9397 734 10011