DATA SHEET
Preliminary specification
Supersedes data of 1999 Jan 14
File under Integrated Circuits, IC03
1999 Oct 21
INTEGRATED CIRCUITS
TEA1207T
High efficiency DC/DC converter
1999 Oct 21
2
Philips Semiconductors
Preliminary specification
High efficiency DC/DC converter
TEA1207T
FEATURES
Fully integrated DC/DC converter circuit
Up-or-down conversion
Start-up from 1.85 V input voltage
Adjustable output voltage
High efficiency over large load range
Power handling capability up to 0.85 A continuous
average current
275 kHz switching frequency
Low quiescent power consumption
Synchronizing with external clock
True current limit for Li-ion battery compatibility
Up to 100% duty cycle in down mode
Undervoltage lockout
Shut-down function
8-pin SO package.
APPLICATIONS
Cellular and cordless phones, Personal Digital
Assistants (PDAs) and others
Supply voltage source for low-voltage chip sets
Portable computers
Battery backup supplies
Cameras.
GENERAL DESCRIPTION
The TEA1207T is a fully integrated DC/DC converter.
Efficient, compact and dynamic power conversion is
achieved using a novel digitally controlled concept like
Pulse Width Modulation (PWM) or Pulse Frequency
Modulation (PFM), integrated low R
DSon
CMOS power
switches with low parasitic capacitances, and fully
synchronous rectification.
The device operates at 275 kHz switching frequency
which enables the use of external components with
minimum size. Deadlock is prevented by an on-chip
undervoltage lockout circuit.
Efficient behaviour during short load peaks and
compatibility with Li-ion batteries is guaranteed by an
accurate current limiting function.
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TEA1207T
SO8
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
1999 Oct 21
3
Philips Semiconductors
Preliminary specification
High efficiency DC/DC converter
TEA1207T
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Voltage levels
U
PCONVERSION
; pin U/D = LOW
V
I
input voltage
V
I(start)
-
5.50
V
V
O
output voltage
2.80
-
5.50
V
V
I(start)
start-up input voltage
I
L
< 125 mA
1.40
1.60
1.85
V
D
OWNCONVERSION
; pin U/D = HIGH
V
I
input voltage
2.80
-
5.50
V
V
O
output voltage
1.30
-
5.50
V
G
ENERAL
V
fb
feedback voltage
1.19
1.24
1.29
V
Current levels
I
q
quiescent current on pin 3
down mode; V
I
= 3.6 V 52
65
72
A
I
shdwn
current in shut-down state
-
2
10
A
I
LX
maximum continuous current on pin 4
T
amb
= 80
C
-
-
0.60
A
I
lim
current limit deviation
I
lim
= 0.5 to 5 A
up mode
-
17.5
-
+17.5
%
down mode
-
17.5
-
+17.5
%
Power MOSFETs
R
DSon
drain-to-source on-state resistance
N-type
0.10
0.20
0.30
P-type
0.10
0.22
0.35
Efficiency
1
efficiency upconversion
V
I
= 3.6 V; V
O
= 4.6 V;
L1 = 10
H
I
L
= 1 mA
-
88
-
%
I
L
= 200 mA
-
95
-
%
I
L
= 1 A; pulsed
-
83
-
%
2
efficiency downconversion
V
I
= 3.6 V; V
O
= 2.0 V;
L1 = 10
H
I
L
= 1 mA
-
86
-
%
I
L
= 200 mA
-
93
-
%
I
L
= 1 A; pulsed
-
81
-
%
Timing
f
sw
switching frequency
PWM mode
220
275
330
kHz
f
sync
synchronization clock input frequency
4
6.5
20
MHz
t
res
response time
from standby to P
0(max)
-
50
-
s
1999
Oct
21
4
Philips Semiconductors
Preliminar
y specification
High efficiency DC/DC con
v
e
r
ter
TEA1207T
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BLOCK DIA
GRAM
a
ndbook, full pagewidth
MGR665
CONTROL LOGIC
AND
MODE GEARBOX
START-UP
CIRCUIT
I/V
CONVERTER
INTERNAL
SUPPLY
I/V
CONVERTER
TIME
COUNTER
BAND GAP
REFERENCE
13 MHz
OSCILLATOR
SYNC
GATE
TEMPERATURE
PROTECTION
DIGITAL CONTROLLER
sense FET
P-type POWER FET
sense
FET
SHDWN
GND
SYNC
U/D
N-type
POWER
FET
LX
UPOUT/DNIN
FB
TEA1207T
5
6
8
1
4
ILIM
2
3
7
CURRENT LIMIT
COMPARATORS
Fig.1 Block diagram.
1999 Oct 21
5
Philips Semiconductors
Preliminary specification
High efficiency DC/DC converter
TEA1207T
PINNING
SYMBOL
PIN
DESCRIPTION
U/D
1
up-or-down mode selection
input; active LOW for up mode
ILIM
2
current limiting resistor
connection
UPOUT/DNIN
3
output voltage in up mode;
input voltage in down mode
LX
4
inductor connection
SYNC
5
synchronization clock input
GND
6
ground
FB
7
feedback input
SHDWN
8
shut-down input
Fig.2 Pin configuration.
handbook, halfpage
MGR666
1
2
3
4
8
7
6
5
U/D
SHDWN
ILIM
FB
UPOUT/DNIN
GND
LX
SYNC
TEA1207T
FUNCTIONAL DESCRIPTION
Control mechanism
The TEA1207T DC/DC converter is able to operate in PFM
(discontinuous conduction) or PWM (continuous
conduction) operating mode. All switching actions are
completely determined by a digital control circuit which
uses the output voltage level as its control input. This novel
digital approach enables the use of a new pulse width and
frequency modulation scheme, which ensures optimum
power efficiency over the complete operating range of the
converter.
When high output power is requested, the device will
operate in PWM (continuous conduction) operating mode.
This results in minimum AC currents in the circuit
components and hence optimum efficiency, minimum
costs and low EMC. In this operating mode, the output
voltage is allowed to vary between two predefined voltage
levels. As long as the output voltage stays within this
so-called window, switching continues in a fixed pattern.
When the output voltage reaches one of the window
borders, the digital controller immediately reacts by
adjusting the pulse width and inserting a current step in
such a way that the output voltage stays within the window
with higher or lower current capability. This approach
enables very fast reaction to load variations. Figure 3
shows the converter's response to a sudden load
increase. The upper trace shows the output voltage.
The ripple on top of the DC level is a result of the current
in the output capacitor, which changes in sign twice per
cycle, times the capacitor's internal Equivalent Series
Resistance (ESR). After each ramp-down of the inductor
current, i.e. when the ESR effect increases the output
voltage, the converter determines what to do in the next
cycle. As soon as more load current is taken from the
output the output voltage starts to decay.
When the output voltage becomes lower than the low limit
of the window, a corrective action is taken by a ramp-up of
the inductor current during a much longer time. As a result,
the DC current level is increased and normal PWM control
can continue. The output voltage (including ESR effect) is
again within the predefined window. Figure 4 depicts the
spread of the output voltage window. The absolute value
is most dependent on spread, while the actual window size
is not affected. For one specific device, the output voltage
will not vary more than 2% typically.
In low output power situations, the TEA1207T will switch
over to PFM (discontinuous conduction) operating mode.
In this mode, regulation information from earlier PWM
operating modes is used. This results in optimum inductor
peak current levels in the PFM mode, which are slightly
larger than the inductor ripple current in the PWM mode.
As a result, the transition between PFM and PWM mode is
optimum under all circumstances. In the PFM mode the
TEA1207T regulates the output voltage to the high window
limit as shown in Fig.3.
Synchronous rectification
For optimum efficiency over the whole load range,
synchronous rectifiers inside the TEA1207T ensure that
during the whole second switching phase, all inductor
current will flow through the low-ohmic power MOSFETs.
Special circuitry is included which detects that the inductor
current reaches zero. Following this detection, the digital
controller switches off the power MOSFET and proceeds
regulation.
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