2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

CONTENTS

FEATURES

1.1

General

1.2

Stereo decoder and noise blanking

1.3

Weak signal processing

1.4

Audio pre-amplifier

GENERAL DESCRIPTION

ORDERING INFORMATION

QUICK REFERENCE DATA

BLOCK DIAGRAM

PINNING

FUNCTIONAL DESCRIPTION

7.1

Stereo decoder

7.2

FM noise blanker

7.3

AM noise blanker

7.4

Multipath/fading detection and weak signal
control

7.5

Tone/volume control

7.5.1

Source selector

7.5.2

Loudness

7.5.3

Volume 1

7.5.4

Treble

7.5.5

Bass

7.5.6

Volume 2

7.5.7

RSA selector

7.5.8

Chime adder

LIMITING VALUES

THERMAL CHARACTERISTICS

CHARACTERISTICS

C-BUS PROTOCOL

11.1

Read mode: 1st data byte

11.2

Read mode: 2nd data byte

11.3

Subaddress byte for write

11.4

Write mode: subaddress 0H

11.5

Write mode: subaddress 1H

11.6

Write mode: subaddress 2H

11.7

Write mode: subaddress 3H

11.8

Write mode: subaddress 4H

11.9

Write mode: subaddress 5H

11.10

Write mode: subaddress 6H

11.11

Write mode: subaddress 7H

11.12

Write mode: subaddress 8H

11.13

Write mode: subaddress 9H

11.14

Write mode: subaddress AH

11.15

Write mode: subaddress BH

11.16

Write mode: subaddress CH

INTERNAL CIRCUITRY

PACKAGE OUTLINE

SOLDERING

14.1

Introduction to soldering surface mount
packages

14.2

Reflow soldering

14.3

Wave soldering

14.4

Manual soldering

14.5

Suitability of surface mount IC packages for
wave and reflow soldering methods

DATA SHEET STATUS

DEFINITIONS

DISCLAIMERS

PURCHASE OF PHILIPS I

C COMPONENTS

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

FEATURES

1.1

General

�

C-bus compatible

�

Digital alignment/adjustment via I

C-bus:

� FM noise blanker sensitivity

� FM stereo noise canceller

� FM High Cut Control (HCC)

� FM stereo separation.

�

FM audio processing hold for RDS updating; holds the
detectors for the FM weak signal processing in their
present state

�

FM bandwidth limiting; limits the bandwidth of the FM
audio signal with external capacitors

�

AM stereo input; AM stereo audio can be fed in at the
pins for the de-emphasis capacitors; this will provide
8 dB of gain to the AM audio.

1.2

Stereo decoder and noise blanking

�

FM stereo decoder

�

Accepts FM multiplex signal and AM audio at input

�

Pilot detector and pilot canceller

�

De-emphasis selectable between 75 and 50

�

AM noise blanker: impulse noise detector and an audio
hold.

1.3

Weak signal processing

�

FM weak signal processing: six signal condition
detectors, soft mute, stereo noise canceller (blend), and
High Cut Control (roll-off).

1.4

Audio pre-amplifier

�

Source selector for 6 sources: 2 stereo inputs external
(A and B), 1 symmetrical stereo input (C), 1 symmetrical
mono input (D), 1 internal stereo input (AM or FM), and
1 chime/diagnostic mono input

�

Volume 1 control from +20 to

56 dB in 1 dB steps;

programmable 20 dB loudness control included

�

Volume 2 control from 0 to

56 dB in 1 dB steps,

56,

58.5,

62,

68 dB and mute

�

Programmable loudness control with bass boost as well
as bass and treble boost

�

Treble control from

14 to +14 dB in 2 dB steps

�

Bass control from

18 to +18 dB in 2 dB steps with

selectable characteristic

�

Analog Step Interpolation (ASI) minimizes pops by
smoothing out the transitions in the audio signal when a
switch is made

�

Audio Blend Control (ABC) minimizes pops by
automatically incrementing the volume and loudness
controls through each step between their present
settings and the new settings

�

Rear Seat Audio (RSA) can select different sources for
the front and rear speakers

�

Chime input: can be sent to any audio output, at any
volume level

�

Chime adder circuit: chime input can also be summed
with left front and/or right front audio, or be turned off.

GENERAL DESCRIPTION

The TEA6880H is a monolithic bipolar integrated circuit
providing the stereo decoder function and ignition noise
blanking facility combined with source selector and
tone/volume control for AM/FM car radio applications. The
device operates with a power supply voltage range of
7.8 to 9.2 V and a typical current consumption of 40 mA.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TEA6880H

QFP64

plastic quad flat package; 64 leads (lead length 1.95 mm);
body 14

�

2.8 mm

SOT319-2

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

supply voltage

7.8

8.5

9.2

supply current

Stereo decoder path

S/N

signal-to-noise ratio

THD

total harmonic distortion

0.1

channel separation

o(rms)

output voltage level at pins ROPO and
LOPO

FM: 91% modulation;
AM: 100% modulation;
f

mod

= 400 Hz

840

950

1060

Tone volume control

o(rms)

maximum output voltage level at pins
LF, LR, RF and RR

= 8.5 V; THD

0.1%

2000

voltage gain

1 dB steps

112

+20

step(vol)

step resolution (volume)

bass

bass control

+18

treble

treble control

+14

step(treble, bass)

step resolution (bass and treble)

(S + N)/N

signal-plus-noise to noise ratio

= 2.0 V; G

= 0 dB;

unweighted

107

THD

total harmonic distortion

o(rms)

= 1.0 V; G

= 0 dB

0.01

100

ripple rejection

r(rms)

< 200 mV;

f = 100 Hz; G

= 0 dB

CMRR

common mode rejection ratio
differential stereo input

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

BLOCK DIAGRAM

Fig.1 Block diagram (continued in Fig.2).

MHB427

handbook, full pagewidth

50/75

�

DE-EMPHASIS

AM STEREO INPUT

FM BUFFER

FM NB-GATES

MATRIX

SOFT-MUTE

V/I

CONVERTER

STEREO

DECODER

PLL

INPUT BUFFER

80 kHz

LOW-PASS

STEREO

DECODER

OUTPUT

AVERAGE

DETECTOR

(USN1)

AVERAGE

DETECTOR

(WBAM1)

PEAK

DETECTOR

(USN2)

AVERAGE

DETECTOR

(MUTE/HCC)

GATE

LEVEL

ADC

(6-BIT)

LEVEL

INPUT

BUFFER

20 kHz

BAND-PASS

AMWB

DETECTOR

HCC

SNC

de-emphasis
switch

C-BUS

CONTROL LOGIC

C-bus

to NICE

from AM/FM

level detector

C-bus

detector hold

detector reset

test

NOISE

INTERFERENCE

DETECTOR

PULSE

FORMER

sensitivity

start/
slope

BUS

start/

slope

38 kHz

19 kHz

38 kHz

mute slope

mute start

bus controls

22 k

82 k

100 k

22 k

VDD(I

C-bus)

4.7 nF

10 nF

4.7 nF

2.7 nF

3.3 nF

49 48 47

10 nF

220 nF

�

10 nF

3.3 nF

220 nF

33 pF

PEAK

DETECTOR

(WBAM2)

PEAK

DETECTOR

(SNC)

detector
hold

detector
reset

test

sep.adj.

60 kHz

HIGH-PASS

USN

DETECTOR

PULSE

SEPARATOR

120 kHz

HIGH-PASS

AMPLIFIER

sensitivity

pilot

ind.

MPX
input

AMNBIN

MPXRDS

RIN 182 k

470 k

100 nF

6.8 nF

100
nF

22
nF

6.8 nF

68 k

10 nF

100 nF

100
k

220 k

33 nF

mono

input

audio

processing hold

(for RDS update)

from

NICE

(AFSAMPLE)

fref

(75.4 kHz)

trigger sensitivity

TEA6880H

AGC

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

Fig.2 Block diagram (continued from Fig.1).

MHB428

handbook, full pagewidth

INTERNAL

POWER

SUPPLY

PEAK

AVERAGE

DETECTOR

PULSE

FORMER

SOURCE SELECTOR

REAR SEAT AUDIO SELECTOR

USN
ADC

(3-BIT)

BUS

address

select

input

diagnostic

chime

left

right

VCC

(

8.5 V)

100 nF

CELFI
22

�

common

�

220
nF

right

220nF

AUDIO

BLEND CONTROL

(ABC)

ANALOG STEP

INTERPOLATION

(ASI)

WBAM

ADC

(3-BIT)

BUS

LOUDNESS

LEFT

CHIME ADDER

(G =

20 dB)

SWITCH

330
pF

15 nF

10
nF

220
nF

3.3
k

220 nF

3.3 k

68 nF

680 nF

CKVR

220 nF

4.7 k

43 k

68
nF

680 pF

220 nF

CKVL

4.7 k

43 k

10 nF

100 nF

�

220 nF

CKIL

CVHS

220 nF

CKIR

A left

100 nF

A right

C left

AM noise

blanker flag

left front

output

left rear

output

TEA6880H

BUS

CHIME ADDER

(G =

20 dB)

SWITCH

right front

output

BUS

VOLUME 1

LEFT

TREBLE

BAND

LEFT

BASS

BAND

VOLUME 2

LEFT

FRONT

REAR

SEAT

AUDIO

SWITCH

VOLUME 2

LEFT

REAR

VOLUME 2

RIGHT

REAR

ASI/ABC

control

ASI

ABC

LOUDNESS

RIGHT

BUS

VOLUME 1

RIGHT

TREBLE

BAND

RIGHT

BASS

BAND

ASI

ABC

BUS

right rear

output

BUS

VOLUME 2

RIGHT

FRONT

BUS

D input

mono

symmetric

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

PINNING

SYMBOL

PIN

DESCRIPTION

SDAQ

data output (to TEA6840H)

SCLQ

clock output (to TEA6840H)

LEVEL

FM and AM level input (from TEA6840H)

SCL

C-bus clock

SDA

C-bus data

DGND

digital ground

TBL

time constant for FM modulation detector

supply voltage

CHIME

chime tone input

AGND

analog ground

LLN

loudness left network

LOPI

left option port input (terminal impedance typical 100 k

)

LOPO

left option port output

BRI

channel B right stereo input (terminal impedance typical 100 k

)

ADR

address select

BLI

channel B left stereo input (terminal impedance typical 100 k

)

SCAP

supply filter capacitor

CRIP

channel C right symmetrical input (terminal impedance typical 30 k

)

CCOM

channel C common input (terminal impedance typical 30 k

)

CLIP

channel C left symmetrical input (terminal impedance typical 30 k

)

MONOC

mono common input (terminal impedance typical 30 k

)

MONOP

mono symmetrical input (terminal impedance typical 30 k

)

VHS

half supply filter capacitor

ARI

channel A right stereo input (terminal impedance typical 100 k

)

AMNCAP

peak-to-average detector capacitor for AM noise blanker

ALI

channel A left stereo input (terminal impedance typical 100 k

)

ROPO

right option port output

ROPI

right option port input (terminal impedance typical 100 k

)

RLN

loudness right network

RTC

right treble capacitor

RBI

right bass network input

RBO

right bass network output

right front output

right rear output

ASICAP

analog step interpolate capacitor

left rear output

left front output

LBO

left bass network output

LBI

left bass network input

LTC

left treble capacitor

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

AMPCAP

AM blanking time capacitor

AMHOLD

AM noise blanker flag

AMHCAP

AM noise blanker hold capacitor

ref

temperature independent reference current

TWBAM2

time constant for AM wideband peak detector

TUSN2

time constant for ultrasonic noise peak detector

PHASE

phase detector

ref

frequency reference input (75.4 kHz from TEA6840H)

PILOT

pilot on/off output

AFSAMPLE

reset for multipath detector (from TEA6840H for RDS update)

FMHOLD

FM audio processing hold input (from TEA6840H for RDS update)

AMHIN

AM signal input (from TEA6840H)

AMNBIN

AM noise blanker input (from TEA6840H)

TMUTE

time constant for soft mute

MPXRDS

unmuted MPX input (from TEA6840H for RDS update)

TSNC

time constant for stereo noise canceller

MPXIN

MPX input (from TEA6840H)

FMNCAP

FM noise detector capacitor

DEEML

left de-emphasis capacitor

DEEMR

right de-emphasis capacitor

FMLBUF

left AM/FM audio buffer capacitor

FMRBUF

right AM/FM audio buffer capacitor

TWBAM1

time constant for AM wideband average detector

TUSN1

time constant for ultrasonic noise average detector

SYMBOL

PIN

DESCRIPTION

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

FUNCTIONAL DESCRIPTION

7.1

Stereo decoder

The MPX input is the null-node of an operational amplifier
with internal feedback resistor. Adapting the stereo
decoder input to the level of the MPX signal, coming from
the FM demodulator output, is realized by the value of the
input series resistor R

. To this input a second source

(AM detector output) can be fed by current addition.

The input amplifier is followed by an integrated 4th order
Bessel low-pass filter with a cut-off frequency of 80 kHz.
It provides necessary signal delay for FM noise blanking
and damping of high frequency interferences coming to
the stereo decoder input.

Output of this filter is fed to the soft mute control circuitry,
the output is voltage to current converted and then fed to
phase detector, pilot detector and pilot canceller circuits,
contained in the stereo decoder PLL block. For
regeneration of the 38 kHz subcarrier, a PLL is used.
The fully integrated oscillator is adjusted by means of a
digital auxiliary PLL into the capture range of the main PLL.
The auxiliary PLL needs an external reference frequency
(75.4 kHz) which is provided by the TEA6840H.
The required 19 and 38 kHz signals are generated by
division of the oscillator output signal in a logical circuitry.
The 19 kHz quadrature phase signal is fed to the 19 kHz
phase detector, where it is compared with the incoming
pilot tone. The DC output signal of the phase detector
controls the oscillator (PLL).

The pilot presence detector is driven by an internally
generated in-phase 19 kHz signal. Its pilot dependent DC
output voltage is fed to a threshold switch, which activates
the pilot indicator bit and turns the stereo decoder to stereo
operation. The same DC voltage is used to control the
amplitude of an anti-phase internally generated 19 kHz
signal. In the pilot canceller, the pilot tone is compensated
by this anti-phase 19 kHz signal.

The pilot cancelled signal is fed to the matrix. There, the
side signal is demodulated and combined with the main
signal to left and right audio channel. Compensation for
roll-off in the incoming MPX signal caused by IF filters and
FM demodulator is typically realized by an external
compensation network at pin 57, individual alignment is
achieved by I

C-bus controlled amplification of the side

signal (DAA). A smooth mono to stereo takeover is
achieved by controlling the efficiency of the matrix with
help of the SNC peak detector.

The matrix is followed by the FM noise suppression gates,
which are combined with FM single poles and High Cut
Control (HCC). The single pole is defined by internal
resistors and external capacitors. From the gate circuits
audio is fed to the switchable de-emphasis, where the
demodulated AM stereo signal can be fed in. After
de-emphasis the signal passes to the output buffers and is
fed to the radio input of the source selector. For HCC, the
time constant of the single pole contained in the output
buffer can be changed to higher values. This function is
controlled by an average detector contained in the
multipath and fading detector.

7.2

FM noise blanker

The input of the ignition noise blanker is coupled to the
MPXRDS (pin 55) input signal and to the IF level input
(pin 3). Both signals are fed via separate 120 kHz filters
and rectifiers to an adder circuit. The output signal of the
adder circuit is fed in parallel to the noise detector and the
interference detector. The noise detector is a negative
peak detector. Its output controls the trigger sensitivity
(prevention to false triggering at noisy input signals) and
the gain of the MPX high-pass filter. The output of the
interference detector, when receiving a steep pulse, fires a
monoflop, contained in the pulse former circuitry. The time
constant of the monoflop is defined by an internal capacitor
and its output activates the blanking gates in the audio.

7.3

AM noise blanker

The AM noise blanking pulse is derived from the AM audio
signal which is fed into pin 53 with the help of a
peak-to-average comparator. The blanking time is set by a
pulse former with external capacitor. The blanking pulse is
fed to the gate in the AM audio path and out to pin
AMHOLD to operate the gate built into the external
AM stereo processor.

7.4

Multipath/fading detection and weak signal
control

For FM signal quality dependent controls there is built-in a
combination of six detectors driven by the level information
direct, by the AC components on the level via a 20 kHz
band-pass filter (AM wideband) or the high notes present
at the FM demodulator output via a 60 kHz high-pass filter
(ultrasonic noise). The relation between DC level and the
AC components is programmable by the I

C-bus (2 bits

each). Output of level buffer, AM wideband detector and
ultrasonic noise detector are analog-to-digital converted
and readable by the I

C-bus.

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

For the time of fast RDS updating soft mute, SNC and
HCC can be put on hold and the AM wideband peak
detector and the ultrasonic noise peak detector are put on
reset by a switch signal delivered from the TEA6840H via
pin 51 (FMHOLD).

The six separate detecting circuits are:

1. The AM wideband noise peak detector is driven from

a 20 kHz band-pass filter connected to the level buffer
output. The time constant is defined by an external
capacitor at pin 45 (TWBAM2). The output voltage of
the detector is analog-to-digital converted by 3-bit.

2. The AM wideband noise average detector is driven

from a 20 kHz band-pass filter connected to the level
buffer output. The time constant is defined by an
external capacitor at pin 63 (TWBAM1). The output of
the detector is connected to the Stereo Noise Control
(SNC) circuit.

3. The ultrasonic noise peak detector is driven from a

60 kHz high-pass filter connected to the MPX signal
from pin 55 (MPXRDS). The time constant is defined
by an external capacitor at pin 46 (TUSN2). The output
voltage of the detector is analog-to-digital converted
by 3-bit.

4. The ultrasonic noise average detector is driven from a

60 kHz high-pass filter connected to the MPX signal
from pin 55 (MPXRDS). The time constant is defined
by an external capacitor at pin 64 (TUSN1). The output
of the detector is connected to soft mute control and
stereo noise control circuits.

5. For soft mute and high cut control purposes an

average detector with externally defined time constant
(TMUTE, pin 54) is provided. The detector is driven by
level output only. Soft mute as well as high cut control
can be switched off by the I

C-bus.

6. The stereo noise control peak detector with externally

defined time constant (TSNC, pin 56) is driven by
DC level output, AM wideband and ultrasonic noise
outputs. It provides the stereo blend facility (SNC).
Starting point and slope of stereo blend can be chosen
by the I

C-bus controlled reference voltage.

7.5

Tone/volume control

The tone/volume control part consists of the following
functions:

�

Source selector

�

Loudness

�

Volume 1

�

Treble

�

Bass

�

Volume 2

�

Rear Seat Audio (RSA) selector

�

Chime adder

�

Analog step interpolation

�

Audio blend control.

The stages loudness, volume 1, bass, and volume 2
include the Analog Step Interpolation (ASI) function. This
minimizes pops by smoothing out the transitions in the
audio signal during switching. The transition time is
I

C-bus programmable in a range of 1 : 24 in four steps.

The stages loudness, volume 1, and volume 2 also have
the Audio Blend Control (ABC) function. This minimizes
pops by automatically incrementing the volume and
loudness controls through each step between their present
settings and the new settings. The speed of the ABC
function is correlated with the transition time of the ASI
function.

All stages are controlled via the I

C-bus.

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

7.5.1

OURCE SELECTOR

The source selector allows the selection between
6 sources:

�

2 external stereo inputs (ALI, ARI, BLI and BRI)

�

1 external symmetrical stereo input (CLIP, CRIP and
CCOM)

�

1 external symmetrical mono input (MONOP and
MONON)

�

1 internal stereo input (AM/FM)

�

1 chime/diagnostic mono input (CHIME).

Via the chime/diagnostic mono input a chime input signal
can be sent to any audio output, at any volume level.

7.5.2

OUDNESS

The output of the source selector is fed into the loudness
circuit via the external capacitors C

KVL

(pins LOPO and

LOPI) and C

KVR

(pins ROPO and ROPI). Depending on

the external circuits for the left and the right channel only a
bass boost or bass and treble boost is available. With the
external circuits shown in Figs 13 and 15 the curves from
Figs 14 and 16 will be obtained (without influence of C

KVL

respectively C

KVR

7.5.3

OLUME

The volume 1 control follows behind the loudness circuit.
The control range of volume 1 is between +20 and

36 dB

in steps of 1 dB.

7.5.4

REBLE

The output signal of the volume 1 control is fed into the
treble control stage. The control range is between
+14 and

14 dB in steps of 2 dB. Fig.20 shows the control

characteristic with external capacitors of 10 nF.

7.5.5

ASS

The bass control is the next stage. The characteristic of the
bass curves depends upon the external circuits at
pins LBO/LBI (left channel) and RBO/RBI (right channel)
and also upon the setting of BSYM bit (MSB of the bass
control byte). With BSYM = 1, an equalizer characteristic
and with BSYM = 0, a shelving characteristic is obtained.
Figures 17 and 18 show the bass curves with an external
circuit of 2

�

220 nF and R = 3.3 k

for each channel with

different values for BSYM. Figure 19 shows the bass
curves with an external capacitor of 47 nF for each
channel and BSYM = 0, for boost and cut.

7.5.6

OLUME

The four volume 2 blocks are located at the end of the
tone/volume control. In addition to volume control (same
settings as volume 2) also the balance and fader functions
are performed by individual attenuation offsets for the four
attenuators. The control range of these attenuators is
56 dB in steps of 1 dB and additional the steps

58.5 dB,

62 dB,

68 dB, and a mute step.

7.5.7

RSA

SELECTOR

The RSA selector provides the possibility to select an
alternative source for the rear channels. In this event rear
channels are only controlled by volume 2 function.

7.5.8

HIME ADDER

With the chime adder circuit the chime input signal can be
summed with the left front and/or right front audio, or be
turned off.

2000

May

Philips Semiconductors

Product specification

Up-le

el Car r

adio Analog Signal

Processor (CASP)

TEA6880H

10 CHARACTERISTICS
FM part: input signal V

i(MPX)(p-p)

= 1.89 V; m = 100% (

f =

�

75 kHz, f

mod

= 400 Hz); de-emphasis of 75

�

s and series resistor at input R

= 182 k

;

FM audio measurements are taken at pins 13 and 27.
Tone part: R

= 600

; R

= 10 k

, AC-coupled; C

= 2.5 nF; CLK = square-wave (5 to 0 V) at 100 kHz; stereo source = A channel input; volume 1

attenuator = 0 dB; loudness = 0 dB, off; volume 2 attenuators = 0 dB; bass linear; treble linear; input voltage = 1 V, f = 1 kHz. Tone part audio
measurements are taken at pins 33 and 37. V

= 8.3 to 8.7 V; V

= 0; T

amb

= 25

�

C; unless otherwise specified.

This IC shall not radiate noise in the audio system such that it disturbs any other circuit. This IC shall also not be susceptible to the radiation of any
other circuit.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

supply voltage

7.8

8.5

9.2

supply current

= 8.5 V

half supply voltage

= 8.5 V

3.75

4.25

4.75

ref

reference current

= 8.5 V; R

ext

= 100 k

�

FM signal path

i(MPX)(p-p)

MPX input signal (peak-to-peak value)

= 182 k

1.89

i(MPX)

overdrive margin of MPX input signal

THD = 1%

AF input current

3.66

�

i(max)

maximum AF input current

THD = 1%

7.32

�

o(rms)

AF mono output signal (RMS value)

91% modulation without pilot

890

1000

1110

out

AF mono channel balance

without pilot; V

channel separation

aligned setting of data byte 1, bit 0 to bit 3;
m = 30% modulation plus 9% pilot

L = 1; R = 0

L = 0; R = 1

THD

total harmonic distortion

i(MPX)(p-p)

= 1.89 V; f

mod

= 1 kHz without pilot

0.1

0.3

i(MPX)(p-p)

= 1.89 V; f

mod

= 5 kHz

L = 1; R = 0

0.1

0.3

L = 0; R = 1

0.1

0.3

S/N

signal-to-noise ratio

f = 20 Hz to 15 kHz

pilot signal suppression

f = 19 kHz

subcarrier suppression

f = 38 kHz

f = 57 kHz

f = 76 kHz

2000

May

Philips Semiconductors

Product specification

Up-le

el Car r

adio Analog Signal

Processor (CASP)

TEA6880H

IM2

second order intermodulation for f

spur

= 1 kHz

mod

= 10 kHz; note 1

IM3

third order intermodulation for f

spur

= 1 kHz

mod

= 13 kHz; note 1

57(RDS)

traffic radio (RDS)

f = 57 kHz; note 2

Subsidiary Communication Authorization
(SCA)

f = 67 kHz; note 3

114

Adjacent Channel Interference (ACI)

f = 114 kHz; note 4

190

f = 190 kHz; note 4

PSRR

power supply ripple rejection

f = 100 Hz; V

ripple(rms)

= 100 mV

S59

; R

S60

de-emphasis output source resistance

data byte 3, bit 5 = 1; 75

�

22.7

25.4

data byte 3, bit 5 = 0; 50

�

13.4

15.2

; I

current capacity of FM buffer

61,62

= 5.5

�

1 V

200

�

PLL VCO

osc

oscillator frequency

228

kHz

frequency range of free running oscillator

190

270

kHz

ref

reference frequency

75.4

kHz

i(fref)

reference frequency input voltage

100

500

i(48)

input impedance

100

PLL pilot detector

i(pilot)(rms)

pilot threshold voltage for automatic switching
by pilot input voltage (RMS value)

stereo on; STIN = 1

stereo off; STIN = 0

hys

(pilot)

hysteresis of pilot threshold voltage

49-10

switching voltage for external mono control
(pin 49)

0.3

0.7

AM signal path

LOPO

;

ROPO

AC output voltage at pins 13 and 27

AMON = 1 and AMST = 0; R

= 220 k

;

iAM(mono)

= 250 mV

195

245

295

AM stereo audio buffer voltage gain

subaddress 0H: AMON = 1 and AMST = 1;
input signal at pin 59 or 60; coupled with 220 nF;
V

i(59,60)

= 200 mV; f

= 1 kHz; note 5

i(59,60)

input resistance for AM stereo left and right

AMON = 1 and AMST = 1; note 6

100

120

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PARAMETER

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UNIT

2000

May

Philips Semiconductors

Product specification

Up-le

el Car r

adio Analog Signal

Processor (CASP)

TEA6880H

Noise blanker

PART

sup

interference suppression time

�

offset

gate input offset current at pins during
suppression pulse duration

during AF suppression time

ch(FMNCAP)

charge current (into 4 V)

12.5

9.5

�

dch(FMNCAP)

discharge current (from 5.5 V)

100

�

Trigger Threshold Control (TTC), dependency on MPX signal at MPXRDS input

58-10

trigger threshold variation voltage

i(MPXRDS)

= 0 V

4.5

5.5

58-10

trigger threshold voltage

i(MPXRDS)

= 10 mV; f = 120 kHz

i(MPXRDS)

= 100 mV; f = 120 kHz

100

200

7-10

trigger threshold variation with audio
frequency f = 15 kHz

i(MPXRDS)

= 670 mV

500

Trigger Threshold Control (TTC), dependency on level detector input signal

58-10

trigger threshold voltage

LEVEL(AC)

= 0 V

4.5

5.5

58-10

trigger threshold voltage as a function of
V

LEVEL(AC)

= 10 mV; f = 120 kHz

LEVEL(AC)

= 200 mV; f = 120 kHz

Trigger sensitivity measurement with pulse (on MPX signal) at MPXRDS input

pulse

trigger sensitivity

pulse

= 10

�

s; write mode; data byte 3, bits 6 and 7:

NBS1 = 1; NBS0 = 1

NBS1 = 1; NBS0 = 0

100

NBS1 = 0; NBS0 = 1

150

NBS1 = 0; NBS0 = 0

200

Trigger sensitivity measurement with pulse (on level signal) at AM/FM level input

pulse

trigger sensitivity

pulse

= 10

�

s; V

3-10

= 0.5 V; write mode;

data byte 3, bits 6 and 7:

NBS1 = 1; NBS0 = 1

250

NBS1 = 1; NBS0 = 0

275

NBS1 = 0; NBS0 = 1

300

NBS1 = 0; NBS0 = 0

320

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UNIT

2000

May

Philips Semiconductors

Product specification

Up-le

el Car r

adio Analog Signal

Processor (CASP)

TEA6880H

PART

mod

trigger threshold

140

hold time (suppression time)

400

500

600

�

AMPCAP(AC)

AF voltage at pin 43

iAM(mono)

= 50 mV (RMS); f = 1 kHz

AMGATE

attenuation of blanking gate

iAM(mono)

= 50 mV (RMS); gate open: internal

voltage; gate closed: V

DC42-10

= 4 V; note 7

sup(AMHOLD)

suppression time at pin 42

pulse

= 10

�

s; repetition rate = 50 Hz; V

pulse

= 1.7 V

(pin 53); V

3-10

= 0.5 V

400

500

600

�

(25-10)DC

detector voltage; V

ext(53-10)DC

0.7 V

53(AC)

= 0 V; V

(3-10)DC

= 3.5 V

3.3

3.8

4.3

trigger sensitivity

pulse

= 10

�

s; repetition rate = 50 Hz; V

pulse

= 1.7 V

(pin 53); V

3-10

= 4 V

offset

gate input offset current at pins during
suppression pulse duration

during AF suppression time

+50

Muting average detector (pin 54); see Fig.12

i(LEVEL)

input voltage on pin LEVEL

0.5

voltage gain pin 3 to pin 54

TMUTE

offset between pins 3 and 54

1.5

TMUTE/K

temperature dependence at pin 54

3.3

mV/K

UTING AVERAGE DETECTOR TIME CONSTANT

ch(TMUTE)

TMUTE charge current

0.2

�

dch(TMUTE)

TMUTE discharge current

0.2

�

DC output voltage

EST CONDITION

ch(test)

capacitor charge current

data byte 6, bit 7 = 1

�

dch(test)

capacitor discharge current

data byte 6, bit 7 = 1

�

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UNIT

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May

Philips Semiconductors

Product specification

Up-le

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adio Analog Signal

Processor (CASP)

TEA6880H

AM wideband average detector (pin 63); see Fig.6

TWBAM1

DC voltage at TWBAM1 w.r.t pin 10

LEVEL(AC)

= 400 mV; V

LEVEL(DC)

= 3.5 V; f

= 24 kHz;

write mode; data byte 1, bits 4 and 5:

AWS1 = 1; AWS0 = 1

4.10

AWS1 = 1; AWS0 = 0

3.60

AWS1 = 0; AWS0 = 1

3.00

AWS1 = 0; AWS0 = 0

2.35

TWBAM1

DC voltage coefficient

LEVEL(AC)

= 400 mV; V

LEVEL(DC)

= 3.5 V; f

= 24 kHz;

write mode; note 8; data byte 1, bits 4 and 5:

AWS1 = 1; AWS0 = 1

0.69

0.82

0.98

AWS1 = 1; AWS0 = 0

0.60

0.72

0.86

AWS1 = 0; AWS0 = 1

0.50

0.60

0.71

AWS1 = 0; AWS0 = 0

0.40

0.47

0.56

DC output voltage

1.5

5.5

WIDEBAND AVERAGE DETECTOR TIME CONSTANT

ch(TWBAM1)

TWBAM1 charge current

11.5

19.5

�

dch(TWBAM1)

TWBAM1 discharge current

19.5

11.5

�

Ultrasonic noise average detector (pin 64); see Fig.5

TUSN1

DC voltage at TUSN1 w.r.t. pin 10

MPXRDS(AC)

= 350 mV; V

LEVEL(DC)

= 3.5 V;

= 80 kHz; write mode; data byte 1, bits 6 and 7:

USS1 = 1; USS0 = 1

4.25

USS1 = 1; USS0 = 0

4.00

USS1 = 0; USS0 = 1

3.50

USS1 = 0; USS0 = 0

2.60

TUSN1

DC voltage coefficient

MPXRDS(AC)

= 350 mV; V

LEVEL(DC)

= 3.5 V;

= 80 kHz; write mode; note 9; data byte 1,

bits 6 and 7:

USS1 = 1; USS0 = 1

0.71

0.85

1.00

USS1 = 1; USS0 = 0

0.67

0.80

0.95

USS1 = 0; USS0 = 1

0.60

0.70

0.85

USS1 = 0; USS0 = 0

0.44

0.52

0.62

DC output voltage

1.5

5.5

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PARAMETER

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UNIT

2000

May

Philips Semiconductors

Product specification

Up-le

el Car r

adio Analog Signal

Processor (CASP)

TEA6880H

LTRASONIC NOISE AVERAGE DETECTOR TIME CONSTANT

ch(TUSN1)

TUSN1 charge current

11.5

19.5

�

dch(TUSN1)

TUSN1 discharge current

19.5

11.5

�

Peak detector for stereo noise control (SNC, pin 56)

EPENDENCY ON LEVEL VOLTAGE

; see Fig.12

LEVEL

input voltage

0.5

4.75

gain pin 3 to pin 56

TSNC

DC voltage at TSNC referred to DC level
voltage at pin 3

without MPXRDS and LEVEL (AC) input

(3-10)DC

= 0.5 V

1.75

2.00

2.25

(3-10)DC

= 3.5 V

4.50

5.00

5.50

TSNC/K

temperature dependence at pin 56

3.3

mV/K

EPENDENCY ON ULTRASONIC NOISE

; see Fig.5

TSNC

DC voltage at TSNC w.r.t. pin 10

MPXRDS(AC)

= 350 mV; V

(3-10)DC

= 3.5 V;

= 80 kHz; write mode; data byte 1, bits 6 and 7:

USS1 = 1; USS0 = 1

4.25

USS1 = 1; USS0 = 0

4.00

USS1 = 0; USS0 = 1

3.50

USS1 = 0; USS0 = 0

2.60

TSNC

DC voltage coefficient

MPXRDS(AC)

= 350 mV; V

(3-10)DC

= 3.5 V;

= 80 kHz; write mode; note 10; data byte 1,

bits 6 and 7:

USS1 = 1; USS0 = 1

0.71

0.85

1.00

USS1 = 1; USS0 = 0

0.67

0.80

0.95

USS1 = 0; USS0 = 1

0.60

0.70

0.85

USS1 = 0; USS0 = 0

0.44

0.52

0.62

DC output voltage

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UNIT

2000

May

Philips Semiconductors

Product specification

Up-le

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adio Analog Signal

Processor (CASP)

TEA6880H

EPENDENCY ON

WIDEBAND NOISE

; see Fig.6

TSNC

DC voltage at TSNC

LEVEL(AC)

= 400 mV; V

LEVEL(DC)

= 3.5 V; f

= 24 kHz;

write mode; data byte 1, bits 4 and 5:

AWS1 = 1; AWS0 = 1

4.10

AWS1 = 1; AWS0 = 0

3.60

AWS1 = 0; AWS0 = 1

3.00

AWS1 = 0; AWS0 = 0

2.35

TSNC

DC voltage coefficient

LEVEL(AC)

= 400 mV; V

LEVEL(DC)

= 3.5 V; f

= 24 kHz;

write mode; note 11; data byte 1, bits 4 and 5:

AWS1 = 1; AWS0 = 1

0.69

0.82

0.98

AWS1 = 1; AWS0 = 0

0.60

0.72

0.86

AWS1 = 0; AWS0 = 1

0.50

0.60

0.71

AWS1 = 0; AWS0 = 0

0.40

0.47

0.56

DC output voltage

1.5

5.5

ETECTOR TIME CONSTANT

ch(TSNC)

TSNC charge current

2.3

�

dch(TSNC)

TSNC discharge current

�

EST CONDITION

ch(test)

charge current for testing

data byte 6, bit 7 = 1; V

(3-10)DC

= 2 V;

(56-10)DC

= 2.8 V

1.5

dch(test)

discharge current for testing

data byte 6, bit 7 = 1; V

(3-10)DC

= 2 V;

(56-10)DC

= 4.2 V

200

�

SYMBOL

PARAMETER

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UNIT

2000

May

Philips Semiconductors

Product specification

Up-le

el Car r

adio Analog Signal

Processor (CASP)

TEA6880H

Ultrasonic noise peak detector (pin 46); see Fig.5

TUSN2

DC voltage at TUSN2 w.r.t. pin 10

MPXRDS(AC)

= 350 mV; V

(3-10)DC

= 3.5 V;

= 80 kHz; write mode; data byte 1, bits 6 and 7:

USS1 = 1; USS0 = 1

4.25

USS1 = 1; USS0 = 0

4.00

USS1 = 0; USS0 = 1

3.50

USS1 = 0; USS0 = 0

2.60

TUSN2

DC voltage coefficient

MPXRDS(AC)

= 350 mV; V

(3-10)DC

= 3.5 V;

= 80 kHz; write mode; note 12; data byte 1,

bits 6 and 7:

USS1 = 1; USS0 = 1

0.71

0.85

1.00

USS1 = 1; USS0 = 0

0.67

0.80

0.95

USS1 = 0; USS0 = 1

0.60

0.70

0.85

USS1 = 0; USS0 = 0

0.44

0.52

0.62

DC output voltage

1.5

5.5

ETECTOR TIME CONSTANT

ch(TUSN2)

TUSN2 charge current

1.6

�

dch(TUSN2)

TUSN2 discharge current

�

AM wideband peak detector (pin 45); see Fig.6

TWBAM2

DC voltage at TWBAM2 w.r.t pin 10

LEVEL(AC)

= 400 mV; V

LEVEL(DC)

= 3.5 V; f

= 24 kHz;

write mode; data byte 1, bits 4 and 5:

AWS1 = 1; AWS0 = 1

4.10

AWS1 = 1; AWS0 = 0

3.60

AWS1 = 0; AWS0 = 1

3.00

AWS1 = 0; AWS0 = 0

2.35

TWBAM2

DC voltage coefficient

LEVEL(AC)

= 400 mV; V

LEVEL(DC)

= 3.5 V; f

= 24 kHz;

write mode; note 13; data byte 1, bits 4 and 5:

AWS1 = 1; AWS0 = 1

0.69

0.82

0.98

AWS1 = 1; AWS0 = 0

0.60

0.72

0.86

AWS1 = 0; AWS0 = 1

0.50

0.60

0.71

AWS1 = 0; AWS0 = 0

0.40

0.47

0.56

DC output voltage

SYMBOL

PARAMETER

CONDITIONS

MIN.

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UNIT

2000

May

Philips Semiconductors

Product specification

Up-le

el Car r

adio Analog Signal

Processor (CASP)

TEA6880H

ETECTOR TIME CONSTANT

ch(TWBAM2

)

TWBAM2 charge current

1.6

�

dch(TWBAM2)

TWBAM2 discharge current

�

Soft mute; see Figs 7 and 4

0dB

attenuation at pins 13 and 27

TMUTE

= 3.5 V; V

TUSN1

= 3.5 V

0.5

+0.5

6dB

start of muting; AC attenuation at
pins 13 and 27

see Fig.4; write mode; data byte 0, bits 0 and 1;
MSL0 = 1; MSL1 = 1

MST1 = 0; MST0 = 0; V

TMUTE

= 0.42V

TUSN1

without AC

MST1 = 0; MST0 = 1; V

TMUTE

= 0.45V

TUSN1

without AC

MST1 = 1; MST0 = 0; V

TMUTE

= 0.47V

TUSN1

without AC

MST1 = 1; MST0 = 1; V

TMUTE

= 0.49V

TUSN1

without AC

10dB

AC attenuation for setting of mute slope at
pins 13 and 27

MST1 = 0; MST0 = 0; see Fig.7

MSL1 = 0; MSL0 = 0; V

TMUTE(DC)

= 0.35V

TUSN1

without AC

MSL1 = 0; MSL0 = 1; V

TMUTE(DC)

= 0.38V

TUSN1

without AC

MSL1 = 1; MSL0 = 0; V

TMUTE(DC)

= 0.39V

TUSN1

without AC

MSL1 = 1; MSL0 = 1; V

TMUTE(DC)

= 0.395V

TUSN1

without AC

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2000

May

Philips Semiconductors

Product specification

Up-le

el Car r

adio Analog Signal

Processor (CASP)

TEA6880H

High Cut Control (HCC)

HCC(start)

AC attenuation for start of HCC

AF = 10 kHz; V

MPXIN

= 200 mV; HSL1 = 1;

HSL0 = 0; data byte 0 SMUT = 0 and MONO = 1;
write mode; see note 16 and Fig.10; data byte 3,
bits 2 and 3:

HST1 = 1; HST0 = 1; V

(3-10)DC

= 1.30 V

1.5

4.5

HST1 = 1; HST0 = 0; V

(3-10)DC

= 1.45 V

1.5

4.5

HST1 = 0; HST0 = 1; V

(3-10)DC

= 1.90 V

1.5

4.5

HST1 = 0; HST0 = 0; V

(3-10)DC

= 2.10 V

1.5

4.5

HCC(slope)

AC attenuation for slope of HCC

AF = 10 kHz; V

MPXIN

= 200 mV;

61-10

, C

62-10

= 2.7 nF; HST1 = 1; HST0 = 1;

data byte 0 SMUT = 0 and MONO = 1; write mode;
see note 16 and Fig.11; data byte 3, bits 0 and 1:

HSL1 = 1; HSL0 = 1

5.5

7.5

9.5

HSL1 = 1; HSL0 = 0

HSL1 = 0; HSL0 = 1

HSL1 = 0; HSL0 = 0

HCC(max)

maximum HCC attenuation

AF = 10 kHz; V

TMUTE

= 2 V; data byte 0, SMUT = 0

and MONO = 1; data byte 3, bit 1 = bit 0 = 1

61-10

, C

62-10

= 2.7 nF; data byte 3 bit 4 = 1

14.5

61 -10

, C

62-10

= 680 pF; data byte 3 bit 4 = 0

14.5

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2000

May

Philips Semiconductors

Product specification

Up-le

el Car r

adio Analog Signal

Processor (CASP)

TEA6880H

Analog-to-digital converters

EVEL ANALOG

DIGITAL CONVERTER

(6-

BIT

)

LEVEL(min)

lower limit of conversion range

600

720

840

LEVEL(max)

upper limit of conversion range

3.2

3.4

3.6

LEVEL

bit resolution

LTRASONIC NOISE ANALOG

DIGITAL CONVERTER

(3-

BIT

)

TUSN(min)

lower limit of conversion range

1.9

2.1

2.4

TUSN(max)

upper limit of conversion range

3.8

4.1

4.5

TUSN

bit resolution

280

330

380

WIDEBAND NOISE ANALOG

DIGITAL CONVERTER

(3-

BIT

)

TWBAM(min)

lower limit of conversion range

1.9

2.1

2.4

TWBAM(max)

upper limit of conversion range

3.8

4.1

4.5

TWBAM

bit resolution

280

330

380

Tone/volume control

v(max)

maximum voltage gain

; R

10 M

v(signal)

signal voltage gain

amb

= 25

�

0.75

+0.75

amb

40 to +85

�

o(rms)

output voltage level

THD

0.5%

2000

THD = 1%; G

= 3 dB

2300

= 2 k

; C

= 10 nF; THD = 1%

2000

i(rms)

input sensitivity

= 500 mV; G

= 20 dB

roll-off frequency

high frequency (

1 dB)

20000

input A; C

KIL

= C

KIR

= 100 nF;

KVL

= C

KVR

= 220 nF

low frequency (

1 dB)

low frequency (

3 dB)

input C; C

KICL

= C

KICR

= 1

�

KVL

= C

KVR

= 220 nF

low frequency (

1 dB)

low frequency (

3 dB)

channel separation

= 1 V; frequency range 250 Hz to 20 kHz

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Philips Semiconductors

Product specification

Up-le

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adio Analog Signal

Processor (CASP)

TEA6880H

THD

total harmonic distortion

valid for input channel A, B or C; same for all 4
outputs refer to inputs

i(rms)

= 1 V; f = 1 kHz;

volume 1 attenuator:

6 dB; equalizer bands flat

0.05

0.1

i(rms)

= 2 V; f = 1 kHz; V

= 8.3 V;

volume 1 attenuator:

13 dB; equalizer bands flat

0.1

0.3

i(rms)

= 2 V; f = 1 kHz; V

= 8.5 V;

volume 1 attenuator: 0 dB; equalizer bands flat

0.05

0.1

i(rms)

= 1 V; f = 1 kHz; V

= 8.3 V;

volume 1 attenuator: 0 dB; equalizer bands flat

0.01

0.1

i(rms)

= 2.3 V; f = 1 kHz; V

= 9 V;

volume 1 attenuator:

13 dB; equalizer bands flat

0.13

0.3

i(rms)

= 1 V; f = 20 Hz to 20 kHz;

volume 1 attenuator:

6 dB; equalizer bands flat

0.05

0.2

i(rms)

= 2 V; f = 20 Hz to 20 kHz; V

= 8.3 V;

volume 1 attenuator:

13 dB; equalizer bands flat

0.1

0.3

i(rms)

= 2.3 V; f = 20 Hz to 20 kHz; V

= 9 V;

volume 1 attenuator:

13 dB; equalizer bands flat

0.1

0.3

i(rms)

= 0.5 V; f = 25 Hz; volume 1

attenuator: 0 dB; equalizer bass boost: +8 dB

0.1

0.2

i(rms)

= 0.5 V; f = 4 kHz; volume 1

attenuator: 0 dB; equalizer treble boost: +8 dB

0.15

0.3

chime adder total harmonic distortion

i(rms)

= 0.5 V; f = 1 kHz; V

= 8.5 V;

no input signal at input A

0.04

0.1

PSRR

power supply ripple rejection C

= 47

�

= 22

�

stereo source: A, B, C or mono;
V

= 8.5 V + 0.2 V (RMS)

f = 20 to 100 Hz

f = 1 to 20 kHz

f = 1 kHz

turn-on

turn-on time from V

applied to 66% final DC

voltage at outputs

SCAP = 22

�

F; VHS = 47

�

250

SCAP = 10

�

F; VHS = 10

�

100

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2000

May

Philips Semiconductors

Product specification

Up-le

el Car r

adio Analog Signal

Processor (CASP)

TEA6880H

noise(rms)

noise voltage CCIR-ARM weighted
(RMS value) without input signal and shorted
AF inputs

volume 1 attenuator: +20 dB

100

�

volume 1 attenuator: +20 dB; symmetrical input

100

140

�

volume 1 attenuator: 0 dB

�

volume 1 attenuator: 0 dB; symmetrical input

12.5

�

volume 1 attenuator: 0 dB;
bass and treble boost: 6 dB

�

volume 1 attenuator: 0 dB;
bass and treble boost: 6 dB; symmetrical input

�

volume 1 attenuator:

9 dB

�

minimum volume; volume 1 attenuator:

18 dB;

loudness:

20 dB; volume 2 attenuator:

22 dB

�

mute selected: data byte 8, AMUT = 1

3.5

�

volume setting:

20 dB; volume 1 attenuator:

10 dB; loudness:

10 dB; A-weighted

5.7

�

CMRR

input common mode rejection

C channel input; V

i(rms)

= 1 V; f = 20 Hz to 20 kHz on

CLIP, CRIP and CCOM

C channel input; V

i(rms)

= 1 V; f = 1 kHz on CLIP,

CRIP and CCOM

C channel input; V

i(rms)

= 1 V; f = 20 Hz to 20 kHz on

CLIP, CRIP and CCOM; volume attenuator:

15 dB

CMRR

mono

mono input common mode rejection

source = mono input

crosstalk between bus inputs and signal
outputs

clock frequency = 50 kHz;
repetition burst rate = 300 Hz; total initialization;
note 17

110

ABC

Audio Blend Control (ABC) step time

ASICAP

= 22 nF; write mode; data byte 4,

bits 6 and 7:

ASI1 = 0; ASI0 = 0

0.83

ASI1 = 0; ASI0 = 1

3.33

ASI1 = 1; ASI0 = 0

8.33

ASI1 = 1; ASI0 = 1

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000

May

Philips Semiconductors

Product specification

Up-le

el Car r

adio Analog Signal

Processor (CASP)

TEA6880H

Source selector

i(stereo)

stereo input impedance (A and B input)

100

120

i(sym)

symmetrical input impedance
(C and mono input)

i(CHIME)

CHIME input impedance (chime input)

100

120

output impedance at ROPO and LOPO

100

output load resistance at ROPO and LOPO

output load capacitance at ROPO and LOPO

2500

source selector voltage gain

0.2

+0.2

input isolation of one selected source to any
other input

f = 1 kHz

105

f = 12.5 kHz

f = 20 Hz to 20 kHz

i(rms)

maximum input voltage (RMS value)

THD

0.5%; V

= 8.5 V

2.0

2.15

THD

0.5%; V

= 7.8 V

1.8

1.9

Loudness control

input impedance at ROPI and LOPI

100

120

loudness

loudness control, maximum gain

f = 1 kHz; loudness on/off

0.2

+0.2

loudness control, minimum gain

f = 1 kHz; loudness on/off

18.5

21.5

loudness

gain, loudness on referred to loudness off

f = 1 kHz; G

loudness

20 dB

1.5

+1.5

step

step resolution gain

f = 1 kHz

step error between any adjoining step

f = 1 kHz

0.5

Bmax

maximum loudness boost; without influence of
coupling capacitors

compared to 1 kHz; loudness on

f = 30 Hz

18.5

f = 10 kHz

compared to 1 kHz; loudness off

f = 30 Hz

f = 10 kHz

ref

= 30 Hz; f

meas

= 300 Hz; bass boost only

12.5

15.5

ref

= 30 Hz; f

meas

= 300 Hz; bass and treble boost

13.5

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000

May

Philips Semiconductors

Product specification

Up-le

el Car r

adio Analog Signal

Processor (CASP)

TEA6880H

Volume 1 control

voltage gain

+20

step

step resolution gain

step error between any adjoining step

0.5

attenuator gain set error

= +20 to

36 dB

track

gain tracking error

= +20 to

36 dB

Treble control

treble

treble gain control, maximum boost

f = 10 kHz; V

i(rms)

= 200 mV

maximum attenuation

f = 10 kHz

step

step resolution gain

f = 10 kHz

step error between any adjoining step

f = 10 kHz

0.5

Bass control

bass

bass gain control, maximum boost

external T-filter; f = 60 Hz; BSYB = 1;
V

i(rms)

= 200 mV

maximum attenuation

external T-filter; f = 60 Hz; BSYC = 0

external T-filter; f = 60 Hz; BSYC = 1

14.4

15.5

step

step resolution gain

f = 60 Hz; boost; BSYB = 1

f = 60 Hz; cut; BSYC = 0

f = 60 Hz; cut; BSYC = 1

1.2

1.6

1.9

step error between any adjoining step

f = 60 Hz

0.5

centre frequency

bass

= 2

�

220 nF; R

bass

= 3.3 k

equalizer quality factor

i(rms)

= 200 mV; boost = 12 dB

0.8

0.9

1.1

bow

equalizer bowing

i(rms)

= 200 mV; bass and treble boost = 12 dB;

reference flat frequency response

2.1

3.3

Volume 2 control

voltage gain

step

step resolution

= 0 to

56 dB

step error between any adjoining step

= 0 to

56 dB

0.5

additional steps

58.5

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000

May

Philips Semiconductors

Product specification

Up-le

el Car r

adio Analog Signal

Processor (CASP)

TEA6880H

mute

mute attenuation

100

110

f = 20 Hz to 20 kHz

attenuator gain set error

= 0 to

32 dB

32 to

68 dB

track

gain tracking error

= 0 to

56 dB

output impedance

120

output load resistance

o(L)

output load capacitance

o(L)

DC load resistance at output to ground

4.7

Chime adder

v(CHIME)

chime adder voltage gain

i(rms)

= 1 V; chime input; chime adder on

i(CHIME)(rms)

maximum chime input voltage (sine wave)

main output voltage V

o(rms)

< 1.5 V; chime input;

chime adder on

2.0

factor for V

i(CHIME)

to avoid internal clipping

�

i(CHIME)(p-p)

< 5.7 V

o(p-p)

0.22

0.25

0.28

Digital part (SDA, SDAQ, SCL, SDA, SCLQ, FMHOLD, AFSAMPLE); note 18

HIGH-level input voltage

9.7

LOW-level input voltage

0.3

+0.3

+1.5

HIGH-level input current

= 0 to 9.5 V

+10

�

LOW-level input current

+10

�

LOW-level output voltage SDA

= 3 mA

0.4

Digital part (SDAQ and SCLQ); note 18

o(sink)

output sink current

600

�

pull-up resistance

load capacitance

Digital part (ADR); note 18

HIGH-level input voltage

LOW-level input voltage

0.3

+1.5

HIGH-level input current

150

�

LOW-level input current

�

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

Notes to the characteristics

1. Intermodulation suppression; Beat Frequency Components (BFC):

;

measured with 91% mono signal; f

mod

= 10 kHz or 13 kHz; 9% pilot signal.

2. RDS suppression:

measured with 91% stereo signal; f

mod

= 1 kHz; 9% pilot signal; 5% RDS subcarrier

= 57 kHz; f

mod

= 23 Hz; AM m = 0.6).

3. Subsidiary Communication Authorization (SCA):

;

measured with 81% mono signal; f

mod

= 1 kHz; 9% pilot signal; 10% SCA subcarrier (f

= 67 kHz, unmodulated).

4. Adjacent Channel Interference (ACI):

;

measured with 90% mono signal; f

mod

= 1 kHz; 9% pilot signal; 1% spurious signal

= 110 kHz or 186 kHz, unmodulated).

5. AM stereo audio buffer gain:

;

6. Input resistance for AM stereo left and right:

7. Attenuation of blanking gate:

8. TWBAM1 DC voltage coefficient:

9. TUSN1 DC voltage coefficient:

10. TSNC DC voltage coefficient:

IM2

o(signal)

at 1 kHz

(

)

o(spurious)

at 1 kHz

(

)

------------------------------------------------------

10 kHz

�

(

)

19 kHz

�

IM3

o(signal)

at 1 kHz

(

)

o(spurious)

at 1 kHz

(

)

------------------------------------------------------

13 kHz

�

(

)

38 kHz

�

57(RDS)

o(signal)

at 1 kHz

(

)

o(spurious)

at 1 kHz

23 Hz

�

(

)

---------------------------------------------------------------------------

o(signal)

at 1 kHz

(

)

o(spurious)

at 9 kHz

(

)

------------------------------------------------------

38 kHz

�

(

)

67 kHz

�

114

o(signal)

at 1 kHz

(

)

o(spurious)

at 4 kHz

(

)

------------------------------------------------------

110 kHz

38 kHz

�

(

)

�

190

o(signal)

at 1 kHz

(

)

o(spurious)

at 4 kHz

(

)

------------------------------------------------------

186 kHz

38 kHz

�

(

)

�

---------

log

---------

log

i(59,60)

59,60

i(59,60)

--------------------

AMGATE

AMPCAP

at gate open

AMPCAP

at gate close

-----------------------------------------------------------

log

TWBAM1

with AC voltage at pin 3

TWBAM1

without AC voltage

----------------------------------------------------------------------------------------

TUSN1

with AC voltage at pin 55

TUSN1

without AC voltage

---------------------------------------------------------------------------------------

TSNC

with AC voltage at pin 55

TSNC

without AC voltage

-------------------------------------------------------------------------------------

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

11. TSNC DC voltage coefficient:

12. TUSN2 DC voltage coefficient:

13. TWBAM2 DC voltage coefficient:

14. Start of channel separation:

15. Slope of channel separation:

16. AC attenuation for start and slope of HCC:

17. Crosstalk between bus inputs and signal outputs:

18. The characteristics are in accordance with the I

C-bus specification. This specification,

"The I

C-bus and how to use

it", can be ordered using the code 9398 393 40011.

TSNC

with AC voltage at pin 3

TSNC

without AC voltage

---------------------------------------------------------------------------------

TUSN2

with AC voltage at pin 55

TUSN2

without AC voltage

---------------------------------------------------------------------------------------

TWBAM2

with AC voltage at pin 3

TWBAM2

without AC voltage

----------------------------------------------------------------------------------------

cs(start)

20log

LOPO(AC)

ROPO(AC)

--------------------------

cs(slope)

20log

LOPO(AC)

ROPO(AC)

--------------------------

HCC(10 kHz)

20log

13,27

13 27

without High Cut active

--------------------------------------------------------------------------------

20log

bus(p-p)

o(rms)

---------------------

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

11.1

Read mode: 1st data byte

Table 4

Format of 1st data byte

Table 5

Description of 1st data byte bits

Table 6

Level setting ADC

STIN

RDSU

LVL5

LVL4

LVL3

LVL2

LVL1

LVL0

BIT

SYMBOL

DESCRIPTION

STIN

Stereo indicator. This bit indicates if a pilot signal has been detected. If STIN = 0, then
no pilot signal detected. If STIN = 1, then a pilot signal has been detected.

RDSU

Measure mode. This bit selects the measure mode for the RDS flags. If RDSU = 0,
then continuous mode selected. If RDSU = 1, then RDS update mode selected.

5 to 0

LVL[5:0]

ADC voltage level. These 6 bits determine the ADC voltage level, see Table 6.

LEVEL

(V)

LVL5

LVL4

LVL3

LVL2

LVL1

LVL0

3.600

3.553

3.506

3.460

3.413

3.366

3.319

3.272

3.225

3.179

3.132

3.085

3.038

2.991

2.944

2.898

2.851

2.804

2.757

2.710

2.663

2.617

2.570

2.523

2.476

2.429

2.383

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

11.3

Subaddress byte for write

Table 11 Format for subaddress byte

Table 12 Description of subaddress byte

Table 13 Selection of data byte

Note

1. Not tested; function not guaranteed.

AIOF

BOUT

SAD3

SAD2

SAD1

SAD0

BIT

SYMBOL

DESCRIPTION

AIOF

Auto-increment control. This bit controls the auto-increment function. If AIOF = 0, then
the auto-increment is on. If AIOF = 1, then auto-increment is off.

BOUT

C-bus output control. This bit enables/disables the I

C-bus output SDAQ and SCLQ

to the TEA6840H. If BOUT = 0, then the I

C-bus output is disabled. If BOUT = 1, then

the I

C-bus output is enabled.

These 2 bits are not used; both must be set to logic 0.

SAD3

Data byte select. These 4 bits select which data byte is to be addressed; see Table 13.

SAD2

SAD1

SAD0

ADDRESSED DATA BYTE

MNEMONIC

SAD3

SAD2

SAD1

SAD0

Alignment 0

ALGN0

Alignment 1

ALGN1

Alignment 2

ALGN2

Alignment 3

ALGN3

ASI time source selector

SSEL

Bass control

BASS

Treble control

TRBL

Loudness control

LOUD

Volume 1

VOLU1

Volume 2, left front

VOL2_LF

Volume 2, right front

VOL2_RF

Volume 2, left rear

VOL2_LR

Volume 2, right rear

VOL2_RR

Not used

(1)

Not used

(1)

Not used

(1)

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

11.4

Write mode: subaddress 0H

Table 14 Format of data byte Alignment 0 (ALGN0)

Table 15 Description of ALGN0 bits

Table 16 Setting of AM/FM mode

Note

1. MPX input (MPXIN) and AM input (AMHIN) muted, stereo decoder in mono mode and de-emphasis terminals

(DEEML and DEEMR) are audio signal inputs.

Table 17 Setting of start of muting (

MUTE

= 6 dB)

AMON

AMST

SEAR

SMUT

MMUT

MONO

MST1

MST0

BIT

SYMBOL

DESCRIPTION

AMON

AM/FM mode selection. These 2 bits select the AM/FM mode and source; see
Table 16.

AMST

SEAR

Search mode selection. If SEAR = 0, then mute and SNC detectors normal. If
SEAR = 1, then mute and SNC detectors fast.

SMUT

Soft mute enable. If SMUT = 0, then soft mute off. If SMUT = 1, then soft mute
enabled.

MMUT

Muting of MPX output. If MMUT = 0, then MPX output not muted. If MMUT = 1, then
MPX output muted.

MONO

Stereo decoder mode selection. If MONO = 0, then Stereo mode selected. If
MONO = 1, then Mono mode selected.

MST1

Start of muting. These 2 bits determine the value of V

TMUTE

; see Table 17 and Fig.4.

MST0

SELECTED MODE

AMON

AMST

AM stereo mode, note 1

AM mode, active input AMHIN

Not allowed

FM mode, active input MPXIN

TMUTE

(V)

MST1

MST0

2.45

2.30

2.15

2.00

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

Table 22 Setting of channel separation alignment

Note

1. Not tested; function not guaranteed.

11.6

Write mode: subaddress 2H

Table 23 Format of data byte Alignment 2 (ALGN2)

Table 24 Description of ALGN2 bits

CHANNEL SEPARATION ALIGNMENT

CHS3

CHS2

CHS1

CHS0

Not used

(1)

Not used

(1)

Not used

(1)

Not used

(1)

Not used

(1)

Not used

(1)

Setting 9, minimum gain of side signal

Setting 8

Setting 7

Setting 6

Setting 5

Setting 4

Setting 3

Setting 2

Setting 1

Setting 0, maximum gain of side signal

MSL1

MSL0

SSL1

SSL0

SST3

SST2

SST1

SST0

BIT

SYMBOL

DESCRIPTION

MSL1

Soft mute slope alignment. These 2 bits determine the value of V

TMUTE(DC)

; see

Table 25 and Fig.7.

MSL0

SSL1

Stereo noise control slope alignment. These 2 bits determine the value of

; see

Table 26 and Fig.8.

SSL0

SST3

Stereo noise control start alignment. These 4 bits determine the stereo noise control
start alignment; see Table 27 and Fig.9.

SST2

SST1

SST0

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

11.7

Write mode: subaddress 3H

Table 28 Format of data byte Alignment 3 (ALGN3)

Table 29 Description of ALGN3 bits

Table 30 Setting of noise blanker sensitivity

Table 31 Setting of alignment for start of high cut control (

10kHz

= 3 dB)

NBS1

NBS0

DE75

HCCS

HST1

HST0

HSL1

HSL0

BIT

SYMBOL

DESCRIPTION

NBS1

Noise blanker sensitivity. These 2 bits determine the noise blanker sensitivity levels;
see Table 30.

NBS0

DE75

De-emphasis. If DE75 = 1, then de-emphasis is 75

�

s. If DE75 = 1, then de-emphasis

is 50

�

HCCS

HCC control switch. With static roll-off: HCCS = 1, C

= C

= 2.7 nF. Without static

roll-off: HCCS = 0, C

= C

= 680 pF.

HST1

HCC start alignment. These 2 bits determine the alignment for the start of high cut
control; see Table 31 and Fig.10.

HST0

HSL1

HCC slope alignment. These 2 bits determine the alignment for the slope of high cut
control; see Table 32 and Fig.11.

HSL0

pulse(p)(MPX)

(mV) V

pulse(p)(level)

(mV)

NBS1

NBS0

110

120

150

120

200

(3-10)DC

(V)

HST1

HST0

1.30

1.45

1.90

2.10

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

11.8

Write mode: subaddress 4H

Table 33 Format of data byte Source Selector (SSEL)

Table 34 Description of SSEL bits

Table 35 ASI/ABC speed selection (C

= 15 nF)

Table 36 Selected source for rear outputs

Note

1. Not tested; function not guaranteed.

ASI1

ASI0

RSA2

RSA1

RSA0

MSS2

MSS1

MSS0

BIT

SYMBOL

DESCRIPTION

ASI1

ASI/ABC speed selection. These 2 bits select the ASI/ABC speed (time per step), see
Table 35.

ASI0

RSA2

Rear seat audio selector. These 3 bits select the source for the rear outputs, see
Table 36.

RSA1

RSA0

MSS2

Main source selector. These 3 bits select the source for the main control part, see
Table 37.

MSS1

MSS0

ASI/ABC SPEED (ms)

ASI1

ASI0

8.33

3.33

0.83

SELECTED SOURCE

RSA2

RSA1

RSA0

Internal, main channel

(1)

Internal, main channel

(1)

Internal, main channel

(1)

Internal, main channel

AM/FM (internal)

Input A (stereo)

Input B (stereo)

Input C (stereo, symmetrical)

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

Table 37 Selected source for main control part

Note

1. Not tested; function not guaranteed.

11.9

Write mode: subaddress 5H

Table 38 Format of data byte Bass control (BASS)

Table 39 Description of BASS bits

SELECTED SOURCE

MSS2

MSS1

MSS0

Chime input

(1)

Chime input

(1)

Chime input

Input D (mono, symmetrical)

AM/FM (internal)

Input A (stereo)

Input B (stereo)

Input C (stereo, symmetrical)

BSYC

BSYB

BAS4

BAS3

BAS2

BAS1

BAS0

BIT

SYMBOL

DESCRIPTION

BSYC

Bass filter mode for cut. If BSYC = 0, then shelving characteristic selected. If
BSYC = 1, then band-pass filter characteristic selected.

This bit is not used and must be set to logic 0.

BSYB

Bass filter mode for boost. If BSYB = 0, then shelving characteristic selected. If
BSYB = 1, then band-pass filter characteristic selected.

BAS4

Bass control. These 5 bits determine the bass control level, see Table 40.

BAS3

BAS2

BAS1

BAS0

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

Table 40 Setting of bass control level

Note

1. Not tested; function not guaranteed.

BASS CONTROL (dB)

BAS4

BAS3

BAS2

BAS1

BAS0

+18

(1)

+18

(1)

+18

(1)

+18

(1)

+18

(1)

+18

+16

+14

+12

+10

2 (

1.8)

4 (

3.6)

6 (

5.4)

8 (

7.1)

10 (

8.7)

12 (

10.3)

14 (

11.7)

16 (

13.1)

18 (

14.4)

18 (

14.4)

(1)

18 (

14.4)

(1)

18 (

14.4)

(1)

18 (

14.4)

(1)

18 (

14.4)

(1)

18 (

14.4)

(1)

18 (

14.4)

(1)

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

11.11 Write mode: subaddress 7H

Table 44 Format of data byte Loudness control (LOUD)

Table 45 Description of LOUD bits

Table 46 Attenuation of loudness block

LOFF

LSN4

LSN3

LSN2

LSN1

LSN0

BIT

SYMBOL

DESCRIPTION

LOFF

Loudness switch control. If LOFF = 0, then the loudness switch is on. If LOFF = 1,
then loudness switch is off.

These 2 bits are not used, each must be set to logic 0.

LSN4

Loudness control. These 5 bits determine the attenuation of the loudness block, see
Table 46.

LSN3

LSN2

LSN1

LSN0

ATTENUATION (dB)

LSN4

LSN3

LSN2

LSN1

LSN0

(1)

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

11.12 Write mode: subaddress 8H

Table 47 Format of data byte Volume 1 control (VOLU1)

Table 48 Description of VOLU1 bits

Table 49 Attenuation of volume 1 block

AMUT

VOL5

VOL4

VOL3

VOL2

VOL1

VOL0

BIT

SYMBOL

DESCRIPTION

AMUT

Audio mute switch. If AMUT = 0, then there is no audio mute. If AMUT = 1, then audio
mute on.

This bit is not used and must be set to logic 0.

5 to 0

VOL[5:0]

Volume 1 control. These 6 bits determine the attenuation of volume 1 block; see
Table 49.

ATTENUATION (dB)

VOL5

VOL4

VOL3

VOL2

VOL1

VOL0

+20

(1)

+20

(1)

+20

(1)

+20

+19

+18

+17

+16

+15

+14

+13

+12

+11

+10

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

Note

1. Not tested; function not guaranteed.

(1)

ATTENUATION (dB)

VOL5

VOL4

VOL3

VOL2

VOL1

VOL0

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

11.13 Write mode: subaddress 9H

Table 50 Format of data byte Volume 2, left front (VOL2_LF)

Table 51 Description of VOL2_LF bits

Table 52 Attenuation of volume 2 left front

CHML

VLF5

VLF4

VLF3

VLF2

VLF1

VLF0

BIT

SYMBOL

DESCRIPTION

CHML

Chime adder left front select. If CHML = 1, then chime on. If CHML = 0, then chime
off.

This bit is not used and must be set to logic 0.

5 to 0

VLF[5:0]

Left front volume 2, balance and fader control. These 6 bits determine the
attenuation of volume 2 left front; see Table 52.

ATTENUATION (dB)

VLF5

VLF4

VLF3

VLF2

VLF1

VLF0

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

Note

1. Not tested; function not guaranteed.

58.5

Mute left front

(1)

Mute left front

(1)

Mute left front

(1)

ATTENUATION (dB)

VLF5

VLF4

VLF3

VLF2

VLF1

VLF0

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

11.14 Write mode: subaddress AH

Table 53 Format of data byte Volume 2, right front (VOL2_RF)

Table 54 Description of VOL2_RF bits

Table 55 Attenuation of volume 2 right front

CHMR

VRF5

VRF4

VRF3

VRF2

VRF1

VRF0

BIT

SYMBOL

DESCRIPTION

CHMR

Chime adder right front select. If CHMR = 1, then chime on. If CHMR = 0, then chime
off.

This bit is not used and must be set to logic 0.

5 to 0

VRF[5:0]

Right front volume 2, balance and fader control. These 6 bits determine the
attenuation of volume 2 right front; see Table 55.

ATTENUATION (dB)

VRF5

VRF4

VRF3

VRF2

VRF1

VRF0

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

Note

1. Not tested; function not guaranteed.

58.5

Mute right front

(1)

Mute right front

(1)

Mute right front

(1)

ATTENUATION (dB)

VRF5

VRF4

VRF3

VRF2

VRF1

VRF0

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

11.15 Write mode: subaddress BH

Table 56 Format of data byte Volume 2, left rear (VOL2_LR)

Table 57 Description of VOL2_LR bits

Table 58 Attenuation of volume 2 left rear

VLR5

VLR4

VLR3

VLR2

VLR1

VLR0

BIT

SYMBOL

DESCRIPTION

These 2 bits are not used, each must be set to logic 0.

5 to 0

VLR[5:0]

Left rear volume 2, balance and fader control. These 6 bits determine the attenuation
of volume 2 left rear; see Table 58.

ATTENUATION (dB)

VLR5

VLR4

VLR3

VLR2

VLR1

VLR0

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

Note

1. Not tested; function not guaranteed.

58.5

Mute left rear

(1)

Mute left rear

(1)

Mute left rear

(1)

ATTENUATION (dB)

VLR5

VLR4

VLR3

VLR2

VLR1

VLR0

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

11.16 Write mode: subaddress CH

Table 59 Format of data byte Volume 2, right rear (VOL2_RR)

Table 60 Description of VOL2_RR bits

Table 61 Attenuation of volume 2 right rear

VRR5

VRR4

VRR3

VRR2

VRR1

VRR0

BIT

SYMBOL

DESCRIPTION

These 2 bits are not used, each must be set to logic 0.

5 to 0

VRR[5:0]

Right rear volume 2, balance and fader control. These 6 bits determine the
attenuation of volume 2 right rear, see Table 61.

ATTENUATION (dB)

VRR5

VRR4

VRR3

VRR2

VRR1

VRR0

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

Note

1. Not tested; function not guaranteed.

58.5

Mute right rear

(1)

Mute right rear

(1)

Mute right rear

(1)

ATTENUATION (dB)

VRR5

VRR4

VRR3

VRR2

VRR1

VRR0

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

14 SOLDERING

14.1

Introduction to soldering surface mount
packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

14.2

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250

�

C. The top-surface temperature of the

packages should preferable be kept below 230

�

14.3

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

�

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

�

For packages with leads on two sides and a pitch (e):

� larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

� smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

�

For packages with leads on four sides, the footprint must
be placed at a 45

�

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

�

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

14.4

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

�

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

�

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

14.5

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45

�

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE

SOLDERING METHOD

WAVE

REFLOW

(1)

BGA, SQFP

not suitable

suitable

HLQFP, HSQFP, HSOP, HTSSOP, SMS

not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO

not recommended

(5)

suitable

2000 May 08

Philips Semiconductors

Product specification

Up-level Car radio Analog Signal
Processor (CASP)

TEA6880H

15 DATA SHEET STATUS

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

DATA SHEET STATUS

PRODUCT

STATUS

DEFINITIONS

(1)

Objective specification

Development

This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.

Preliminary specification

Qualification

This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.

Product specification

Production

This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

16 DEFINITIONS

Short-form specification

The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition

Limiting values given are in

accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information

Applications that are

described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.

17 DISCLAIMERS

Life support applications

These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes

Philips Semiconductors

reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

18 PURCHASE OF PHILIPS I

C COMPONENTS

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

� Philips Electronics N.V.

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

2000

Philips Semiconductors � a worldwide company

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Printed in The Netherlands

753503/01/pp

Date of release:

2000 May 08

Document order number:

9397 750 04633

Электронный компонент: TEA6880H