1996 Oct 10
2
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizer
TSA5520; TSA5521
FEATURES
Complete 1.3 GHz single chip system
Four PNP band switch buffers (40 mA)
33 V output tuning voltage
In-lock detector
15-bit programmable divider
Programmable reference divider ratio
(512, 640 or 1024)
Programmable charge-pump current (60 or 280
A)
Varicap drive disable
Universal bus protocol I
2
C-bus or 3-wire bus (the
TSA5520/TSA5521 I
2
C-bus mode only includes the
write mode; if both read and write modes are required
the TSA5526/TSA5527 devices should be selected):
bus protocol for 18 or 19 bits transmission
(3-wire bus)
extra protocol for 27 bits for test and features
(3-wire bus)
address plus 4 data bytes transmission (I
2
C-bus)
three independent I
2
C-bus addresses
Low power and low radiation.
APPLICATIONS
TV tuners and front ends
VCR tuners.
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TSA5520M
SSOP16
plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
TSA5520T
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
TSA5521M
SSOP16
plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
TSA5521T
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1996 Oct 10
3
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizer
TSA5520; TSA5521
QUICK REFERENCE DATA
Notes
1. One band switch buffer ON with 40 mA.
2. One buffer ON, I
o
= 40 mA; two buffers ON, maximum sum of I
o
= 50 mA.
3. The power dissipation is calculated as follows:
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CC1
supply voltage (+5 V)
4.5
-
5.5
V
V
CC2
band switch supply voltage (12 V)
V
CC1
12
13.5
V
I
CC1
supply current
-
20
25
mA
I
CC2
band switch supply current
note 1
-
50
55
mA
f
RF
RF input frequency
64
-
1300
MHz
V
i(RF)
RF input voltage
80 to 150 MHz
-
25
-
+3
dBm
150 MHz to 1 GHz
-
28
-
+3
dBm
1 to 1.3 GHz
-
15
-
+3
dBm
f
xtal
crystal oscillator input frequency
3.2
4.0
4.48
MHz
I
o(PNP)
PNP band switch buffers output current note 2
4
-
50
mA
P
tot
total power dissipation
note 3
-
250
400
mW
T
stg
IC storage temperature
-
40
-
+150
C
T
amb
operating ambient temperature
-
20
-
+85
C
P
D
V
CC1
I
CC1
V
CC2
I
CC2
I
o
(
)
I
o
V
CE satPNP
(
)
V33 2
/
(
)
2
27 k
/
+
+
+
=
1996 Oct 10
4
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizer
TSA5520; TSA5521
Table 1
Differences between TSA5520 and TSA5521
Notes
1. The selection of the reference divider is given by an automatic identification of the data word length.
2. The reference divider is set to 640 at power-on reset.
TYPE NUMBER
DATA WORD
REFERENCE DIVIDER
FREQUENCY STEP (kHz)
TSA5520
18-bit
512
(1)
62.5
TSA5520
19-bit
1024
(1)
31.25
TSA5521
18-bit or 19-bit
640
(2)
50
The device has three independent I
2
C-bus addresses
which can be selected by applying a specific voltage on the
CE input (see Table 5). The general address C2 is always
valid. When the I
2
C-bus format is fully used, TSA5520 and
TSA5521 are equal.
3-wire bus format (SW = V
CC1
or open-circuit)
Data is transmitted to the device during a HIGH level on
the CE input (enable line pin 15). The device is compatible
with 18-bit and 19-bit data formats. The first four bits are
used to program the PNP band switch buffers and the
remaining bits are used to control the programmable
divider. A 27-bit data format may also be used to set the
charge-pump current, the reference divider ratio and for
test purposes. The difference between TSA5520 and
TSA5521 are given in Table 1.
When the 27-bit format is used, the TSA5520 and
TSA5521 are equal and the reference divider is controlled
by the RSA and RSB bits (see Table 7). More details are
given in Chapter "Functional description" Section "3-wire
bus mode (SW = open-circuit or V
CC1
); see
Figs 3, 4 and 5".
GENERAL DESCRIPTION
The device is a single-chip PLL frequency synthesizer
designed for TV and VCR tuning systems. The circuit
consists of a divide-by-eight prescaler with its own
preamplifier, a 15-bit programmable divider, a crystal
oscillator and its programmable reference divider and a
phase/frequency detector combined with a charge-pump
which drives the tuning amplifier and the 33 V output.
Four high-current PNP band switch buffers are provided
for band switching. Two PNP buffers can be switched on
simultaneously. The sum of the collector currents is limited
to 50 mA.
Depending on the reference divider ratio (512, 640 or
1024), the phase comparator operates at 3.90625 kHz,
6.25 kHz or 7.8125 kHz using a 4 MHz crystal.
The lock detector output is LOW when the PLL loop is
locked. In the test mode, this output is used as a test
output for f
ref
and 1/2f
div
(see Table 6). The device can be
controlled in accordance with the I
2
C-bus format or the
3-wire bus format depending on the voltage applied to the
SW input (see Table 2).
I
2
C-bus format (SW = LOW)
Five serial bytes (including address byte) are required to
address the device, select the VCO frequency, program
the four PNP band switch buffers, set the charge-pump
current and the reference divider ratio.
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