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Электронный компонент: UAA1570HL

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DATA SHEET
Product specification
File under Integrated Circuits, IC18
1999 May 10
INTEGRATED CIRCUITS
UAA1570HL
Global Positioning System (GPS)
front-end receiver circuit
1999 May 10
2
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end
receiver circuit
UAA1570HL
CONTENTS
1
FEATURES
2
GENERAL DESCRIPTION
3
ORDERING INFORMATION
4
QUICK REFERENCE DATA
5
BLOCK DIAGRAM
6
PINNING INFORMATION
7
FUNCTIONAL DESCRIPTION
7.1
Low noise amplifiers LNA1 and LNA2
7.1.1
LNA1IN
7.1.2
LNA1OUT
7.1.3
LNA2IN
7.1.4
LNA2OUT
7.1.5
MX1IN
7.1.6
General remarks and results
7.2
Correlation of the UAA1570HL data sheet,
application and test boards
7.3
RF mixer with preamplifier
7.4
VCO
7.5
First IF filter
7.6
Second IF mixer
7.7
Second IF filter
7.8
Time and amplitude quantization
7.8.1
Clock inputs
7.8.2
CMOS to ECL sample clock squaring circuit
7.8.3
Time quantization (sampler)
7.8.4
TTL output stage
7.8.5
1-bit delays
7.9
Programmable synthesizer
7.9.1
VCO prescaler
7.9.2
Main synthesizer dividers (N-path)
7.9.3
Second local oscillator dividers (L-path)
7.9.4
Reference dividers (R-path)
7.10
Serial interface
7.10.1
p0 and p1
7.10.2
r5
7.10.3
r0, r1, r2, r3 and r4
7.10.4
n7
7.10.5
n0, n1, n2, n3, n4, n5 and n6
7.10.6
l0, l1, l2 and l3
7.11
The serial interface word
7.12
The default frequency plan
7.13
Phase detector, charge pump and loop filter
8
OPERATING MODE SELECTION TABLES
8.1
Manual selection operating modes
9
LIMITING VALUES
10
THERMAL CHARACTERISTICS
11
DC CHARACTERISTICS
12
AC CHARACTERISTICS
13
CHARACTERIZATION TEST CIRCUIT
14
DEFAULT APPLICATION AND
DEMONSTRATION BOARD
15
INTERNAL CIRCUITRY
16
PACKAGE OUTLINE
17
SOLDERING
17.1
Introduction to soldering surface mount
packages
17.2
Reflow soldering
17.3
Wave soldering
17.4
Manual soldering
17.5
Suitability of surface mount IC packages for
wave and reflow soldering methods
18
DEFINITIONS
19
LIFE SUPPORT APPLICATIONS
1999 May 10
3
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end
receiver circuit
UAA1570HL
1
FEATURES
Complete single-chip programmable
double-superheterodyne C/A-code GPS receiver
Programmable high IF frequencies supporting
wideband/P-code GPS and Global Navigation Satellite
System (GLONASS) applications
Supports frequency plans with a 2nd IF of
4
f
0
(1.023 MHz) = 4.092 MHz
48-pin LQFP package
-
40 to +85
C operating temperature range
2.7 V minimum supply voltage
Low DC power consumption [57 mA typical with both
Low-Noise Amplifiers (LNAs) active]
Power-down mode (<900
A)
Typical receiver noise figure at 1.57542 GHz: 4.5 dB
Typical phase noise
-
72 dBc/Hz at 10 kHz offset
Simple microstrip LNA1/2 and first mixer matching
Single pin VCO with external varactor and resonator
Digital Phase Locked Loop (DPLL) synthesizer with
programmable VCO, 2nd Local Oscillator (LO) and
reference dividers
3-bit synthesizer and power-down control input
Reference and independent sample clock input with
internal squaring
1-bit amplitude quantized and time sampled TTL/CMOS
compatible output driver
High active gain supporting SAW filter applications
Configurable for external first LNA applications.
2
GENERAL DESCRIPTION
The UAA1570HL is a complete single-chip
double-superheterodyne receiver front-end intended for
GPS and GLONASS navigation systems. The IC includes
a programmable on-chip DPLL synthesizer, VCO with
external varactor and resonator, a 1-bit amplitude
quantizer and a time sampled TTL/CMOS compatible
SIGN output bit driver. It can be used with either an active
or passive antenna system by disabling or enabling the
on-chip LNAs and is ideally suited for low power GPS
receiver applications because of its 3 V supply and the
power management features through control pins.
Programmable prescaler controls provide the flexibility of
using different frequency schemes.
The UAA1570HL is optimized to provide SIGN bit data to
the companion Philips part, the SAA1575HL baseband
digital signal processor. The SAA1575HL can provide the
sample clock input to the UAA1570HL by dividing a
TTL/CMOS level reference clock signal down to a
programmable sampling clock output frequency. Both ICs
can also be used independently.
The UAA1570HL is supplied in a low profile, 48-pin LQFP
package for excellent Radio Frequency (RF) performance
and small size.
3
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
UAA1570HL
LQFP48
plastic low profile quad flat package; 48 leads; body 7
7
1.4 mm
SOT313-2
1999 May 10
4
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end
receiver circuit
UAA1570HL
4
QUICK REFERENCE DATA
V
CCA
= V
DDD
= 3 V; T
amb
= 25
2
C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CCA
analog supply voltage
2.7
3
5
V
V
DDD
digital supply voltage
2.7
3
5
V
I
VCCA
+ I
VDDD
analog supply current plus digital
supply current
V
CCA
and V
DDD
= 2.7 V
-
55.1
62.3
mA
V
CCA
and V
DDD
= 5 V
-
61
69.3
mA
G
RF
available RF power gain
LNAs at 1.57542 GHz
-
31
-
dB
G
IF1
available 1st mixer power gain
MX1 at 1.57542 GHz
-
17.7
-
dB
G
IF2
available 2nd mixer power gain
MX2 at 41.8 MHz
-
21.4
-
dB
G
v(lim)
limiter voltage gain to 1st latch
limiter at 3.48 MHz
-
78
-
dBV
V
lim(M)
differential limiter sensitivity
(peak value)
f = 3.48 MHz
-
100
-
V
F
RX
receiver noise figure
f = 1.57542 GHz
-
4.5
5.2
dB
T
amb
operating ambient temperature
V
CCA
and V
DDD
= 3.3 to 5 V
-
40
+25
+85
C
V
CCA
and V
DDD
= 3 to 5 V
-
30
+25
+85
C
V
CCA
and V
DDD
= 2.7 to 5 V
0
+25
+85
C
1999 May 10
5
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end
receiver circuit
UAA1570HL
5
BLOCK DIAGRAM
Fig.1 Block diagram.
Shaded blocks are NOT active during synthesizer state.
(1) The default values are: L = 10, N = 71 and R = 4.
handbook, full pagewidth
MHB269
UAA1570HL
DIVIDE-BY-1 or 2
DIVIDE-BY-R
(1)
(4 to 31)
DIVIDE-BY-1 or 2
DIVIDE-BY-2
DIVIDE-BY-N
(1)
(64 to 127)
DIVIDE-BY-2
DIVIDE-BY-2
DIVIDE-BY-L
(1)
(4 to 15)
DIVIDE-BY-3
VCO
9
10
11
12
13
14
15
16
17
18
48
47
46
45
44
43
19
20
21
22
24
23
LNA2
4
3
2
1
5
6
DATA REGISTER
FOR
PROGRAMMING
28
36
35
33
31
32
QUANTIZER
29
30
34
27
26
25
SQUARING
CIRCUIT
SQUARING
CIRCUIT
8
7
to data register
MIXER 2
MIXER 1
40
42
41
39
38
LNA1
PHASE
FREQUENCY
DETECTOR
37
to data
register
VCCA(LNA2)
LNA2GND1
LNA2IN
BIASGND2
LNA2GND2
LNA2OUT
REFIN
VCCA(VCO)
VCOGND
P12GND
CLOCK
TANK
VCCA(PLL)
DGND
SIGN
VDDD
VCCA(LIM)
BFCP
LIMINP
LIMINN
BFCN
LIMGND
IF2N
DATA
MX1IN
MX1GND
V
CCA(MX1P)
IF1P
IF1N
V
CCA(MX2)
MX2GND
IF2INP
STROBE
IF2P
MXPGND
IF2INN
LNA1GND2
BIASGND1
LNA1IN
LNA1GND1
V
CCA(LNA1)
P42GND
COMP
P39GND
PLLGND
SCLK
LNA1OUT
P41GND