2000 Apr 17
2
Philips Semiconductors
Preliminary specification
2 GHz image rejecting front-end
UAA2077TS
FEATURES
Low noise, wide dynamic range amplifier
Very low noise figure
Dual balanced mixers for over 30 dB on-chip image
rejection
Quadrature 200 MHz IF recombiner
On-chip quadrature network
Independent SX, RX, power-down control modes and
fast power-up switching
Very small outline packaging
No image filter required, resulting in a very small
application.
APPLICATIONS
GSM dual band solution with UAA3522HL
High frequency front-end for DCS1800/PCS1900
portable hand-held equipment
Compact mobile digital communication equipment
Time Division Multiple Access (TDMA) receivers e.g.
RF Local Area Networks (RF LANs).
GENERAL DESCRIPTION
The UAA2077TS contains a 2 GHz front-end receiver
intended to be used in mobile telephones. Designed in an
advanced BiCMOS process it combines high performance
with a low power consumption and high integration, thus
reducing external component costs and overall front-end
size.
The main advantage of the UAA2077TS is its ability to
provide an image rejection over 30 dB. Therefore, an
additional image filter between the Low Noise Amplifier
(LNA) and the mixer is not required.
Image rejection is achieved internally by two RF mixers in
quadrature operation and two all-pass filters in the I and Q
IF channels that shift the phase of signals by 45
and 135
respectively. These two phase shifted IF signals are
combined and buffered to the front-end IF output signal.
An input signal with a frequency above the Local Oscillator
(LO) frequency results in an IF signal, while an input signal
with a frequency below the LO frequency is rejected.
The receive section consists of an LNA that drives a
quadrature mixer pair. The IF amplifier consists of an
on-chip 45
and 135
phase shifting network and an image
reject IF recombiner. The IF driver has differential
open-collector outputs.
The LO part consists of an internal all-pass phase shifting
filter to provide the quadrature LO signals for the mixers of
the receive section. The all-pass filter output signals are
buffered before being fed to the mixers. All RF inputs and
IF outputs are balanced.
Pins RXON and SXON allow control of the different active
modes and power-down. The SX mode and the RX mode
are independent active states of the LO section and the
receive section respectively. When the logic level on
pin SXON is HIGH, all internal buffers in the LO path of the
circuit are turned on, thus minimizing LO pulling during the
independent powering up of the receive section. Special
care has been taken by design for fast switching from
power-down to any of the different active modes.
QUICK REFERENCE DATA
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CC
supply voltage
2.7
2.8
3.3
V
I
CC(pd)
power-down supply current
-
-
50
A
I
CC(SRX)
supply current in SRX mode
-
25
28
mA
T
amb
ambient temperature
-
30
+25
+70
C
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
UAA2077TS/D
SSOP16
plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
2000 Apr 17
3
Philips Semiconductors
Preliminary specification
2 GHz image rejecting front-end
UAA2077TS
BLOCK DIAGRAM
handbook, full pagewidth
FCA012
14
11
LOGND
135
135
16
QUADRATURE
PHASE
SHIFTER
IF
COMBINER
13
VCCLO
LOCAL OSCILLATOR SECTION
RECEIVE SECTION
1
6
LNAGND
2, 5, 8
n.c.
9
GND
10
RXON
7
SXON
4
RFINB
3
RFINA
LNA
12
LOINB LOINA
45
45
15
VCCLNA
IFA
IFB
UAA2077TS
Fig.1 Block diagram.
PINNING
SYMBOL
PIN
DESCRIPTION
V
CCLNA
1
supply voltage for receive section
(LNA and IF parts)
n.c.
2
not connected
RFINA
3
RF input A (balanced)
RFINB
4
RF input B (balanced)
n.c.
5
not connected
LNAGND
6
ground for receive section (LNA and
IF parts)
SXON
7
SX mode enable input (see Table 1)
n.c.
8
not connected
GND
9
ground
RXON
10
RX mode enable input (see Table 1)
LOINB
11
LO input B (balanced)
LOINA
12
LO input A (balanced)
V
CCLO
13
supply voltage for LO section
LOGND
14
ground for LO section
IFA
15
IF output A (balanced)
IFB
16
IF output B (balanced)
handbook, halfpage
UAA2077TS
FCA011
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCCLNA
n.c.
RFINA
RFINB
n.c.
LNAGND
SXON
n.c.
GND
RXON
LOINB
LOINA
VCCLO
LOGND
IFA
IFB
Fig.2 Pin configuration.
2000 Apr 17
4
Philips Semiconductors
Preliminary specification
2 GHz image rejecting front-end
UAA2077TS
FUNCTIONAL DESCRIPTION
Receive section
The circuit contains a low-noise amplifier followed by two
high dynamic range mixers (see Fig.3). The mixers are of
the Gilbert cell type, the architecture of which is fully
differential.
The LO signal is phase shifted into 45
and 135
signals,
mixed with the RF input signal to provide the
I and Q channel signals. The I and Q channel signals are
buffered, phase shifted by 45
and 135
respectively,
amplified and internally combined, thus obtaining image
rejection.
Balanced signal interfaces are used for minimizing
crosstalk from package parasitics.
The IF output is of a differential open collector type.
A typical application consists of pull-up resistors of 680
at each IF output and a differential load resistance of 1 k
for the IF filter, due to its impedance or its matching
network.
The power gain refers to the resulting power into the 1 k
load. The path for the DC current from V
CC
into the open
collector outputs should be realized by the inductors.
The output signal is limited to V
CC
+ 3V
BE
.
Fast switching between power-down and the RX mode is
controlled by the mode control pin RXON.
handbook, full pagewidth
FCA013
135
16
IF
COMBINER
1
6
LNAGND
2, 5, 8
n.c.
10
RXON
4
RFINB
3
RFINA
LNA
45
15
VCCLNA
IFA
IFB
UAA2077TS
to LO section
9
GND
Fig.3 Receive section.
2000 Apr 17
5
Philips Semiconductors
Preliminary specification
2 GHz image rejecting front-end
UAA2077TS
Local oscillator section
The LO input directly drives the two internal all-pass
networks to provide the quadrature signals for the mixers
(see Fig.4).
The SX mode (see Table 1) is used to activate the
LO section, thus minimizing pulling of the external Voltage
Controlled Oscillator (VCO) when enabling the receive
section. The SX mode is active when the logic level on pin
SXON is HIGH.
Table 1
Operating modes
LOGIC LEVEL
MODE
PIN RXON PIN SXON
LOW
LOW
Power-down mode
HIGH
LOW
RX mode; receive section
active
LOW
HIGH
SX mode; LO section active
HIGH
HIGH
SRX mode; both sections
active
handbook, halfpage
FCA014
14
11
LOGND
135
QUADRATURE
PHASE
SHIFTER
13
VCCLO
7
SXON
12
LOINB
to receive section
LOINA
45
UAA2077TS
9
GND
Fig.4 LO section.
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