2000 Feb 04
2
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
FEATURES
General
Low power consumption
3.0 V power supply
System clock of 256f
s
, 384f
s
and 512f
s
Supports sampling frequencies from 8 to 55 kHz
Non-inverting ADC plus integrated high-pass filter to
cancel DC offset
ADC supports 2 V (RMS) input signals
Overload detector for easy record level control
Separate power control for ADC and DAC
Integrated digital interpolation filter plus non-inverting
DAC
Functions controllable either via L3 microcontroller
interface or via static pins
UDA1344TS is pin and function compatible with
UDA1340M
Small package size (SSOP28)
Easy application.
Multiple format input interface
I
2
S-bus, MSB-justified or LSB-justified
16, 18 and 20 bits format compatible
Three combined data formats with MSB-justified output
and LSB-justified 16, 18 and 20 bits input
1f
s
input and output format data rate.
DAC digital sound processing
The sound processing features of the UDA1344TS can be
used in the L3 mode only:
Digital tone control, bass boost and treble
Digital dB-linear volume control (low microcontroller
load) via L3 microcontroller
Digital de-emphasis for 32, 44.1 and 48 kHz
Soft mute.
Advanced audio configuration
Stereo single-ended input configuration
Stereo line output (under microcontroller volume
control), no post filter required
High linearity, dynamic range and low distortion.
GENERAL DESCRIPTION
The UDA1344TS is a single-chip stereo Analog-to-Digital
Converter (ADC) and Digital-to-Analog Converter (DAC)
with signal processing features employing bitstream
conversion techniques. The low power consumption and
low voltage requirements make the device eminently
suitable for use in low-voltage low-power portable digital
audio equipment which incorporates recording and
playback functions.
The UDA1344TS supports the I
2
S-bus data format with
word lengths of up to 20 bits, the MSB-justified data format
with word lengths of up to 20 bits and the LSB-justified
data format with word lengths of 16, 18 and 20 bits. The
UDA1344TS also supports three combined data formats
with MSB-justified data output and LSB-justified
16, 18 and 20 bits data input.
The UDA1344TS can be controlled either via static pins or
via the L3 interface. In the L3 mode the UDA1344TS has
special Digital Sound Processing (DSP) features in
playback mode such as de-emphasis, volume control,
bass boost, treble and soft mute.
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
UDA1344TS
SSOP28
plastic shrink small outline package; 28 leads; body width 5.3 mm
SOT341-1
2000 Feb 04
3
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
QUICK REFERENCE DATA
Notes
1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately
1 mA by using a series resistor.
2. The input voltage to the ADC is inversely proportional to the supply voltage.
3. The output voltage of the UDA1344TS differs from the output voltage of the UDA1340M.
4. The output of the DAC scales proportionally with the supply voltage.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
DDA(ADC)
ADC analog supply voltage
2.7
3.0
3.6
V
V
DDA(DAC)
DAC analog supply voltage
2.7
3.0
3.6
V
V
DDO
operational amplifier supply voltage
2.7
3.0
3.6
V
V
DDD
digital supply voltage
2.7
3.0
3.6
V
I
DDA(ADC)
ADC analog supply current
operating
-
9.0
11.0
mA
ADC power-down
-
3.5
5.0
mA
I
DDA(DAC)
DAC analog supply current
operating
-
4.0
6.0
mA
DAC power-down
-
25
75
A
I
DDO
operational amplifier supply current
operating
-
4.0
6.0
mA
DAC power-down
-
250
350
A
I
DDD
digital supply current
operating
-
6.0
9.0
mA
DAC power-down
-
2.5
4.0
mA
ADC power-down
-
3.5
5.0
mA
T
amb
ambient temperature
-
40
-
+85
C
Analog-to-digital converter
V
i(rms)
input voltage (RMS value)
notes 1 and 2
-
1.0
-
V
(THD + N)/S
total harmonic distortion-plus-noise to
signal ratio
at 0 dB
-
-
85
-
80
dB
at
-
60 dB; A-weighted
-
-
35
-
30
dB
S/N
signal-to-noise ratio
V
i
= 0 V; A-weighted
-
95
-
dB
cs
channel separation
-
100
-
dB
Digital-to-analog converter
V
o(rms)
output voltage (RMS value)
notes 3 and 4
-
900
-
mV
(THD + N)/S
total harmonic distortion-plus-noise to
signal ratio
at 0 dB
-
-
90
-
85
dB
at
-
60 dB; A-weighted
-
-
37
-
dB
S/N
signal-to-noise ratio
code = 0; A-weighted
-
100
-
dB
cs
channel separation
-
100
-
dB
Power performance
P
ADDA
power consumption in record and
playback mode
-
69
-
mW
P
DA
power consumption in playback mode
-
42
-
mW
P
AD
power consumption in record mode
-
37.5
-
mW
P
PD
power consumption in power-down mode
-
17
-
mW
2000 Feb 04
5
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
PINNING
SYMBOL
PIN
DESCRIPTION
V
SSA(ADC)
1
ADC analog ground
V
DDA(ADC)
2
ADC analog supply voltage
VINL
3
ADC input left
V
ref(A)
4
ADC reference voltage
VINR
5
ADC input right
V
ADCN
6
ADC negative reference voltage
V
ADCP
7
ADC positive reference voltage
MC1
8
mode control 1 input (pull-down)
MP1
9
multi purpose pin 1 output
V
DDD
10
digital supply voltage
V
SSD
11
digital ground
SYSCLK
12
system clock input:
256f
s
, 384f
s
or 512f
s
MP2
13
multi purpose pin 2 input
MP3
14
multi purpose pin 3 input
MP4
15
multi purpose pin 4 input
BCK
16
bit clock input
WS
17
word select input
DATAO
18
data output
DATAI
19
data input
MP5
20
multi purpose pin 5 output
(pull-down)
MC2
21
mode control 2 input (pull-down)
V
SSA(DAC)
22
DAC analog ground
V
DDA(DAC)
23
DAC analog supply voltage
VOUTR
24
DAC output right
V
DDO
25
operational amplifier supply voltage
VOUTL
26
DAC output left
V
SSO
27
operational amplifier ground
V
ref(D)
28
DAC reference voltage
Fig.2 Pin configuration.
handbook, halfpage
VSSA(ADC)
VDDA(ADC)
VINL
Vref(A)
VINR
VADCN
VADCP
MC1
MP1
VDDD
VSSD
SYSCLK
MP2
MP3
Vref(D)
VSSO
VOUTL
VDDO
VDDA(DAC)
VSSA(DAC)
VOUTR
MC2
MP5
DATAI
DATAO
WS
BCK
MP4
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
UDA1344TS
MGL442
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