2000 Feb 08

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio ADC

UDA1360TS

FEATURES

General

Low power consumption

2.4 to 3.6 V power supply

Supports 256 and 384f

system clock

Supports sampling frequency range of 5 to 55 kHz

Small package size (SSOP16)

Integrated high-pass filter to cancel DC offset

Power-down mode

Supports 2 V (RMS) input signals

Easy application

Non-inverting ADC plus decimation filter.

Multiple format output interface

S-bus and MSB-justified format compatible

Up to 20 significant bits serial output.

Advanced audio configuration

Stereo single-ended input configuration

High linearity, dynamic range and low distortion.

GENERAL DESCRIPTION

The UDA1360TS is a single chip stereo Analog-to-Digital
Converter (ADC) employing bitstream conversion
techniques. The low power consumption and low voltage
requirements make the device eminently suitable for use
in low-voltage low-power portable digital audio equipment
which incorporates recording functions.

The UDA1360TS supports the I

S-bus data format and the

MSB-justified data format with word lengths of up to
20 bits.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

DDA

analog supply voltage

2.4

3.0

3.6

DDD

digital supply voltage

2.4

3.0

3.6

DDA

analog supply current

DDD

digital supply current

3.5

amb

operating ambient temperature

+85

ADC

i(rms)

input voltage (RMS value)

see Table 1

1.0

(THD + N)/S

total harmonic distortion plus
noise-to-signal ratio

at 0 dB

60 dB; A-weighted

S/N

signal-to-noise ratio

= 0 V; A-weighted

channel separation

100

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

UDA1360TS

SSOP16

plastic shrink small outline package; 16 leads; body width 4.4 mm

SOT369-1

2000 Feb 08

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio ADC

UDA1360TS

PINNING

SYMBOL

PIN

DESCRIPTION

VINL

left channel input

ref

reference voltage

VINR

right channel input

ref(n)

ADC negative reference voltage

ref(p)

ADC positive reference voltage

SFOR

data format selection input

PWON

power control input

SYSCLK

system clock input 256 or 384f

DDD

digital supply voltage

SSD

digital ground

BCK

bit clock input

word selection input

DATAO

data output

FSEL

system clock frequency select

SSA

analog ground

DDA

analog supply voltage

Fig.2 Pin configuration.

handbook, halfpage

UDA1360TS

MGM968

VINL

Vref

VINR

Vref(n)

Vref(p)

SFOR

PWON

SYSCLK

VDDD

VSSD

BCK

DATAO

FSEL

VSSA

VDDA

FUNCTIONAL DESCRIPTION

System clock

The UDA1360TS accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock. The system frequency is
selectable via the static FSEL pin, and the system clock
must be locked in frequency to the digital interface input
signals.

The options are 256f

(FSEL = LOW) and 384f

(FSEL = HIGH). The sampling frequency range is
5 to 55 kHz.

The BCK clock can be up to 128f

, or in other words the

BCK frequency is 128 times the Word Select (WS)
frequency or less: f

BCK

128

Notes:

1. The WS edge MUST fall on the negative edge of the

BCK at all times for proper operation of the digital I/O
data interface.

2. For MSB justified formats it is important to have a WS

signal with 50% duty factor.

Analog-to-Digital Converter (ADC)

The stereo ADC of the UDA1360TS consists of two
3rd-order Sigma-Delta modulators. They have a modified

Ritchie-coder architecture in a differential switched
capacitor implementation. The over-sampling ratio is 128.

Input level

The overall system gain is proportional to V

DDA

. The 0 dB

input level is defined as that which gives a

1 dB FS digital

output (relative to the full-scale swing). In addition, an input
gain switch is incorporated with the above definitions.

The UDA1360TS front-end is equipped with a selectable
0 or 6 dB gain, in order to supports 2 V (RMS) input using
a series resistor of 12 k

For the definition of the pin settings for 1 or 2 V (RMS)
mode given in Table 1, it is assumed that this resistor is
present as a default component.

If the 2 V (RMS) signal input is not needed, the external
resistor should not be used.

2000 Feb 08

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio ADC

UDA1360TS

Table 1

Application modes using input gain stage

Multiple format output interface

The UDA1360TS supports the following data output
formats;

S-bus with data word length of up to 20 bits

MSB-justified serial format with data word length of up to
20 bits.

The output format can be set by the static SFOR pin. When
SFOR is LOW, the I

S-bus is selected, when SFOR is set

HIGH the MSB-justified format is selected.

The data formats are illustrated in Fig.4. Left and right data
channel words are time multiplexed.

Decimation filter

The decimation from 128f

is performed in two stages.

The first stage realizes 3rd-order sin x/x characteristic.
This filter decreases the sample rate by 16. The second
stage (an FIR filter) consists of 3 half-band filters, each
decimating by a factor of 2.

Table 2

DC cancellation filter characteristics

Mute

On recovery from power-down, the serial data output
DATAO is held LOW until valid data is available from the
decimation filter. This time tracks with the sampling
frequency:

; where f

= 44.1 kHz.

Power-down mode

The PWON pin can control the power saving together with
the optional gain switch for 2 V (RMS) or 1 V (RMS) input.
When the PWON pin is set LOW, the ADC is set to
power-down. When PWON is set to HIGH or to half the
power supply, then either 6 dB gain or 0 dB gain in the
analog front-end is selected.

Application modes

The UDA1360TS can be set to different modes using two
3-level pins and one 2-level pin. The selection of modes is
given in Table 3.

Table 3

Mode selection summary

RESISTOR

(12 k

)

INPUT GAIN

SWITCH

MAXIMUM INPUT

VOLTAGE

Present

0 dB

2 V (RMS)

Present

6 dB

1 V (RMS)

Absent

0 dB

1 V (RMS)

Absent

6 dB

0.5 V (RMS)

ITEM

CONDITION

VALUE

(dB)

Pass-band ripple

none

Pass-band gain

Stop band

>0.55f

Droop

at 0.00045f

0.031

Attenuation at DC

at 0.00000036f

>40

Dynamic range

0 to 0.45f

>110

PIN

SFOR

S-bus

test mode

MSB

PWON

power-down

0 dB gain

6 dB gain

FSEL

256f

384f

12288

----------------

279 ms

2000 Feb 08

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio ADC

UDA1360TS

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134). All voltage referenced to ground,
V

DDD

= V

DDA

= 3 V; T

amb

= 25

C; unless otherwise specified.

Notes

1. All V

and V

connections must be made to the same power supply.

2. Equivalent to discharging a 100 pF capacitor via a 1.5 k

series resistor.

3. Equivalent to discharging a 200 pF capacitor via a 0.75

H series inductor.

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

DDD

digital supply voltage

note 1

5.0

DDA

analog supply voltage

note 1

5.0

xtal(max)

maximum crystal temperature

150

stg

storage temperature

+125

amb

operating ambient temperature

+85

electrostatic handling

note 2

3000

+3000

note 3

300

+300

SYMBOL

PARAMETER

VALUE

UNIT

th(j-a)

thermal resistance from junction to ambient

in free air

140

K/W

Fig.3 Serial interface timing.

handbook, full pagewidth

MGM969

BCK

DATAO

th;WS

ts;WS

tBCK(H)

tBCK(L)

Tcy

td;DAT

td;DAT(WS)

th;DAT

2000 Feb 08

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio ADC

UDA1360TS

DC CHARACTERISTICS
V

DDD

= V

DDA

= 3 V; T

amb

= 25

C; all voltages referenced to ground (pins 10 and 15); unless otherwise specified.

Note

1. All power supply pins (V

and V

) must be connected to the same external power supply unit.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

DDA

analog supply voltage

note 1

2.4

3.0

3.6

DDD

digital supply voltage

note 1

2.4

3.0

3.6

DDA

analog supply current

operation mode

power-down mode

3.5

DDD

digital supply current

operation mode

3.5

power-down mode

0.5

Digital inputs

INS

BCK, FSEL, SYSCLK

AND

HIGH-level input voltage

0.8V

DDD

+ 0.5

LOW-level input voltage

0.5

0.2V

DDD

input leakage current

input capacitance

INS

PWON

AND

SFOR

HIGH-level input voltage

0.8V

DDD

+ 0.5

MIDDLE-level input voltage

0.3V

DDD

0.7V

DDD

LOW-level input voltage

0.5

0.2V

DDD

Digital output; Pin DATAO

HIGH-level output voltage

2 mA

0.85V

DDD

LOW-level output voltage

= 2 mA

0.4

Analog

ref

reference voltage

referenced to V

SSA

0.45V

DDA

0.5V

DDA

0.55V

DDA

input resistance

input capacitance

2000 Feb 08

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio ADC

UDA1360TS

AC CHARACTERISTICS (ANALOG)
V

DDD

= V

DDA

= 3 V; f

= 1 kHz; T

amb

= 25

C; all voltages referenced to ground (pins 10 and 15);

unless otherwise specified.

AC CHARACTERISTICS (DIGITAL)
V

DDD

= V

DDA

= 2.7 to 3.6 V; T

amb

20 to +85

C; all voltages referenced to ground (pins 10 and 15);

unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

i(rms)

input voltage (RMS value)

see Table 1

1.0

unbalance between channels

0.1

(THD + N)/S

total harmonic distortion plus
noise-to-signal ratio

at 0 dB

60 dB; A-weighted

S/N

signal-to-noise ratio

= 0 V; A-weighted

channel separation

100

PSRR

power supply rejection ratio

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Timing

sys

clock cycle

sys

= 256f

782

sys

= 384f

522

CWL

sys

LOW-level pulse width

0.4T

sys

0.6T

sys

CWH

sys

HIGH-level pulse width

0.4T

sys

0.6T

sys

Serial data timing (see Fig.3)

bit clock cycle

BCK(H)

bit clock HIGH time

100

BCK(L)

bit clock LOW time

100

rise time

fall time

d;DAT

data output delay time (from BCK
falling edge)

d;DAT(WS)

data output delay time (from WS
edge)

MSB-justified format

h;DAT

data output hold time

s;WS

word selection set-up time

2000 Feb 08

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio ADC

UDA1360TS

SOLDERING

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250

C. The top-surface temperature of the

packages should preferable be kept below 230

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint must
be placed at a 45

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

2000 Feb 08

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio ADC

UDA1360TS

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PACKAGE

SOLDERING METHOD

WAVE

REFLOW

(1)

BGA, SQFP

not suitable

suitable

HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS

not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO

not recommended

(5)

suitable

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

2000

Philips Semiconductors a worldwide company

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Printed in The Netherlands

753503/25/02/pp

Date of release:

2000 Feb 08

Document order number:

9397 750 05031

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