2001 Jan 17
2
Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
UDA1361TS
FEATURES
General
Low power consumption
256, 384, 512 and 768f
s
system clock
2.4 to 3.6 V power supply
Supports sampling frequency of 5 to 110 kHz
Small package size (SSOP16)
Integrated high-pass filter to cancel DC offset
Power-down mode
Supports 2 V (RMS) input signals
Easy application
Master or slave operation.
Multiple format output interface
I
2
S-bus and MSB-justified format compatible
Up to 24 significant bits serial output.
Advanced audio configuration
Stereo single-ended input configuration
High linearity, dynamic range and low distortion.
GENERAL DESCRIPTION
The UDA1361TS is a single chip stereo Analog-to-Digital
Converter (ADC) employing bitstream conversion
techniques. The low power consumption and low voltage
requirements make the device eminently suitable for use
in low-voltage low-power portable digital audio equipment
which incorporates recording functions.
The UDA1361TS supports the I
2
S-bus data format and the
MSB-justified data format with word lengths of up to
24 bits.
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
UDA1361TS
SSOP16
plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
2001 Jan 17
5
Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
UDA1361TS
FUNCTIONAL DESCRIPTION
System clock
The UDA1361TS accommodates master and slave
modes. The system devices must provide the system
clock regardless of master or slave mode. In the master
mode a system clock frequency of 256f
s
is required. In the
slave mode a system frequency of 256, 384, 512 or 768f
s
is automatically detected (for a system clock of 768f
s
the
sampling frequency must be limited to 55 kHz). The
system clock must be locked in frequency to the digital
interface input signals.
Input level
The overall system gain is proportional to V
DDA
, or more
accurately the potential difference between the reference
voltages V
VRP
and V
VRN
. The
-
1 dB input level at which
THD + N/S is specified corresponds to
-
1 dB(FS) digital
output (relative to the full-scale swing). With an input gain
switch, the input level can be calculated as follows:
at 0 dB gain:
at 6 dB gain:
In applications where a 2 V (RMS) input signal is used, a
12 k
resistor must be connected in series with the input
of the ADC. This forms a voltage divider together with the
internal ADC resistor and ensures that only 1 V (RMS)
maximum is input to the IC.
Using this application for a 2 V (RMS) input signal, the gain
switch must be set to 0 dB. When a 1 V (RMS) input signal
is input to the ADC in the same application the gain switch
must be set to 6 dB.
An overview of the maximum input voltage allowed against
the presence of an external resistor and the setting of the
gain switch is given in Table . The power supply voltage is
assumed to be 3 V.
Table 1
Application modes using input gain stage
Multiple format output interface
The serial interface provides the following data output
formats in both master and slave modes
(see Figs 3, 4 and 5).
I
2
S-bus with data word length of up to 24 bits
MSB-justified serial format with data word length of up to
24 bits.
The master mode drives pins WS (word select; 1f
s
) and
BCK (bit clock; 64f
s
). WS and BCK are received in slave
mode.
Table 2
Master/slave select
Table 3
Select data format
Decimation filter
The decimation from 64f
s
is performed in two stages. The
first stage realizes a 4th-order sinx/x characteristic. This
filter decreases the sample rate by 8.
The second stage, a FIR filter, consists of 3 half-band
filters, each decimating by a factor of 2.
V
i
1 dB
(
)
V
VRP
V
VRN
3
----------------------------------
V (RMS)
=
=
V
i
1 dB
(
)
V
VRP
V
VRN
2
3
----------------------------------
V (RMS)
=
=
RESISTOR
(12 k
)
INPUT GAIN
SWITCH
MAXIMUM
INPUT
VOLTAGE (RMS)
Present
0 dB
2 V
Present
0 dB
1 V
Absent
0 dB
1 V
Absent
6 dB
0.5 V
MSSEL
MASTER/SLAVE SELECT
L
slave mode
H
master mode
M
(reserved for digital test)
SFOR
DATA FORMAT
L
I
2
S-bus data format
H
MSB-justified data format
M
(reserved for analog test)
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