General description

The UDA1384 is a single-chip consisting of 4 plus 1 Analog-to-Digital Converters (ADC)
and 6 Digital-to-Analog Converters (DAC) with signal processing features employing
bitstream conversion techniques. The multichannel configuration makes the device
eminently suitable for use in digital audio equipment which incorporates surround feature.

The UDA1384 supports conventional 2 channels per line data transfer conformable to the
I

S-bus format with word lengths of up to 24 bits, the MSB-justified format with word

lengths of up to 24 bits and the LSB-justified format with word lengths of 16 bits, 20 bits
and 24 bits, as well as 4 channels to 6 channels per line transfer mode. The device also
supports a combination of the MSB-justified output format and the LSB-justified input
format. The UDA1384 has special sound processing features in the Direct Stream Digital
(DSD) playback mode, de-emphasis, volume and mute which can be controlled via the
L3-bus or I

C-bus interface.

Features

2.1 General

2.7 V to 3.6 V power supply

5 V tolerant digital inputs

24-bit data path

Selectable control: via L3-bus or I

C-bus microcontroller interface

Supports sample frequency ranges for:

Audio ADC: f

= 16 kHz to 100 kHz

Voice ADC: f

= 7 kHz to 50 kHz

Audio DAC: f

= 16 kHz to 200 kHz

Separate power control for ADC and DAC

ADC plus integrated high-pass filter to cancel DC offset

Integrated digital filter plus DAC

Slave mode only applications

Easy application

UDA1384

Multichannel audio coder-decoder

Rev. 02 -- 17 January 2005

Product data sheet

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2 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

2.2 Multiple format data interface

Audio interface supports standard I

S-bus, MSB-justified, LSB-justified and two

multichannel formats

Voice interface supports I

S-bus and mono channel formats

2.3 Digital sound processing

Control via L3-bus or I

C-bus:

Channel independent digital logarithmic volume

Digital de-emphasis for f

= 32 kHz, 44.1 kHz, 48 kHz or 96 kHz

Soft or quick mute

Output signal polarity control

2.4 Advanced audio configuration

Inputs:

4 single-ended audio inputs (2

stereo) with programmable gain amplifiers

1 single-ended voice input

Outputs:

6 differential audio outputs (3

stereo)

DSD mode to support stereo DSD playback

High linearity, wide dynamic range and low distortion

DAC digital filter with selectable sharp or soft roll-off

Applications

Excellently suitable for multichannel home audio-video application

Quick reference data

Table 1:

Quick reference data

DDD

= V

DDA(AD)

= V

DDA(DA)

= 3.3 V; T

amb

= 25

C; R

= 22 k

; all voltages referenced to ground

(pins V

); unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supplies

DDA(AD)

ADC analog supply
voltage

2.7

3.3

3.6

DDA(DA)

DAC analog supply
voltage

2.7

3.3

3.6

DDD

digital supply voltage

2.7

3.3

3.6

DDA(AD)

ADC analog supply
current

ADC

= 48 kHz

DDA(DA)

DAC analog supply
current

DAC

= 48 kHz

DDD

digital supply current f

ADC

= f

DAC

= 48 kHz;

VOICE

= 48 kHz

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Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

[1]

The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to
approximately 1 mA by using a series resistor.

[2]

The input voltage to the ADC scales proportionally with the power supply voltage.

Ordering information

DDD(pd)

digital supply current
in Power-down mode

audio and voice
ADCs power-down

DAC power-down

amb

ambient temperature

+85

Audio analog-to-digital converter

digital output level

at 0 dB setting;
900 mV input

[1] [2]

2.5

1.2

0.7

(THD+N)/S

total harmonic
distortion-plus-noise
to signal ratio

1 dBFS

60 dBFS;

A-weighted

S/N

signal-to-noise ratio

code = 0; A-weighted

channel separation

100

Digital-to-analog converter

Differential mode

o(rms)

output voltage
(RMS value)

at 0 dBFS digital
input

1.9

2.0

2.1

(THD+N)/S

total harmonic
distortion-plus-noise
to signal ratio

at 0 dBFS

60 dBFS;

A-weighted

S/N

signal-to-noise ratio

code = 0; A-weighted

100

110

channel separation

114

Single-ended mode

o(rms)

output voltage
(RMS value)

at 0 dBFS digital
input

1.0

(THD+N)/S

total harmonic
distortion-plus-noise
to signal ratio

at 0 dBFS

60 dBFS;

A-weighted

S/N

signal-to-noise ratio

code = 0; A-weighted

105

channel separation

110

Table 1:

Quick reference data

...continued

DDD

= V

DDA(AD)

= V

DDA(DA)

= 3.3 V; T

amb

= 25

C; R

= 22 k

; all voltages referenced to ground

(pins V

); unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 2:

Ordering information

Type number

Package

Name

Description

Version

UDA1384H

QFP44

plastic quad flat package; 44 leads (lead length
1.3 mm); body 10

1.75 mm

SOT307-2

9397 750 14366

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Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

Pinning information

7.1 Pinning

7.2 Pin description

Fig 2.

Pin configuration

UDA1384H

ref

VOUT2P

VINL1

VOUT1N

SSA(AD)

VOUT1P

VINR1

I2C_L3

DDA(AD)

DDD

VINL2

SSD

ADCN

DATADA3

VINR2

DATADA2

ADCP

DATADA1

VVOICE

BCKDA

TEST

WSDA

DATAAD2

VOUT6N

DATAAD1

VOUT6P

BCKAD

VOUT5N

WSAD

VOUT5P

DATAV

SSA(D

BCKV

VOUT4N

WSV

VOUT4P

SYSCLK

A(D

MCMODE

VOUT3N

MCCLK

VOUT3P

MCDATA

VOUT2N

001aac311

Table 3:

Pin description

Symbol

Pin

Type

Description

ref

AIO

ADC reference voltage

VINL1

AIO

ADC 1 input left

SSA(AD)

AGND

ADC analog ground

VINR1

AIO

ADC 1 input right

DDA(AD)

ADC analog supply voltage

VINL2

AIO

ADC 2 input left

ADCN

AIO

ADC reference voltage N

VINR2

AIO

ADC 2 input right

ADCP

AIO

ADC reference voltage P

VVOICE

AIO

voice ADC input

TEST

DID

test input; must be connected to digital ground (V

SSD

) in

application

DATAAD2

ADC 2 data output

DATAAD1

ADC 1 data output

BCKAD

DIS

ADC bit clock input

WSAD

ADC word select input

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Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

[1]

See

Table 4

DATAV

voice data output

BCKV

DIS

voice bit clock input

WSV

DIO

voice word select input or output

SYSCLK

DIS

system clock input: 256f

, 384f

, 512f

or 768f

MCMODE

L3-bus L3MODE input or I

C-bus DAC mute control input

MCCLK

DIS

L3-bus L3CLOCK input or I

C-bus SCL input

MCDATA

IIC

L3-bus L3DATA input and output or I

C-bus SDA input and

output

WSDA

DAC word select input

BCKDA

DIS

DAC bit clock input

DATADA1

DAC channel 1 and channel 2 data input

DATADA2

DAC channel 3 and channel 4 data input

DATADA3

DAC channel 5 and channel 6 data input

SSD

DGND

digital ground

DDD

digital supply voltage

I2C_L3

selection input for L3-bus or I

C-bus control

VOUT1P

AIO

DAC 1 positive output

VOUT1N

AIO

DAC 1 negative output

VOUT2P

AIO

DAC 2 positive output

VOUT2N

AIO

DAC 2 negative output

VOUT3P

AIO

DAC 3 positive output

VOUT3N

AIO

DAC 3 negative output

DDA(DA)

DAC analog supply voltage

VOUT4P

AIO

DAC 4 positive output

VOUT4N

AIO

DAC 4 negative output

SSA(DA)

AGND

DAC analog ground

VOUT5P

AIO

DAC 5 positive output

VOUT5N

AIO

DAC 5 negative output

VOUT6P

AIO

DAC 6 positive output

VOUT6N

AIO

DAC 6 negative output

Table 4:

Pin types

Type

Description

AGND

analog ground

AIO

analog input and output

analog supply

DGND

digital ground

digital input

DID

digital input with internal pull-down resistor

DIO

digital input and output

Table 3:

Pin description

...continued

Symbol

Pin

Type

Description

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UDA1384

Multichannel audio coder-decoder

Functional description

8.1 System clock

The UDA1384 operates in slave mode only; this means that in all applications the system
must provide either the system clock (the bit clock for the voice ADC) or the word clock.

The audio ADC part, the voice ADC part and the DAC part can operate at different
sampling frequencies (DAC-WS and ADC-WS modes) as well as a common frequency
(SYSCLK, WSDA and DSD modes).

The voice ADC part supports a sampling frequency up to 50 kHz and the audio ADC
supports a sampling frequency up to 100 kHz. The DAC sampling frequency range is
extended up to 200 kHz with the range above 100 kHz being supported through 192 kHz
sampling mode, which halves the oversampling ratio of SYSCLK and internal clocks.

The mode of operation of the audio and voice channels can be set via the L3-bus or
I

C-bus microcontroller interface and are summarized in

Table 5

and

Table 6

When applied, the system clock must be locked in frequency to the corresponding digital
interface clocks.

The voice ADC part can either receive or generate the WSV signal as shown in

Table 6

DIS

digital Schmitt-triggered input

digital output

digital supply

IIC

input and open-drain output for I

C-bus

Table 4:

Pin types

...continued

Type

Description

Table 5:

Audio ADC and DAC operating clock mode

Mode

Audio ADC

Audio DAC

Clock

Frequency

Clock

Frequency

SYSCLK

256f

, 384f

, 512f

or 768f

SYSCLK

256f

, 384f

, 512f

or 768f

SYSCLK

128f

, 192f

, 256f

or 384f

;

192 kHz sampling mode

DAC-WS

SYSCLK

256f

, 384f

, 512f

or 768f

WSDA

ADC-WS

WSAD

SYSCLK

256f

, 384f

, 512f

or 768f

SYSCLK

128f

, 192f

, 256f

or 384f

;

192 kHz sampling mode

WSDA

DSD

SYSCLK

44.1 kHz

512

SYSCLK

44.1 kHz

512

Table 6:

Voice ADC operating clock mode

Mode

Voice ADC

Bit clock frequency (BCKV)

Word select (WSV)

WSV-in

input: 32f

, 64f

, 128f

or 256f

input

WSV-out

input: 32f

, 64f

, 128f

or 256f

output

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UDA1384

Multichannel audio coder-decoder

8.2 Audio analog-to-digital converter (audio ADC)

The audio analog-to-digital front-end of the UDA1384 consists of 4-channel single-ended
ADCs with programmable gain stage (from 0 dB to 24 dB with 3 dB steps), controlled via
the microcontroller interface. Using the PGA feature, it is possible to accept an input signal
of 900 mV (RMS) or 1.8 V (RMS) if an external resistor of 10 k

is used in series. The

schematic of audio ADC front-end is shown in

Figure 3

8.3 Voice Analog-to-Digital Converter (voice ADC)

The voice analog-to-digital front-end of the UDA1384 consists of a single-channel
single-ended ADC with a fixed gain (26 dB) Low Noise Amplifier (LNA). Together with the
digital variable gain amplification stage, the voice ADC provides optimal processing and
reproduction of the microphone signal. The supported sampling frequency range is from
7 kHz to 50 kHz. Power-down of the LNA and the ADC can be controlled separately.

8.4 Decimation filter of audio ADC

The decimation from 64f

is performed in two stages. The first stage realizes

characteristics with a decimation factor of 8. The second stage consists of three half-band
filters, each decimating by a factor of 2. The filter characteristics are shown in

Table 7

8.5 Decimation filter of voice ADC

The voice ADC decimation filter is realized with the combination of a Finite Impulse
Response (FIR) filter and Infinite Impulse Response (IIR) filter for shorter group delay. The
filter characteristics are shown in

Table 8

. During the power-on sequence, the output of

the ADC is hard muted for a certain period. This hard-mute time can be chosen between
1024 samples and 2048 samples.

Fig 3.

Schematic of audio ADC front-end

mgu582

ref

ADC

DDA

= 3.3 V

VINL,

VINR

10 k

(0 dB setting)

10 k

input signal

2 V (RMS)

Table 7:

Decimation filter characteristics (audio ADC)

Item

Condition

Value (dB)

Pass-band ripple

to 0.45f

0.01

Pass-band droop

0.45f

0.2

Stop band

> 0.55f

Dynamic range

to 0.45f

> 135

sin

----------

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UDA1384

Multichannel audio coder-decoder

8.6 Interpolation filter of DAC

The digital interpolation filter interpolates from 1f

to 128f

(or to 64f

in the 192 kHz

sampling mode) by cascading FIR filters, and has two sets of filter coefficients for sharp
and slow roll-off as given in

Table 9

and

Table 10

8.7 Noise shaper of DAC

The 3rd-order noise shaper operates at either 128f

or 64f

(in the 192 kHz sampling

mode), and converts the 24-bit input signal into a 5-bit signal stream. The noise shaper
shifts in-band quantization noise to frequencies well above the audio band. This noise
shaping technique enables high signal-to-noise ratios to be achieved.

8.8 Digital mixer

The UDA1384 has 6 digital mixers inside the interpolator (see

Figure 4

). The ADC signals

can be mixed with the I

S-bus input signals. The mixing of the ADC signals can be

selected by the bits MIX[1:0].

Table 8:

Decimation filter characteristics (voice ADC)

Item

Condition

Value (dB)

Pass-band ripple

to 0.45f

0.05

Pass-band droop

0.45f

0.2

Stop band

> 0.55f

Dynamic range

to 0.45f

> 110

Table 9:

Interpolation filter characteristics (sharp roll-off)

Item

Condition

Value (dB)

Pass-band ripple

to 0.45f

0.002

Stop band

> 0.55f

Dynamic range

to 0.45f

> 135

Table 10:

Interpolation filter characteristics (slow roll-off)

Item

Condition

Value (dB)

Pass-band ripple

to 0.22f

0.002

Pass-band droop

0.45f

3.1

Stop band

> 0.78f

Dynamic range

to 0.22f

> 135

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Multichannel audio coder-decoder

8.9 Audio digital-to-analog converters

The audio digital-to-analog front-end of the UDA1384 consists of 6-channel differential
SDACs: an SDAC is a multi-bit DAC based upon switched resistors. To minimize data
dependent modulation effects, a Dynamic Element Matching (DEM) algorithm scrambler
circuit and DC current compensation circuit are implemented with the SDAC.

8.10 Power-on reset

The UDA1384 has an internal power-on reset circuit which initializes the device (see

Figure 5

). All the digital sound processing features and the system controlling features are

set to their default values in the L3-bus and the I

C-bus modes.

The reset time (see

Figure 6

) is determined by an external capacitor which is connected

between pin V

ref

and ground. The reset time should be at least 250

s for V

ref

< 1.25 V.

When V

DDA(AD)

is switched off, the device will be reset again for V

ref

< 0.75 V.

During the reset time, the system clock should be running.

Fig 4.

Block diagram of DAC mixer

mgw786

MIX[1:0]

DIS[1:0]

ICS[1:0]

from ADC

MIXER

VOLUME

MIXER

MUTE

DAC1

VOLUME

DE-EMPHASIS

MUTE

DAC2

same as above

DAC3

same as above

DAC4

same as above

DAC5

same as above

DAC6

same as above

INTERPOLATION

FILTER

ch1

mixer input

ch2

ch3
ch4

from I

S-bus

DATADA1

DATADA2

DATADA3

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ights reser

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oduct data sheet

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v

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uar

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A1384

Multic

hannel audio coder

-decoder

Fig 7.

Formats of input and output data (single-channel)

MSB

LEFT

LSB-JUSTIFIED FORMAT 20 BITS

BCK

DATA

RIGHT

B19

LSB

MSB

B19

LSB

MSB

= 8

LEFT

S-BUS FORMAT

BCK

DATA

RIGHT

= 8

MSB

mgt020

B10

LEFT

LSB-JUSTIFIED FORMAT 24 BITS

BCK

DATA

RIGHT

MSB

B23

LSB

B10

MSB

B23

LSB

MSB

LEFT

LSB-JUSTIFIED FORMAT 16 BITS

BCK

DATA

RIGHT

B15

LSB

MSB

B15

LSB

MSB-JUSTIFIED FORMAT

LEFT

RIGHT

MSB

LSB

MSB

= 8

BCK

DATA

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oduct data sheet

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uar

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A1384

Multic

hannel audio coder

-decoder

(1) Format 1.

(2) Format 2.

Fig 8.

Formats of input and output data (multichannel)

mgu588

MULTICHANNEL FORMAT 20 BITS

BCK

DATA

CH1

MSB

LSB

MSB

LSB

CH3

LSB

CH5

CH2

MSB

LSB

MSB

MULTICHANNEL FORMAT 24 BITS

(1)

BCK

DATA

CH1

MSB

LSB

MSB

LSB

CH3

LSB

CH5

CH2

MSB

LSB

MSB

LSB

CH4

LSB

CH6

MULTICHANNEL FORMAT 24 BITS

(2)

BCK

DATA

CH1

MSB

LSB

MSB

CH3

MSB

LSB

CH5

LSB

CH2

MSB

LSB

MSB

CH4

MSB

LSB

CH6

LSB

MSB

LSB

CH4

LSB

CH6

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8.12 Voice digital interface

The following voice formats can be selected via the microcontroller interface:

S-bus format with data word length of up to 20 bits. The left and the right channels

contain the same data.

Mono channel format with data word length of up to 20 bits.

The formats are illustrated in

Figure 9

8.13 DSD mode

The UDA1384 can receive 2.8224 MHz DSD signals and generate 88.2 kHz multibit PCM
signals as well as analog signal outputs. The configuration of the UDA1384 in the DSD
mode is shown in

Figure 10

Fig 9.

Voice digital interface formats

mgu587

MSB

LEFT

S-BUS FORMAT

BCK

DATA

RIGHT

MSB

MONO CHANNEL FORMAT

BCK

DATA

MSB

Fig 10. DSD mode

mgu584

left

channel

2.8224 MHz

DSD

right

channel

5.6448 MHz

88.2 kHz

BCKAD

DATADA3

DATADA2

WSAD

WSDA

88.2 kHz

22.5792 MHz

5.6448 MHz

S-bus

(left and right)

88.2 kHz

PCM data

DATADA1

DATAAD1

BCKDA

SYSCLK

DAC

INTERPOLATION

NOISE SHAPING

S-BUS

INTERFACE 2

DECIMATION

FILTER

S-BUS

INTERFACE 1

OUT1N

OUT1P

left
channel

DAC

OUT2N

OUT2P

right
channel

analog
output

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Multichannel audio coder-decoder

8.14 Microcontroller interface mode

The microcontroller interface mode can be selected as shown in

Table 11

L3-bus mode when pin I2C_L3 = LOW

C-bus mode when pin I2C_L3 = HIGH

All the features are accessible with the I

C-bus interface protocol as with the L3-bus

interface protocol.

The detailed description of the device operation in the L3-bus mode and I

C-bus mode is

given in

Section 9

and

Section 10

, respectively.

L3-bus interface

9.1 General

The UDA1384 has an L3-bus microcontroller interface and all the digital sound processing
features and various system settings can be controlled by a microcontroller.

The exchange of data and control information between the microcontroller and the
UDA1384 is LSB first and is accomplished through a serial hardware L3-bus interface
comprising the following pins:

MCCLK: clock line with signal L3CLOCK

MCDATA: data line with signal L3DATA

MCMODE: mode line with signal L3MODE

The L3-bus format has two modes of operation:

Address mode

Data transfer mode

The address mode is used to select a device for a subsequent data transfer. The address
mode is characterized by signal L3MODE = LOW and a burst of 8 pulses for signal
L3CLOCK, accompanied by 8 bits (see

Figure 11

Table 11:

Pin function in the L3-bus or I

C-bus mode

Pin

Level on pin I2C_L3

LOW

HIGH

L3-bus mode signal

C-bus mode signal

MCCLK

L3CLOCK

SCL

MCDATA

L3DATA

SDA

MCMODE

L3MODE

QMUTE

Table 12:

QMUTE

Signal QMUTE

Function

LOW

no muting

HIGH

muting

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The data transfer mode is characterized by signal L3MODE = HIGH and is used to
transfer one or more bytes representing a register address, instruction or data.

Basically, two types of data transfers can be defined:

Write action: data transfer to the device

Read action: data transfer from the device.

9.2 Device addressing

The device address consists of one byte with:

Data Operating Mode (DOM) bits 0 and 1 representing the type of data transfer (see

Table 13

)

Address bits 2 to 7 representing a 6-bit device address. The address of the UDA1384
is 01 0100 (bits 2 to 7).

9.3 Register addressing

After sending the device address (including DOM bits), indicating whether the information
is to be read or written, one data byte is sent using bit 0 to indicate whether the
information will be read or written and bits 1 to 7 for the destination register address.

Basically, there are 3 methods for register addressing:

1. Addressing for write data: bit 0 is logic 0 indicating a write action to the destination

Figure 11

2. Addressing for prepare read: bit is logic 1, indicating that data will be read from the

Figure 12

3. Addressing for data read action. Here, the device returns a register address prior to

sending data from that register. When bit 0 is logic 0, the register address is valid;
when bit 0 is logic 1, the register address is invalid (see

Figure 12

Table 13:

Selection of data transfer

DOM

Transfer

Bit 1

Bit 0

not used

write data or prepare read

read data

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9.4 Data write mode

The data write mode is explained in the signal diagram of

Figure 11

. For writing data to a

device, 4 bytes must be sent (see

Table 14

1. Byte 1 starting with `01' for signalling the write action to the device, followed by the

device address `01 0100'

2. Byte 2 starting with a `0' for signalling the write action, followed by 7 bits indicating the

destination address in binary format with bit A6 being the MSB and bit A0 being the
LSB

3. Byte 3 with bit D15 being the MSB

4. Byte 4 with bit D0 being the LSB

It should be noted that each time a new destination register address needs to be written,
the device address must be sent again.

9.5 Data read mode

To read data from the device, a prepare read must first be done and then data read. The
data read mode is explained in the signal diagram of

Figure 12

For reading data from a device, the following 6 bytes are involved (see

Table 15

1. Byte 1 with the device address, including `01' for signalling the write action to the

device.

2. Byte 2 is sent with the register address from which data needs to be read. This byte

starts with a `1', which indicates that there will be a read action from the register,
followed by 7 bits for the destination address in binary format, with bit A6 being the
MSB and bit A0 being the LSB.

3. Byte 3 with the device address, including `11' is sent to the device. The `11' indicates

that the device must write data to the microcontroller.

4. Byte 4 sent by the device to the bus, with the (requested) register address and a flag

bit indicating whether the requested register was valid (bit is logic 0) or invalid (bit is
logic 1).

5. Byte 5 sent by the device to the bus, with the data information in binary format, with

bit D15 being the MSB.

6. Byte 6 sent by the device to the bus, with the data information in binary format, with

bit D0 being the LSB.

Table 14:

L3-bus write data

Byte

L3-bus
mode

Action

First in time

Latest in time

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

address

device
address

data
transfer

data
byte 1

D15

D14

D13

D12

D11

D10

data
transfer

data
byte 2

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Multichannel audio coder-decoder

10. I

C-bus interface

10.1 General

The UDA1384 has an I

C-bus microcontroller interface. All the features are accessible

with the I

C-bus interface protocol. In the I

C-bus mode, the DAC mute function is

accessible via pin MCMODE with signal QMUTE.

The exchange of data and control information between the microcontroller and the
UDA1384 is accomplished through a serial hardware interface comprising the following
pins as shown in

Table 11

MCCLK: clock line with signal SCL

MCDATA: data line with signal SDA

10.2 Characteristics of the I

C-bus

The bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to the supply voltage V

via a pull-up resistor when connected to the output

stages of a microcontroller. For a 400 kHz IC, the recommendation for this type of bus
from Philips Semiconductors must be followed (e.g. up to loads of 200 pF on the bus a
pull-up resistor can be used, between 200 pF and 400 pF a current source or switched
resistor must be used). Data transfer can only be initiated when the bus is not busy.

10.3 Bit transfer

One data bit is transferred during each clock pulse (see

Figure 13

). The data on the SDA

line must remain stable during the HIGH period of the clock pulse as changes in the data
line at this time will be interpreted as control signals. The maximum clock frequency is
400 kHz.

To be able to run on this high frequency, all the inputs and outputs connected to this bus
must be designed for this high-speed I

C-bus according to the Philips specification.

Table 15:

L3-bus read data

Byte

L3-bus
mode

Action

First in time

Latest in time

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

address

device
address

data
transfer

address

device
address

data
transfer

0 or 1

data
transfer

data
byte 1

D15

D14

D13

D12

D11

D10

data
transfer

data
byte 2

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10.4 Byte transfer

Each byte (8 bits) is transferred with the MSB first (see

Table 16

10.5 Data transfer

A device generating a message is a transmitter; a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves.

10.6 Start and stop conditions

Both data and clock line will remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH, is defined as a start condition (S); see

Figure 14

. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as

a stop condition (P).

10.7 Acknowledgment

The number of data bits transferred between the start and stop conditions from the
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit (see

Figure 15

). At the acknowledge bit the data line is released by the

master and the master generates an extra acknowledge related clock pulse.

Fig 13. Bit transfer on the I

C-bus

mbc621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Table 16:

Byte transfer

Bit number

MSB

LSB

Fig 14. START and STOP conditions on the I

C-bus

mbc622

SDA

SCL

STOP condition

SDA

SCL

START condition

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A slave receiver which is addressed, must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge
clock pulse, so the SDA line is stable LOW during the HIGH period of the acknowledge
related clock pulse. Set-up and hold times must be taken into account. A master receiver
must signal an end of data to the transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event, the transmitter must leave the
data line HIGH to enable the master to generate a stop condition.

10.8 Device address

Before any data is transmitted on the I

C-bus, the device which should respond is

addressed first. The addressing is always done with byte 1 transmitted after the start
procedure. The UDA1384 acts as a slave receiver or a slave transmitter.

Therefore, the clock signal SCL is only an input signal. The data signal SDA is a
bidirectional line. The UDA1384 device address is shown in

Table 17

10.9 Register address

The register addresses in the I

C-bus mode are the same as in the L3-bus mode. The

Section 11

10.10 Write and read data

The I

C-bus configurations for a write and read cycle are shown in

Table 18

and

Table 19

respectively.

Fig 15. Acknowledge on the I

C-bus

mbc602

START

condition

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from

master

Table 17:

C-bus device address of UDA1384

Device address

R/W

0/1

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UDA1384

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The write cycle is used to write groups of two bytes to the internal registers for the
settings. It is also possible to read the registers for the device status information.

10.11 Write cycle

The I

C-bus configuration for a write cycle is shown in

Table 18

. The write cycle is used to

write the data to the internal registers. The device and register addresses are one byte
each, the setting data is always a pair of two bytes.

The format of the write cycle is as follows:

1. The microcontroller starts with a start condition (S).

2. The first byte (8 bits) contains the device address `0011 000' and a logic 0 (write) for

the R/W bit.

3. This is followed by an acknowledge (A) from the UDA1384.

4. After this the microcontroller writes the 8-bit register address (ADDR) where the

writing of the register content of the UDA1384 must start.

5. The UDA1384 acknowledges this register address (A).

6. The microcontroller sends 2 bytes data with the Most Significant (MS) byte first and

then the Least Significant (LS) byte. After each byte an acknowledge is followed from
the UDA1384.

7. If repeated groups of 2 bytes data are transmitted, then the register address is auto

incremented. After each byte an acknowledge is followed from the UDA1384.

8. Finally, the UDA1384 frees the I

C-bus and the microcontroller can generate a stop

condition (P).

[1]

Auto increment of register address.

10.12 Read cycle

The read cycle is used to read the data values from the internal registers. The I

C-bus

configuration for a read cycle is shown in

Table 19

The format of the read cycle is as follows:

1. The microcontroller starts with a start condition (S).

2. The first byte (8 bits) contains the device address `0011 000' and a logic 0 (write) for

the R/W bit.

3. This is followed by an acknowledge (A) from the UDA1384.

4. After this the microcontroller writes the 8-bit register address (ADDR) where the

reading of the register content of the UDA1384 must start.

5. The UDA1384 acknowledges this register address.

6. Then the microcontroller generates a repeated start (Sr).

Table 18:

Master transmitter writes to UDA1384 registers in the I

C-bus mode

Device
address

R/W

Data 1

Data 2

[1]

Data n

[1]

0011 000 0

ADDR

A MS1 A LS1

A MS2

LS2

A MSn

A LSn A

A = acknowledge from UDA1384

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7. Then the microcontroller generates the device address `0011 000' again, but this time

followed by a logic 1 (read) of the R/W bit. An acknowledge is followed from the
UDA1384.

8. The UDA1384 sends 2 bytes data with the Most Significant (MS) byte first and then

the Least Significant (LS) byte. After each byte an acknowledge is followed from the
microcontroller (master).

9. If repeated groups of 2 bytes are transmitted, then the register address is auto

incremented. After each byte an acknowledge is followed from the microcontroller.

10.The microcontroller stops this cycle by generating a Negative Acknowledge (NA).

11.Finally, the UDA1384 frees the I

C-bus and the microcontroller can generate a stop

condition (P).

[1]

Auto increment of register address.

11. Register mapping

In this chapter the register addressing and mapping of the microcontroller interface of the
UDA1384 is given.

Table 20

an overview of the register mapping is given.

Table 21

the actual register mapping is given and the register definitions are explained

Section 11.3

Section 11.14

11.1 Address mapping

Table 19:

Master transmitter reads from the UDA1384 registers in the I

C-bus mode

Device
address

R/W

Device
address

R/W Data 1

Data 2

[1]

Data n

[1]

0011 000 0

ADDR

Sr 0011 000 1 A

MS1 A

LS1

MS2 A

LS2

MSn A

LSn

A = acknowledge from UDA1384

A = acknowledge from master

Table 20:

Overview of register mapping

Address

Function

System settings

00h

system

01h

audio ADC and DAC subsystem

02h

voice ADC system

Status (read out registers)

0Fh

status outputs

Interpolator settings

10h

DAC channel and feature selection

11h

DAC feature control

12h

DAC channel 1

13h

DAC channel 2

14h

DAC channel 3

15h

DAC channel 4

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11.2 Register mapping

Table 21:

UDA1384 register mapping

[1]

Add

Function

D15

D14

D13

D12

D11

D10

System settings

00h

system

RST

[2]

VFS1

VFS0

VCE

VAP

DSD

SC1

SC0

OP1

OP0

FS1

FS0

ACE

ADP

DCE

DAP

01h

audio ADC and DAC
subsystem

PAB

PAA

MTB

MTA

AIF2

AIF1

AIF0

DAG

FIL

DVD

DIS1

DIS0

DIF2

DIF1

DIF0

02h

voice ADC system

BCK1

BCK0

WSM

VH1

VH0

PVA

MTV

VIF

Status (read out only)

0Fh

status outputs

AS1

AS0

DS2

DS1

DS0

Interpolator settings

10h

DAC channel and
feature selection

MIX1

MIX0

MC5

MC4

MC3

MC2

MC1

MC0

SEL1

SEL0

CS5

CS4

CS3

CS2

CS1

CS0

11h

DAC feature control

ICS1

ICS0

DE2

DE1

DE0

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

12h

DAC channel 1

ICS1

ICS0

DE2

DE1

DE0

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

13h

DAC channel 2

DE2

DE1

DE0

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

14h

DAC channel 3

ICS1

ICS0

DE2

DE1

DE0

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

15h

DAC channel 4

DE2

DE1

DE0

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

16h

DAC channel 5

ICS1

ICS0

DE2

DE1

DE0

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

17h

DAC channel 6

DE2

DE1

DE0

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

18h

DAC mixing
channel 1

ICS1

ICS0

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

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[1]

When writing new settings via the L3-bus interface, the default values should always be set to warrant correct operation. Read access to the DAC features register 11h will not
return valid data.

[2]

When bit RST is set to logic 1, the default values are set to all the registers as shown in

Table 21

. When start-up, all the registers in 00h are initialized as the default values and the

mute control bits MTA, MTB, MTV, MT and QM are set to logic 1. All other registers have non fixed values.

19h

DAC mixing
channel 2

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

1Ah

DAC mixing
channel 3

ICS1

ICS0

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

1Bh

DAC mixing
channel 4

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

1Ch

DAC mixing
channel 5

ICS1

ICS0

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

1Dh

DAC mixing
channel 6

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

ADC input amplifier gain settings

20h

ADC 1 and ADC 2
input amplifier gain

IB3

IB2

IB1

IB0

IA3

IA2

IA1

IA0

21h

voice ADC input
amplifier gain

IV4

IV3

IV2

IV1

IV0

Supplemental settings

30h

supplemental
settings 1

PDT

31h

supplemental
settings 2

DITH2 DITH1 DITH0 -

VMTP PDLNA

Table 21:

UDA1384 register mapping

[1]

...continued

Add

Function

D15

D14

D13

D12

D11

D10

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11.3 System settings

Table 22:

System register (address 00h) bit allocation

Bit

Symbol

RST

VFS1

VFS0

VCE

VAP

DSD

SC1

SC0

Reset

Access

read and write

Bit

Symbol

OP1

OP0

FS1

FS0

ACE

ADP

DCE

DAP

Reset

Access

read and write

Table 23:

Description of system register bits

Bit

Symbol

Description

RST

Reset. Bit RST initializes the L3-bus registers with the default settings.

1 = Reset to default settings

0 = No reset

14 to 13

VFS[1:0]

Voice ADC sampling frequency. A 2-bit value to select the voice ADC
sampling frequency. Default 00. See

Table 24

VCE

Voice ADC clock enable.

1 = clock enabled (default)

0 = clock disabled

VAP

Voice ADC power control. Bit VAP is to reduce the power consumption of
the voice ADC.

1 = state is power-on

0 = state is power-off (default)

DSD

DSD mode selection. Bit DSD selects the DSD mode.

1 = DSD mode

0 = normal mode (default)

9 to 8

SC[1:0]

System clock frequency. A 2-bit value to select the used external clock
frequency. 128f

system clock for the DAC can be used by setting

bit DVD = 1. Default 00. See

Table 25

7 to 6

OP[1:0]

Operating mode selection. A 2-bit value to select the operation mode of
the audio ADC and DAC. Default 00. See

Table 26

5 to 4

FS[1:0]

Sampling frequency. A 2-bit value to select the sampling frequency of the
audio ADC and DAC in the WS mode. Default 01. See

Table 27

ACE

ADC clock enable. Bit ACE enables the audio ADC clock

1 = clock enabled (default)

0 = clock disabled

ADP

ADC power control. Bit ADP is to reduce the power consumption of the
audio ADC.

1 = state is power-on

0 = state is power-off (default)

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DCE

DAC clock enable. Bit DCE enables the DAC clock.

1 = clock enabled (default)

0 = clock disabled

DAP

DAC power control. Bit DAP is to reduce the power consumption of the
DAC.

1 = state is power-on

0 = state is power-off (default)

Table 24:

Voice ADC sampling frequency bits

VFS1

VFS0

Function

6.25 kHz to 12.5 kHz (default)

12.5 kHz to 25 kHz

25 kHz to 50 kHz

reserved

Table 25:

System clock frequency bits

SC1

SC0

ADC

DAC

Remark

Bit DVD = 0

Bit DVD = 1

256f

128f

default

384f

192f

512f

256f

768f

384f

Table 26:

Operating mode bits

OP1

OP0

ADC mode

DAC mode

Remark

SYSCLK (256f

, 384f

, 512f

or 768f

)

SYSCLK (128f

, 256f

, 384f

512f

or 768f

)

default

SYSCLK (256f

, 384f

, 512f

or 768f

)

WSDA (1f

)

WSAD (1f

)

SYSCLK (128f

, 256f

, 384f

512f

or 768f

)

WSDA (1f

)

WSDA (1f

)

Table 27:

Audio ADC and DAC sampling frequency bits

FS1

FS0

Function

12.5 kHz to 25 kHz

25 kHz to 50 kHz (default)

50 kHz to 100 kHz

100 kHz to 200 kHz

Table 23:

Description of system register bits

...continued

Bit

Symbol

Description

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11.4 Audio ADC and DAC subsystem settings

Table 28:

Audio ADC and DAC subsystem register (address 01h) bit allocation

Bit

Symbol

PAB

PAA

MTB

MTA

AIF2

AIF1

AIF0

Reset

Access

read and write

Bit

Symbol

DAG

FIL

DVD

DIS1

DIS0

DIF2

DIF1

DIF0

Reset

Access

read and write

Table 29:

Description of the audio ADC and DAC subsystem register bit

Bit

Symbol

Description

ADC DC-filter. Bit DC enables the digital DC-filter of the ADC.

1 = DC-filtering is active (default)

0 = no DC-filtering

PAB

Polarity ADC 2 control. Bit PAB controls the ADC 2 polarity.

1 = polarity is inverted

0 = polarity is not-inverted (default)

PAA

Polarity ADC 1 control. Bit PAA controls the ADC 1 polarity.

1 = polarity is inverted

0 = polarity is not-inverted (default)

MTB

Mute ADC 2. Bit MTB enables the digital mute of ADC 2.

1 = ADC 2 is soft muted

0 = ADC 2 is not muted (default)

MTA

Mute ADC 1. Bit MTA enables the digital mute of ADC 1.

1 = ADC 1 is soft muted

0 = ADC 1 is not muted (default)

10 to 8

AIF[2:0]

ADC output data interface format. A 3-bit value to select the used data
format to the I

S-bus ADC output interface. Default 000. See

Table 30

DAG

DAC gain switch. Bit DAG selects the DAC gain.

1 = gain = 6 dB

0 = gain = 0 dB (default)

FIL

Filter selection. Bit FIL selects the interpolation filter characteristics.

1 = slow roll-off

0 = sharp roll-off (default)

DVD

192 kHz sampling mode selection. Bit DVD selects the oversampling rate
of the noise shaper.

1 = 64f

rate; used for 192 kHz and 176.4 kHz sampling frequencies

0 = 128f

rate (default)

4 to 3

DIS[1:0]

Data interface selection. A 2-bit value to select the data interface
connection. Default 00. See

Table 31

2 to 0

DIF[2:0]

DAC input data interface format. A 3-bit value to select the used data
format to the I

S-bus DAC input interface. Default 000. See

Table 30

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11.5 Voice ADC system settings

Table 30:

Data interface format bits

AIF2

AIF1

AIF0

Function

DIF2

DIF1

DIF0

S-bus format (default)

LSB-justified format, 16 bits

LSB-justified format, 20 bits

LSB-justified format, 24 bits

MSB-justified format

multichannel format, 20 bits

multichannel format, 24 bits (format 1)

multichannel format, 24 bits (format 2)

Table 31:

Data interface selection bits

DIS1

DIS0

Input to DAC

DATADA1 to DAC channel 1 and 2, DATADA2 to DAC channel 3
and 4, and DATADA3 to DAC channel 5 and 6 (default)

DATADA1 to DAC channels 1 to 6

DATADA2 to DAC channels 1 to 6

DATADA3 to DAC channels 1 to 6

Table 32:

Voice ADC system register (address 02h) bit allocation

Bit

Symbol

Reset

Access

read and write

Bit

Symbol

BCK1

BCK0

WSM

VH1

VH0

PVA

MTV

VIF

Reset

Access

read and write

Table 33:

Description of the voice ADC system register bits

Bit

Symbol

Description

15 to 8

default 0000 0000

7 to 6

BCK[1:0]

BCK frequency of voice ADC. A 2-bit value to select the BCK
frequency of the voice ADC in the WSV-out mode. Default 01.
See

Table 34

WSM

WSV mode selection. Bit WSM selects the WSV mode of the voice
ADC

1 = WSV-in mode (default)

0 = WSV-out mode

4 to 3

VH[1:0]

Voice ADC high-pass filter setting. A 2-bit value to enable the
high-pass filter of the voice ADC. Default 01. See

Table 35

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11.6 Status output register

Table 36:

Status output register (address 0Fh) bit allocation

Bit

Symbol

Reset

Access

read only

Bit

Symbol

AS1

AS0

DS2

DS1

DS0

Reset

Access

read only

Table 37:

Description of status output register bits

Bit

Symbol

Description

15 to 6

not used

Voice ADC status. Bit VS indicates the hard mute status of the voice ADC.

1 = power-down is ready and the clock may be disabled

0 = power-down is not ready and the clock should not be disabled

AS1

ADC 2 status. Bit AS1 indicates the hard mute status of ADC 2.

1 = power-down is ready and the clock may be disabled

0 = power-down is not ready and the clock should not be disabled

AS0

ADC 1 status. Bit AS0 indicates the hard mute status of ADC 1.

1 = power-down is ready and the clock may be disabled

0 = power-down is not ready and the clock should not be disabled

DS2

DAC channel 5 and 6 status. Bit DS2 indicates the hard mute status of DAC
channel 5 and 6.

1 = power-down is ready and the clock may be disabled

0 = power-down is not ready and the clock should not be disabled

DS1

DAC channel 3 and 4 status. Bit DS1 indicates the hard mute status of DAC
channel 3 and 4.

1 = power-down is ready and the clock may be disabled

0 = power-down is not ready and the clock should not be disabled

DS0

DAC channel 1 and 2 status. Bit DS0 indicates the hard mute status of DAC
channel 1 and 2.

1 = power-down is ready and the clock may be disabled

0 = power-down is not ready and the clock should not be disabled

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11.7 DAC channel selection

Table 38:

DAC channel select register (address 10h) bit allocation

Bit

Symbol

MIX1

MIX0

MC5

MC4

MC3

MC2

MC1

MC0

Reset

Access

read and write

Bit

Symbol

SEL1

SEL0

CS5

CS4

CS3

CS2

CS1

CS0

Reset

Access

read and write

Table 39:

Description of DAC channel select register bits

Bit

Symbol

Description

15 to 14

MIX[1:0]

DAC mixer setting. A 2-bit value to enable the DAC mixer. Default 00.
See

Table 40

13 to 8

MC[5:0]

DAC mixing channel selection. A group of 6 enable bits to make DAC
mixing channels ready for receiving feature settings through register
address 11h. Only selected registers accept new settings. Default 00 0000
(no channel ready). See

Table 41

7 and 6

SEL[1:0]

Feature selection. A 2-bit value to select the features to be set through
register address 11h. When the feature settings are written, only selected
feature settings are changed and non selected features are kept
unchanged. Default 00. See

Table 42

5 to 0

CS[5:0]

DAC channel selection. A group of 6 enable bits to make DAC channel
ready for receiving feature settings through register address 11h.
Default 00 0000 (no channel ready). See

Table 41

Table 40:

DAC mixer setting bits

MIX1

MIX0

Function

no mixing (default)

no mixing

mixing ADC 1

mixing ADC 2

Table 41:

DAC channel and mixing channel selection bits

MC5

MC4

MC3

MC2

MC1

MC0

Function

CS5

CS4

CS3

CS2

CS1

CS0

no channel ready (default)

channel 1 selected

channel 2 and channel 4 selected

all channels selected

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Multichannel audio coder-decoder

11.8 DAC features settings

Table 42:

Feature selection bits

SEL1

SEL0

Function

all features (default)

volume

mute and quick mute

de-emphasis, polarity and input channel selection

Table 43:

DAC features register (address 11h) bit allocation

Bit

Symbol

ICS1

ICS0

DE2

DE1

DE0

Reset

Access

read and write

Bit

Symbol

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

Reset

Access

read and write

Table 44:

Description of DAC features register bits

Bit

Symbol

Description

15 to 14

ICS[1:0]

Input channel selection. A 2-bit value to select the input channels. As
the controlled channels are paired off, this 2-bit value must be written
to each odd channel register. Default 00. See

Table 45

13 to 11

DE[2:0]

De-emphasis setting. A 3-bit value to enable the digital de-emphasis
filter. Default 000. See

Table 46

Polarity DAC control. Bit PD controls the DAC polarity.

1 = polarity is inverted

0 = polarity is not-inverted (default)

Muting. Bit MT enables the digital mute. All the DAC outputs are
muted at start-up. It is necessary to explicitly switch off for the audio
output by means of bit MT.

1 = muting (start-up)

0 = no muting (default)

Quick mute. Bit QM sets the quick mute mode.

1 = quick mute mode

0 = soft mute mode (default)

7 to 0

VC[7:0]

Interpolator volume control. An 8-bit value to program the volume
attenuation of each channel. The range is from 0 dB to

53 dB in steps

of 0.25 dB, from

53 dB to

80 dB in steps of 3 dB and

dB.

Default 0000 0000. See

Table 47

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Multichannel audio coder-decoder

Table 45:

Input channel selection bits

ICS1

ICS0

Input to DAC output

left channel input data to odd channel output; right channel input
data to even channel output

left channel input data to odd and even channel outputs

right channel input data to odd and even channel outputs

left channel input data to even channel output; right channel input
data to odd channel output

Table 46:

De-emphasis bits

DE2

DE1

DE0

Function

no de-emphasis (default)

de-emphasis of 32 kHz

de-emphasis of 44.1 kHz

de-emphasis of 48 kHz

de-emphasis of 96 kHz

not used

Table 47:

Interpolator volume control bits

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

Volume (dB)

0 (default)

0.25

0.50

0.75

1.00

1.25

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Multichannel audio coder-decoder

11.9 DAC channel 1 to channel 6 settings

All the DAC features which are written in register 11h are copied into the odd channel
registers.

All the DAC features which are written in register 11h are copied into the even channel
registers, except the bits ICS[1:0].

11.10 DAC mixing channel settings

All the DAC features which are written in register 11h are copied into the odd mixing
channel registers, except the bits DE[2:0].

Table 48:

DAC channel 1, 3 and 5 registers (address 12h, 14h and 16h) bit allocation

Bit

Symbol

ICS1

ICS0

DE2

DE1

DE0

Reset

Access

read and write

Bit

Symbol

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

Reset

Access

read and write

Table 49:

DAC channel 2, 4 and 6 registers (address 13h, 15h and 17h) bit allocation

Bit

Symbol

DE2

DE1

DE0

Reset

Access

read and write

Bit

Symbol

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

Reset

Access

read and write

Table 50:

DAC mixing channel 1, 3 and 5 registers (address 18h, 1Ah and 1Ch) bit
allocation

Bit

Symbol

ICS1

ICS0

Reset

Access

read and write

Bit

Symbol

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

Reset

Access

read and write

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UDA1384

Multichannel audio coder-decoder

All the DAC features which are written in register 11h are copied into the even channel
registers, except the bits ICS[1:0] and DE[2:0].

11.11 Audio ADC 1 and ADC 2 input amplifier gain settings

Table 51:

DAC mixing channel 2, 4 and 6 registers (address 19h, 1Bh and 1Dh) bit
allocation

Bit

Symbol

Reset

Access

read and write

Bit

Symbol

VC7

VC6

VC5

VC4

VC3

VC2

VC1

VC0

Reset

Access

read and write

Table 52:

Audio ADC input amplifier gain register (address 20h) bit allocation

Bit

Symbol

IB3

IB2

IB1

IB0

Reset

Access

read and write

Bit

Symbol

IA3

IA2

IA1

IA0

Reset

Access

read and write

Table 53:

Description of audio ADC input amplifier gain register bits

Bit

Symbol

Description

15 to 12

default 0000

11 to 8

IB[3:0]

Audio ADC 2 input amplifier gain. A 4-bit value to program the input
amplifier gain in steps of 3 dB (9 settings). Default 0000. See

Table 54

7 to 4

default 0000

3 to 0

IA[3:0]

Audio ADC 1 input amplifier gain. A 4-bit value to program the input
amplifier gain in steps of 3 dB (9 settings). Default 0000. See

Table 54

Table 54:

Audio ADC input amplifier gain bits

IA3

IA2

IA1

IA0

Gain (dB)

IB3

IB2

IB1

IB0

0 (default)

+12

+15

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Multichannel audio coder-decoder

11.12 Voice ADC gain settings

+18

+21

+24

Table 54:

Audio ADC input amplifier gain bits

...continued

IA3

IA2

IA1

IA0

Gain (dB)

IB3

IB2

IB1

IB0

Table 55:

Voice ADC input amplifier gain register (address 21h) bit allocation

Bit

Symbol

Reset

Access

read and write

Bit

Symbol

IV4

IV3

IV2

IV1

IV0

Reset

Access

read and write

Table 56:

Description of voice ADC input amplifier gain register bits

Bit

Symbol

Description

15 to 8

not used

7 to 5

default 000

4 to 0

IV[4:0]

Voice ADC input amplifier gain. A 5-bit value to program the voice
amplifier gain in steps of 1.5 dB (21 settings). Default 0 0000.
See

Table 57

Table 57:

Voice ADC input amplifier gain bits

IV4

IV3

IV2

IV1

IV0

Gain (dB)

0 (default)

+1.5

+4.5

+7.5

+28.5

+30

not used

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Multichannel audio coder-decoder

11.13 Supplemental settings 1

11.14 Supplemental settings 2

Table 58:

Supplemental settings 1 register (address 30h) bit allocation

Bit

Symbol

Reset

Access

read and write

Bit

Symbol

PDT

Reset

Access

read and write

Table 59:

Description of supplemental settings 1 register bits

Bit

Symbol

Description

15 to 8

default 0000 0000

PDT

Power down time. Bit PDT selects the time of the SDAC power-down
sequence.

1 = 1024/f

seconds

0 = 512/f

seconds (default)

6 to 0

default 000 0000

Table 60:

Supplemental settings 2 register (address 31h) bit allocation

Bit

Symbol

Reset

Access

read and write

Bit

Symbol

DITH2

DITH1

DITH0

VMTP

PDLNA

Reset

Access

read and write

Table 61:

Description of supplemental settings 2 register bits

Bit

Symbol

Description

15 to 7

default 0000 0000 0

6 to 4

DITH[2:0]

DAC dither control. A 3-bit value to control the dithering of the SDAC.
Default 000. See

Table 62

3 to 2

default 00

VMTP

Voice mute period control. Bit VMPT selects the voice ADC mute
period at power-up.

1 = mute for 1024 samples (1024/f

)

0 = mute for 2048 samples (2048/f

; default)

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Multichannel audio coder-decoder

12. Limiting values

[1]

All supply connections must be made to the same power supply.

[2]

ESD behavior is tested in accordance with JEDEC II standard:

a) Human Body Model (HBM); equivalent to discharging a 100 pF capacitor through a 1.5 k

series

resistor.

b) Machine Model (MM); equivalent to discharging a 200 pF capacitor through a 0.75

H series inductor.

13. Thermal characteristics

PDLNA

Power-down voice LNA. Bit PDLNA is to power-down the voice ADC
LNA. It should be noted that disabling the LNA requires a recovery
time defined by the external RC circuit.

1 = power-down

0 = power-on (default)

Table 62:

DAC dither control bits

DITH2

DITH1

DITH0

Function

DC dither (mid level); default

reserved

DC dither (low level)

DC plus AC dither (low level)

DC dither (high level)

DC plus AC dither (high level)

Table 61:

Description of supplemental settings 2 register bits

...continued

Bit

Symbol

Description

Table 63:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

supply voltage

[1]

4.0

xtal(max)

maximum crystal
temperature

150

stg

storage temperature

+125

amb

ambient temperature

+85

esd

electrostatic discharge
voltage

HBM

[2]

2000

+2000

[2]

200

+200

Table 64:

Thermal characteristics

Symbol

Parameter

Conditions

Typ

Unit

th(j-a)

thermal resistance from junction
to ambient

in free air

K/W

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Multichannel audio coder-decoder

14. Static characteristics

Table 65:

Characteristics

DDD

= V

DDA(AD)

= V

DDA(DA)

= 3.3 V; T

amb

= 25

C; R

= 22 k

; all voltages referenced to ground (pins V

); unless otherwise

specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supplies

DDA(AD)

ADC analog supply
voltage

[1]

2.7

3.3

3.6

DDA(DA)

DAC analog supply
voltage

[1]

2.7

3.3

3.6

DDD

digital supply voltage

[1]

2.7

3.3

3.6

DDA(AD)

ADC analog supply
current

ADC

= 48 kHz

ADC

= 96 kHz

DDA(DA)

DAC analog supply
current

DAC

= 48 kHz

DAC

= 96 kHz

DDD

digital supply current

ADC

= f

DAC

= 48 kHz;

VOICE

= 48 kHz

ADC

= f

DAC

= 96 kHz;

VOICE

= 48 kHz

DDD(pd)

digital supply current
in Power down-mode

audio and voice ADCs
power-down

DAC power-down

Digital input pins (5 V tolerant TTL compatible)

HIGH-level input
voltage

2.0

LOW-level input
voltage

0.8

input leakage current

input capacitance

Digital output pins

HIGH-level output
voltage

2 mA

0.85V

DDD

LOW-level output
voltage

= 2 mA

0.4

Analog-to-digital converter

ref

reference voltage on
pin V

ref

with respect to V

SSA(AD)

0.45V

DDA(AD)

0.5V

DDA(AD)

0.55V

DDA(AD)

ADCP

positive reference
voltage of ADC

DDA(AD)

ADCN

negative reference
voltage of ADC

0.0

output resistance on
pin V

ref

i(ADC)

input resistance of
audio ADC

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Multichannel audio coder-decoder

[1]

All supply connections must be made to the same power supply unit.

15. Dynamic characteristics

i(VADC)

input resistance of
voice ADC

Digital-to-analog converter

load resistance

output resistance

Table 65:

Characteristics

...continued

DDD

= V

DDA(AD)

= V

DDA(DA)

= 3.3 V; T

amb

= 25

C; R

= 22 k

; all voltages referenced to ground (pins V

); unless otherwise

specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 66:

Characteristics

DDD

= V

DDA(AD)

= V

DDA(DA)

= 3.3 V; f

= 1 kHz; T

amb

= 25

C; R

= 22 k

; sampling frequency f

= 48 kHz; all voltages

referenced to ground (pins V

); unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Audio analog-to-digital converter

digital output level

at 0 dB setting; 900 mV input

[1] [2]

2.5

1.2

0.7

at 3 dB setting; 637 mV input

[2]

1.2

at 6 dB setting; 451 mV input

[2]

1.2

at 9 dB setting; 319 mV input

[2]

1.2

at 12 dB setting; 226 mV input

[2]

1.2

at 15 dB setting; 160 mV input

[2]

1.2

at 18 dB setting; 113 mV input

[2]

1.2

at 21 dB setting; 80 mV input

[2]

1.2

at 24 dB setting; 57 mV input

[2]

1.2

input voltage unbalance between
channels

0.1

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Multichannel audio coder-decoder

(THD + N)/S total harmonic

distortion-plus-noise to signal ratio

normal mode; at

1 dBFS

at 0 dB setting

at 3 dB setting

at 6 dB setting

at 9 dB setting

at 12 dB setting

at 15 dB setting

at 18 dB setting

at 21 dB setting

at 24 dB setting

normal mode; at

60 dBFS;

A-weighted

at 0 dB setting

at 3 dB setting

at 6 dB setting

at 9 dB setting

at 12 dB setting

at 15 dB setting

at 18 dB setting

at 21 dB setting

at 24 dB setting

S/N

signal-to-noise ratio

code = 0; A-weighted

channel separation

100

Voice analog-to-digital converter

i(rms)

input voltage (RMS value)

at 0 dBFS digital output; 2.2 k

source impedance

50.0

(THD + N)/S total harmonic

distortion-plus-noise to signal ratio

1 dBFS

20 dBFS

40 dBFS; A-weighted

S/N

signal-to-noise ratio

code = 0; A-weighted

Digital-to-analog converter

Differential mode

o(rms)

output voltage (RMS value)

at 0 dBFS digital input

1.9

2.0

2.1

output voltage unbalance between
channels

< 0.1

(THD + N)/S total harmonic

distortion-plus-noise to signal ratio

at 0 dBFS

20 dBFS

60 dBFS; A-weighted

S/N

signal-to-noise ratio

code = 0; A-weighted

100

110

channel separation

114

Table 66:

Characteristics

...continued

DDD

= V

DDA(AD)

= V

DDA(DA)

= 3.3 V; f

= 1 kHz; T

amb

= 25

C; R

= 22 k

; sampling frequency f

= 48 kHz; all voltages

referenced to ground (pins V

); unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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Multichannel audio coder-decoder

[1]

The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately 1 mA by using a series
resistor.

[2]

The input voltage to the ADC scales proportionally with the power supply voltage.

15.1 Timing

Single-ended mode

o(rms)

output voltage (RMS value)

at 0 dBFS digital input

1.0

output voltage unbalance between
channels

< 0.1

(THD + N)/S total harmonic

distortion-plus-noise to signal ratio

at 0 dBFS

20 dBFS

60 dBFS; A-weighted

S/N

signal-to-noise ratio

code = 0; A-weighted

105

channel separation

110

Table 66:

Characteristics

...continued

DDD

= V

DDA(AD)

= V

DDA(DA)

= 3.3 V; f

= 1 kHz; T

amb

= 25

C; R

= 22 k

; sampling frequency f

= 48 kHz; all voltages

referenced to ground (pins V

); unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 67:

Timing

DDD

= V

DDA(AD)

= V

DDA(AD)

= 2.7 V to 3.6 V; T

amb

C to +85

C; typical timing specified at sampling frequency

= 48 kHz; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

System clock (see

Figure 16

)

sys

system clock cycle time

sys

= 256f

[1]

780

sys

= 384f

[1]

520

sys

= 512f

[1]

390

sys

= 768f

[1]

260

CWL

system clock LOW time

sys

< 19.2 MHz

0.3T

sys

0.7T

sys

19.2 MHz

0.4T

sys

0.6T

sys

CWH

system clock HIGH time

sys

< 19.2 MHz

0.3T

sys

0.7T

sys

19.2 MHz

0.4T

sys

0.6T

sys

S-bus interface

Serial data of audio ADC and DAC (see

Figure 17

)

BCK

audio bit clock frequency

[2]

12.8

MHz

cy(BCK)

BCK cycle time

BCKH

bit clock HIGH time

BCKL

bit clock LOW time

rise time

fall time

su(WS)

word select set-up time

h(WS)

word select hold time

su(DATAI)

data input set-up time

h(DATAI)

data input hold time

h(DATAO)

data output hold time

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Multichannel audio coder-decoder

d(DATAO-BCK)

data output to bit clock delay

d(DATAO-WS)

data output to word select
delay

Serial data of voice ADC

BCKV

voice bit clock frequency

[2]

6.4

MHz

cy(BCKV)

BCKV cycle time

156

BCKVH

bit clock HIGH time

BCKVL

bit clock LOW time

rise time

fall time

su(WSV)

word select set-up time

h(WSV)

word select hold time

h(DATAV)

data output hold time

d(DATAV-BCKV)

data output to bit clock delay

d(DATAV-WSV)

data output to word select
delay

d(WSV-BCKV)

word select to bit clock delay WSV-out mode

+30

L3-bus interface (see

Figure 18

and

Figure 19

)

L3CLOCK timing

cy(CLK)L3

L3CLOCK frequency

2000

kHz

cy(CLK)L3

L3CLOCK cycle time

500

CLK(L3)H

L3CLOCK HIGH time

250

CLK(L3)L

L3CLOCK LOW time

250

L3MODE timing

su(L3)A

L3MODE set-up time in
address mode

190

h(L3)A

L3MODE hold time in
address mode

190

su(L3)D

L3MODE set-up time in data
transfer mode

190

h(L3)D

L3MODE hold time in data
transfer mode

190

stp(L3)

L3MODE stop time in data
transfer mode

190

L3DATA timing

su(L3)DA

L3DATA set-up time in data
transfer and address mode

190

h(L3)DA

L3DATA hold time in data
transfer and address mode

d(L3)R

L3DATA delay time for read
data

Table 67:

Timing

...continued

DDD

= V

DDA(AD)

= V

DDA(AD)

= 2.7 V to 3.6 V; T

amb

C to +85

C; typical timing specified at sampling frequency

= 48 kHz; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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Multichannel audio coder-decoder

[1]

The system clock should not exceed 58 MHz in any mode.

[2]

The bit clock frequency should not exceed 256 times the corresponding sampling frequency.

[3]

is the total capacitance for each bus line.

[4]

To be suppressed by the input filter.

dis(L3)R

L3DATA disable time for read
data

C-bus interface timing (see

Figure 20

)

SCL timing

SCL

SCL clock frequency

400

kHz

LOW

SCL LOW time

1.3

HIGH

SCL HIGH time

0.6

rise time SDA and SCL

[3]

20 + 0.1C

300

fall time SDA and SCL

[3]

20 + 0.1C

300

SDA timing

BUF

bus free time between STOP
and START condition

1.3

SU;STA

set-up time repeated START

0.6

HD;STA

hold time START condition

0.6

SU;DAT

data set-up time

100

HD;DAT

data hold time

SU;STO

set-up time STOP condition

0.6

pulse width of spikes

[4]

capacitive load for each bus
line

400

Table 67:

Timing

...continued

DDD

= V

DDA(AD)

= V

DDA(AD)

= 2.7 V to 3.6 V; T

amb

C to +85

C; typical timing specified at sampling frequency

= 48 kHz; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Fig 16. System clock timing

mgr984

sys

CWH

CWL

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18. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.
However, to be completely safe, it is desirable to take normal precautions appropriate to
handling integrated circuits.

19. Soldering

19.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of
soldering ICs can be found in our

Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.

19.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)
vary between 100 seconds and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215

C to 270

C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

below 225

C (SnPb process) or below 245

C (Pb-free process)

for all BGA, HTSSON..T and SSOP..T packages

for packages with a thickness

2.5 mm

for packages with a thickness < 2.5 mm and a volume

350 mm

so called

thick/large packages.

below 240

C (SnPb process) or below 260

C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm

so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

19.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically
developed.

If wave soldering is used the following conditions must be observed for optimal results:

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Multichannel audio coder-decoder

Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

For packages with leads on four sides, the footprint must be placed at a 45

angle to

the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250

or 265

C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.

19.4 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300

When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270

C and 320

19.5 Package related soldering information

[1]

For more detailed information on the BGA packages refer to the

(LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales office.

Table 68:

Suitability of surface mount IC packages for wave and reflow soldering methods

Package

[1]

Soldering method

Wave

Reflow

[2]

BGA, HTSSON..T

[3]

, LBGA, LFBGA, SQFP,

SSOP..T

[3]

, TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS

not suitable

[4]

suitable

PLCC

[5]

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

[5] [6]

suitable

SSOP, TSSOP, VSO, VSSOP

not recommended

[7]

suitable

CWQCCN..L

[8]

, PMFP

[9]

, WQCCN..L

[8]

not suitable

9397 750 14366

Product data sheet

Rev. 02 -- 17 January 2005

52 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

[2]

All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal or
external package cracks may occur due to vaporization of the moisture in them (the so called popcorn
effect). For details, refer to the Drypack information in the

Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3]

These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no
account be processed through more than one soldering cycle or subjected to infrared reflow soldering with
peak temperature exceeding 217

C measured in the atmosphere of the reflow oven. The package

body peak temperature must be kept as low as possible.

[4]

These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the
solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink
on the top side, the solder might be deposited on the heatsink surface.

[5]

If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6]

Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7]

Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger
than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8]

Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by
using a hot bar soldering process. The appropriate soldering profile can be provided on request.

[9]

Hot bar soldering or manual soldering is suitable for PMFP packages.

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

9397 750 14366

Product data sheet

Rev. 02 -- 17 January 2005

54 of 55

21. Data sheet status

[1]

Please consult the most recently issued data sheet before initiating or completing a design.

[2]

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

22. Definitions

Short-form specification -- The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.

Application information -- Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.

23. Disclaimers

Life support -- These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status `Production'),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.

24. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com

Level

Data sheet status

[1]

Product status

[2] [3]

Definition

Objective data

Development

This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.

Date of release: 17 January 2005

Document number: 9397 750 14366

Published in The Netherlands

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

25. Contents

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.2

Multiple format data interface . . . . . . . . . . . . . . 2

2.3

Digital sound processing. . . . . . . . . . . . . . . . . . 2

2.4

Advanced audio configuration . . . . . . . . . . . . . 2

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pinning information . . . . . . . . . . . . . . . . . . . . . . 5

7.1

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

7.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

Functional description . . . . . . . . . . . . . . . . . . . 7

8.1

System clock. . . . . . . . . . . . . . . . . . . . . . . . . . . 7

8.2

Audio analog-to-digital converter (audio ADC) . 8

8.3

Voice Analog-to-Digital Converter (voice ADC) 8

8.4

Decimation filter of audio ADC . . . . . . . . . . . . . 8

8.5

Decimation filter of voice ADC . . . . . . . . . . . . . 8

8.6

Interpolation filter of DAC . . . . . . . . . . . . . . . . . 9

8.7

Noise shaper of DAC . . . . . . . . . . . . . . . . . . . . 9

8.8

Digital mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

8.9

Audio digital-to-analog converters . . . . . . . . . 10

8.10

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 10

8.11

Audio digital interface . . . . . . . . . . . . . . . . . . . 11

8.12

Voice digital interface . . . . . . . . . . . . . . . . . . . 14

8.13

DSD mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

8.14

Microcontroller interface mode . . . . . . . . . . . . 15

L3-bus interface . . . . . . . . . . . . . . . . . . . . . . . . 15

9.1

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

9.2

Device addressing . . . . . . . . . . . . . . . . . . . . . 16

9.3

9.4

Data write mode . . . . . . . . . . . . . . . . . . . . . . . 18

9.5

Data read mode . . . . . . . . . . . . . . . . . . . . . . . 18

C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 19

10.1

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

10.2

Characteristics of the I

C-bus . . . . . . . . . . . . . 19

10.3

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

10.4

Byte transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 20

10.5

Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 20

10.6

Start and stop conditions . . . . . . . . . . . . . . . . 20

10.7

Acknowledgment . . . . . . . . . . . . . . . . . . . . . . 20

10.8

Device address . . . . . . . . . . . . . . . . . . . . . . . . 21

10.9

10.10

Write and read data . . . . . . . . . . . . . . . . . . . . 21

10.11

Write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

10.12

Read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Register mapping . . . . . . . . . . . . . . . . . . . . . . 23

11.1

Address mapping . . . . . . . . . . . . . . . . . . . . . . 23

11.2

11.3

System settings . . . . . . . . . . . . . . . . . . . . . . . 27

11.4

Audio ADC and DAC subsystem settings. . . . 29

11.5

Voice ADC system settings . . . . . . . . . . . . . . 30

11.6

Status output register . . . . . . . . . . . . . . . . . . . 32

11.7

DAC channel selection . . . . . . . . . . . . . . . . . . 33

11.8

DAC features settings. . . . . . . . . . . . . . . . . . . 34

11.9

DAC channel 1 to channel 6 settings . . . . . . . 36

11.10

DAC mixing channel settings . . . . . . . . . . . . . 36

11.11

Audio ADC 1 and ADC 2 input amplifier gain
settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

11.12

Voice ADC gain settings. . . . . . . . . . . . . . . . . 38

11.13

Supplemental settings 1. . . . . . . . . . . . . . . . . 39

11.14

Supplemental settings 2. . . . . . . . . . . . . . . . . 39

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 40

Thermal characteristics . . . . . . . . . . . . . . . . . 40

Static characteristics . . . . . . . . . . . . . . . . . . . 41

Dynamic characteristics . . . . . . . . . . . . . . . . . 42

15.1

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Test information. . . . . . . . . . . . . . . . . . . . . . . . 48

16.1

Quality information . . . . . . . . . . . . . . . . . . . . . 48

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 49

Handling information . . . . . . . . . . . . . . . . . . . 50

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

19.1

Introduction to soldering surface mount packages
50

19.2

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 50

19.3

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 50

19.4

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 51

19.5

Package related soldering information . . . . . . 51

Revision history . . . . . . . . . . . . . . . . . . . . . . . 53

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 54

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Contact information . . . . . . . . . . . . . . . . . . . . 54

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UDA1384H

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UDA1384H