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Электронный компонент: UMA1002H

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DATA SHEET
Product specification
Supersedes data of 1996 Sep 13
File under Integrated Circuits, IC17
1997 Jan 28
INTEGRATED CIRCUITS
UMA1002
Data processor for cellular radio
(DPROC2)
1997 Jan 28
2
Philips Semiconductors
Product specification
Data processor for cellular radio
(DPROC2)
UMA1002
FEATURES
Single chip solution to all the data handling and
supervisory functions
Configuration to both AMPS and TACS
Additional JTACS option
I
2
C-bus serial control
All analog interface and filtering functions fully
implemented on chip
Error handling in hardware reduces software
requirements
Robust SAT decoding and transponding circuitry
Low current consumption by on-chip power-down
modes
Reduced system current consumption by new
integrated power-saving features
Majority voting includes more intelligence
On-chip control filler word filter
BCH error filter
Possibility to program ESCC bits
Small physical size: SO28 or LQFP32
External peripheral component count reduced
On-chip selectable clock divider
Integrated pull-up resistor at TXLINE
Simplified reset and abort software routines possible
The SO28 version is fully compatible with UMA1000LT
and UMF1000T.
GENERAL DESCRIPTION
The UMA1002 is a low power CMOS LSI device
incorporating the data transceiving, data processing, and
SAT functions (including on-chip filtering) for an AMPS or
TACS hand-held portable cellular radio telephone.
In this data sheet, the UMA1002 is often referred to by the
descriptive term `DPROC2'.
QUICK REFERENCE DATA
ORDERING INFORMATION
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
V
DD
supply voltage
2.7
3.0
5.5
V
I
DD
supply current normal operation with external clock
-
1.3
1.8
mA
T
amb
operating ambient temperature
-
30
-
+70
C
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
UMA1002T
SO28
plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
UMA1002H
LQFP32
plastic low profile quad flat package; 32 leads; body 7
7
1.4 mm
SOT358-1
1997
Jan
28
3
Philips Semiconductors
Product specification
Data processor for cellular radio
(DPROC2)
UMA1002
BLOCK DIAGRAM
b
ook, full pagewidth
MBD827
CLOCK
FILTER
OUTPUT
FILTER
TEST
LOGIC
RESET, CLOCK AND
POWER-DOWN
GENERATOR
6
(2)
4
(32)
12 (10)
(20)
9
(7)
22
(22)
13 (11)
ST
GENERATOR
MANCHESTER
AND BCH
ENCODING
I C
INTERFACE
TRANSMIT
BUFFER
SAT
REGENERATION
GATED D/A
GATED D/A
SAT
DETERMINATION
BIAS
GENERATOR
ANTI-
ALIASING
FILTER
3
(31)
1 (29)
(6)
21 (21)
23
(23)
25 (25)
24 (24)
18 (16)
15 (13)
17 (15)
11 (9)
SAT
FILTER
INTERPOLATOR
SAT
RECOVERY
COMPARATOR 2
COMPARATOR 1
DATA
RECOVERY
ARBITRATION
LOGIC
20 (19)
SYNCRONIZATION
AND VOTING
DOTTING
DETECTOR
ERROR
CORECTION
19 (17)
27 (26)
5 (1)
8 (5)
(3)
10 (8)
7 (4)
28 (27)
(28)
TST TSCAN
VDDA
VDDD
INVRX
RECDATA
MVO
RXLINE
RXCLK
BUSY/VSAT
RACTRL
TXCTRL
TACTRL
TXCLK
TXHOLD
TXLINE
SCL
SDA
A0
INVTX
JTACS
VSSA
14 (12)
VSSD
CLKOUT
CLKIN
CLKSEL
RESET
DATA
AGND
2 (30)
DEMODD
UMA1002
2
Fig.1 Block diagram.
Pins in parenthesis apply to UMA1002H in LQFP32.
1997 Jan 28
4
Philips Semiconductors
Product specification
Data processor for cellular radio
(DPROC2)
UMA1002
PINNING
SYMBOL
PIN
DESCRIPTION
SO28
LQFP32
V
SSA
1
29
Negative analog supply (0 V). To be connected low-ohmic to V
SSD
.
AGND
2
30
Internally generated analog signal ground. Voltage level =
1
/
2
V
DDA
. This pin should
be connected to a blocking capacitor, no DC load allowed.
DEMODD
3
31
DEMODD inputs analog data and SAT signals from the RF demodulator. This pin
should normally be AC-coupled. See Chapter "AC characteristics".
DATA
4
32
Data is an analog output which provides the Manchester encoded and filtered data
signal, SAT and signalling tone. This signal should normally be AC-coupled into the
Audio/Data summer. See Chapter "AC characteristics".
RACTRL
5
1
Received audio control output. Open-drain output used to blank the audio path to
the earpiece when a sequence of dotting followed by a synchronization word or 2
synchronization words separated by 77 bits is detected. RACTRL and TACTRL
functions can be combined using one line. Output level LOW means audio muted.
RESET
6
2
Master reset input resetting all internal flip-flops to the specified state. This input
has no influence on analog parts, but must be controlled by an active HIGH
microcontroller port.
INVRX
7
4
This input inverts the sense of received data stream, which allows RF
demodulators with high or low local oscillators to be used. The AMPS and TACS
specifications define NRZ encoded logic 1 as a LOW-to-HIGH transition in the
centre of a data bit period. The polarity of the demodulated data stream into
DPROC2 depends on the receiver local oscillator. Input LOW means data normal.
RXLINE
8
5
Received data signal output to the system controller.
TST
9
7
Test input pin (note 1).
RECDATA
10
8
Output of the recovered digital data signal (note 1).
TACTRL
11
9
Transmitter audio control output. This open-drain output is used to blank the audio
path and enable the data path to the modulator during data bursts on the RVC.
Output level LOW means audio muted.
CLKIN
12
10
1.2 MHz or 9.6 MHz external master clock input. This input signal should be
accurate to 100
10
-
6
and have a worst case 60 : 40 mark-space ratio.
CLKOUT
13
11
Output of 1.2 MHz clock signal (for APROC) derived from CLKIN.
V
SSD
14
12
Negative digital supply (0 V), internally connected to substrate. To be connected
low-ohmic to V
SSA
.
TXLINE
15
13
Open-drain bidirectional data line to the system controller (internal 100 k
pull-up).
n.c.
16
14
Not connected.
TXHOLD
17
15
This input holds off transmission of data when set to HIGH.
TXCLK
18
16
Transmitted data clock input from the system controller.
BUSY/VSAT
19
17
Output indicating the status of the RECC by providing output information based on
a majority decision on the last 3 consecutive Busy/Idle bits (FVC = logic 0). Output
level LOW means channel idle.
Indicating the result of the comparison of the measured SAT and the expected SAT
colour-code bits (I
2
C-bus register) in the voice channel mode (FVC = logic 1 and
ENSM = logic 1). Output level LOW means incoming SAT not equal to expected
SAT.
1997 Jan 28
5
Philips Semiconductors
Product specification
Data processor for cellular radio
(DPROC2)
UMA1002
Note
1. Must not be connected in existing applications.
TXCTRL
20
19
Transmitter control open-drain output used to disable the transmitter during an
RECC access failure. Output level LOW means RF disabled.
INVTX
21
21
This input inverts the sense of transmitted data stream, which allows RF
modulators with high or low local oscillators to be used. The AMPS and TACS
specifications define NRZ encoded logic 1 as a LOW-to-HIGH transition in the
centre of a data bit period. The polarity of the modulated data stream depends on
the transmitter local oscillator. Input LOW means data inverted.
TSCAN
22
22
Test switch input, only enabled if TST = logic 1, but should have a defined state.
A0
23
23
Input to select the least significant bit of the I
2
C-bus address.
SDA
24
24
Serial data input/output (I
2
C-bus).
SCL
25
25
Serial clock input (I
2
C-bus).
n.c.
26
18
Not connected.
RXCLK
27
26
Received data clock input from the system controller.
V
DDD
28
27
Digital supply voltage (+3 V).
V
DDA
-
28
Analog supply voltage (+3 V).
MVO
-
3
Majority voting output indicating that on FOCC the first 3 received words do not
differ from each other and thus the majority decision over 5 words can already be
carried out. Because of the required speed, indication is at this pin (and not via the
I
2
C-bus) which can be monitored by the system controller. Output LOW means the
receiver can be switched off.
JTACS
-
6
Digital input signal for JTACS, input HIGH means that data is routed from TXLINE
directly without processing to gated D/A converter (if enabled by STEN bit).
CLKSEL
-
20
Input switch for internal divide-by-8 or divide-by-1 divider between CLKIN and
CLKOUT (internal pull-down
divide-by-1 is default if not bonded out in SO28
package).
SYMBOL
PIN
DESCRIPTION
SO28
LQFP32