Philips Semiconductors
Preliminary specification
XA-H4
Single-chip 16-bit microcontroller
2
1999 Sep 24
DESCRIPTION
The powerful 16-bit XA CPU core and rich feature set make the
XA-H3 and XA-H4 devices ideal for high-performance real-time
applications such as industrial control and networking. By supporting
of up to 32 MB of external memory, these devices provide a low-cost
solution to embedded applications of any complexity. Features like
DMA, memory controller and four advanced USARTs help solve I/O
intensive tasks with a minimum of CPU load.
The XA-H3 feature set is a subset of the XA-H4 (see Table 1). The
XA-H3/H4 devices are members of the Philips XA (eXtended
Architecture) family of high performance 16-bit microcontrollers.
The XA-H3 and XA-H4 are designed to significantly minimize the
need for external components.
FEATURES
Large Memory Support
De-multiplexed Address/Data Bus
Six Programmable Chip Selects
Support for Unified Memory allows easy user modification of
all code
External ISP Flash support for easy code download
Dynamic Bus Sizing each of 6 Chip Selects can be programmed
for 8-bit or 16-bit bus.
Dynamic Bus Timing each of 6 chip selects has individual
programmable bus timing.
32 Programmable General Purpose I/O Pins
Four USARTs with 230.4 kbps capability
Eight DMA Channels
ADDITIONAL XA-H4 FEATURES (NOT AVAILABLE ON XA-H3)
Complete DRAM controller supports up to four banks of 8 MB each
Memory controller supports 16 MB in Unified Mode
Memory controller supports 32 MB in Harvard Mode
Serial ports are USARTs
Synchronous capability up to 1 Mbps, and include
HDLC/SDLC support
Four Match Characters are supported on each USART in
Async Mode
Hardware Autobaud on all four USARTs in Async Mode
USARTs are improved 85C30 style
Philips Semiconductors
Preliminary specification
XA-H4
Single-chip 16-bit microcontroller
1999 Sep 24
3
Table 1. XA-H3 and XA-H4 features comparison
Feature
XA-H3
XA-H4
Maximum External Memory
(Harvard Memory Mode)
6 MB
32 MB
(16 MB Code, 16 MB Data)
Maximum External Memory
(Unified Memory Mode)
6 MB
16 MB
Memory Controller supports both Harvard and Unified architectures
Yes
Yes
De-multiplexed Address/Data Bus
Yes
Yes
DRAM Controller
No
Yes
DMA Channels
8
8
Dynamic Bus Sizing
Yes
Yes
Dynamic Bus Timing
Yes
Yes
Programmable Chip Selects
6
6
General Purpose IO Pins
33
33
Potential Interrupt Pins
16
16
Interrupts (programmable priority)
7 Standard SW
4 High Priority SW
9 Hardware Event
7 Standard SW
4 High Priority SW
9 Hardware Event
Two Counter/Timers plus Watchdog
Yes
Yes
Baud Rate Generators
1
4
4
Serial Ports
4 UARTs
4 USARTs
Maximum Serial Data Rates
asynch to 230.4 kbps (no sync)
asynch to 230.4 kbps
sync to 1 Mbps
Match Characters
No
4 async chars per USART
Hardware Autobaud
No
up to 230.4 kbps
NOTE:
1. Can be used as additional counters if not needed as BRGs.
ORDERING INFORMATION
ROMless Only
Temperature range
C and Package
Freq (MHz)
Package Drawing Number
H4 = PXAH40KFBE
40 to +85
C, 100-Pin Low Profile Quad Flat Package (LQFP)
30
SOT407-1
NOTE
K=30 MHz, F = (40 to +85), BE = LQFP
Philips Semiconductors
Preliminary specification
XA-H4
Single-chip 16-bit microcontroller
1999 Sep 24
4
PIN CONFIGURATION
SU01269
XA-H4
Top View 100 Pin LQFP
Base Part Number PXAH4
Current Part = PXAH40KFBE
K = 30 MHz, F = 40 to +85
C, BE = LQFP pkg
LQFP Package = SOT407-1
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VSS
VDD
A0
A1
A2
A3
A4
A5
A6
A7 (A21_22)
A8 (A19_A20)
A9 (A0_A18)
A10 (A1)
A11 (A2)
A12 (A3)
A13 (A4)
A14 (A5)
A15 (A6_A22)
VSS
VDD
A16 (A7_A20_A21)
A17 (A8_A18_A19)
A18
A19
D0
WE
CS0
CS1_RAS1
CS2_RAS2
CS3_RAS3
ClkOut
VSS
VDD
D15
D14
D13
D12
D1
1
D10
D9
D8
D7
D6
D5
D4
D3
VDD
VSS
D2
D1
VSS
VDD
CD1_Int2
Int0
P2.0_RxD3
P2.1_TxD3
P2.2_R
TClk3
P2.3_ComClk_TRClk3
P2.4_CD3
P2.5_CTS3
P2.6_R
TS3
P2.7_Sync3_BRG3
VSS
VDD
P0.0_Sync0_BRG0
P0.1_R
TS0
P0.2_CTS0
P0.3_CD0
P0.4_TRClk0
P0.5_R
TClk0
TxD0
RxD0
GPOut
P0.6
P0.7
P1.7_BRG2_Sync2
P1.6_RTS2
P1.5_CTS2
P1.4_CD2
P1.3_TRClk2
P1.2_RTClk2
P1.1_TxD2
P1.0_RxD2
P3.7_Int1_TRClk1
P3.6_TxD1
P3.5_RxD1
P3.4_CTS1
P3.3_Timer1_BRG1_Sync1
VDD
XTALOUT
XTALIN
VSS
P3.2_Timer0_ResetOut
P3.0_CS4_RAS4_RTClk1
Reset_In
BLE_CASL
BHE_CASH
WAIT_Size16
OE
P3.1_CS5_RAS5_RTS1
DRAM CAS bits
NOTE: Address lines output during
various DRAM CAS cycles are shown
in parenthesis. See DRAM Controller
chapter in User Manual for details.
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