PLL502-30
750kHz 800MHz Low Phase Noise VCXO (for 12 25MHz Crystals)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/20/06 Page 1
FEATURES
750kHz to 800MHz output range.
Low phase noise output (@ 10kHz frequency
offset, -142dBc/Hz for 19.44MHz, -125dBc/Hz for
155.52MHz, -115dBc/Hz for 622.08MHz).
Selectable CMOS, PECL and LVDS output.
Selectable High Drive or Standard CMOS.
12 to 25MHz crystal input.
No external load capacitor or varicap required.
Output Enable selector.
Wide pull range (+/-200ppm)
3.3V operation.
Available in DIE (65 mil x 62 mil).
DESCRIPTION
The PLL502-30 is a monolithic low jitter and low
phase noise (-142dBc/Hz @ 10kHz offset) VCXO IC
Die, with CMOS, LVDS and PECL output, covering
the 750kHz to 800MHz output range. It allows the
control of the output frequency with an input voltage
(VCON), using a low cost crystal.
The same die can be used as a VCXO with output
frequencies ranging from F
XIN
/ 16 to F
XIN
x 32
thanks to frequency selector pads. This makes the
PLL502-30 ideal as a universal die for applications
ranging from ADSL to SONET.
DIE SPECIFICATIONS
Name Value
Size
62 x 65 mil
Reverse side
GND
Pad dimensions
80 micron x 80 micron
Thickness 10
mil
BLOCK DIAGRAM
DIE CONFIGURATION
OUTPUT SELECTION AND ENABLE
OUTSEL1
(Pad #18)
OUTSEL0
(Pad #25)
Selected Output
0
0
High Drive CMOS
0 1
Standard
CMOS
1 0
PECL
1 1
LVDS
OE_SELECT
(Pad #9)
OE_CTRL
(Pad #30)
State
0
(Default)
Output enabled
0
1 Tri-state
0 Tri-state
1 (Default)
1
(Default)
Output enabled
Pad #9: Bond to GND to set to "0", bond to VDD to set to "1"
Pad #30: Logical states defined by PECL levels if OE_SELECT is "0"
Logical states defined by CMOS levels if OE_SELECT is "1"
18
19
20
21
23
25
7
13
10
26
29
31
Y
X
(0,0)
(1550,1475)
62 m
i
l
65 mil
24
22
17
16
15
14
12
11
9
8
6
1
2
3
4
5
27
28
30
GN
D
GND
B
U
F
GN
D
GN
D
GN
D
GN
D
GN
D
N/
C
OE_SEL^
GNDBUF
CMOS
LVDSB
PECLB
VDDBUF
VDDBUF
PECL
LVDS
O
U
T
SEL1^
SEL0
^
SEL1
^
VDD
VDD
VDD
VDD
O
U
T
SEL0^
XIN
XOUT
SEL2^
SEL3^
OE_CTRL
VCON
Die ID:
A0505-18
C502A
Note: ^ denotes internal pull up
Reference
Divider
Phase
Detector
Charge
Pump
Loop
Filter
VCO
VCO
Divider
XTAL
OSC
CLKBAR
OE
XIN
XOUT
CLK
VCON
VARICAP
+
SEL
PLL502-30
750kHz 800MHz Low Phase Noise VCXO (for 12 25MHz Crystals)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/20/06 Page 2
FREQUENCY SELECTION TABLE
SEL3
(Pad #28)
SEL2
(Pad #29)
SEL1
(Pad #19)
SEL0
(Pad #20)
Selected Multiplier
0 0 0 0
Reserved
0 0 0 1
Reserved
0 0 1 0
Reserved
0
0
1
1
Fin x 32
0 1 0 0
Reserved
0 1 0 1
Reserved
0 1 1 0
Fin
/
8
0
1
1
1
Fin x 2
1 0 0 0
Reserved
1 0 0 1
Fin
/
2
1 0 1 0
Fin
/
16
1
0
1
1
Fin x 4
1 1 0 0
Fin
/
4
1
1
0
1
Fin x 8
1
1
1
0
Fin x 16
1 1 1 1
No
multiplication
All pads have internal pull-ups (default value is 1). Bond to GND to set to 0.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
V
DD
4.6 V
Input Voltage, dc
V
I
-0.5
V
DD
+0.5 V
Output Voltage, dc
V
O
-0.5
V
DD
+0.5 V
Storage Temperature
T
S
-65 150
C
Ambient Operating Temperature*
T
A
-40 85
C
Junction Temperature
T
J
125
C
Lead Temperature (soldering, 10s)
260
C
ESD Protection, Human Body Model
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
PLL502-30
750kHz 800MHz Low Phase Noise VCXO (for 12 25MHz Crystals)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/20/06 Page 3
2. Crystal Specifications
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
Crystal Resonator Frequency
F
XIN
Parallel Fundamental Mode
12
25
MHz
Crystal Loading Rating
C
L (xtal)
at VCON = 1.65V
9.5
pF
Crystal Pullability
C
0
/C
1 (xtal)
AT
cut
250
-
Recommended ESR
R
E
AT cut
30
Note: Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at
nominal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This
however may reduce the pull range.
3. Voltage Control Crystal Oscillator
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
VCXO Stabilization Time *
T
VCXOSTB
From power valid
10 ms
VCXO Tuning Range
F
XIN
= 12 25MHz;
XTAL C
0
/C
1
< 250
0V
VCON 3.3V
500 ppm
CLK output pullability
VCON=1.65V,
1.65V
200
ppm
VCXO Tuning Characteristic
150
ppm/V
Pull range linearity
10
%
VCON pin input impedance
2000
k
VCON modulation BW
0V
VCON 3.3V, -3dB
25
kHz
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications
PARAMETERS SYMBOL
CONDITIONS
MIN. TYP. MAX. UNITS
Fout<24MHz
60/28/15
24MHz<Fout<96MHz
65/45/30
Supply Current,
Dynamic (with
Loaded Outputs)
I
DD
PECL/LVDS/CMOS
96MHz<Fout<700MHz 100/80/40
mA
Operating Voltage
V
DD
2.97 3.63 V
Output Clock
Duty Cycle
@ 50% V
DD
(CMOS)
@ 1.25V (LVDS)
@ V
DD
1.3V (PECL)
45
45
45
50
50
50
55
55
55
%
Short Circuit
Current
50
mA
PLL502-30
750kHz 800MHz Low Phase Noise VCXO (for 12 25MHz Crystals)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/20/06 Page 4
5. Jitter Specifications
PARAMETERS CONDITIONS
FREQUENCY MIN. TYP. MAX. UNITS
19.44MHz 2.2
77.76MHz 3.5
155.52MHz 4.3
Period jitter RMS
1
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
622.08MHz 5.0
ps
19.44MHz 17
77.76MHz 25
155.52MHz 27
Period jitter Peak-to-
Peak
1
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
622.08MHz 35
ps
155.52MHz 2.6 4
Integrated jitter RMS
2
Integrated 12 kHz to 20 MHz
622.08MHz 2.5 4
ps
6. Phase Noise Specifications
PARAMETERS FREQUENCY @10Hz
@100Hz @1kHz @10kHz @100kHz UNITS
19.44MHz -80 -108
-132
-142
-150
77.76MHz -72 -103
-122
-130
-125
155.52MHz -65 -95
-120
-125
-121
Phase Noise
2
relative
to carrier
(typical)
622.08MHz -55 -85
-109
-115
-110
dBc/Hz
Note: Phase Noise measured at VCON = 0V
7. CMOS Electrical Characteristics
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
I
OH
V
OH
= V
DD
-0.4V, V
DD
=3.3V 30 mA
Output drive current
(High Drive)
I
OL
V
OL
= 0.4V, V
DD
= 3.3V
30
mA
I
OH
V
OH
= V
DD
-0.4V, V
DD
=3.3V 10 mA
Output drive current
(Standard Drive)
I
OL
V
OL
= 0.4V, V
DD
= 3.3V
10
mA
Output Clock Rise/Fall Time
(Standard Drive)
0.3V ~ 3.0V with 15 pF load
2.4
Output Clock Rise/Fall Time
(High Drive)
0.3V ~ 3.0V with 15 pF load
1.2
ns
PLL502-30
750kHz 800MHz Low Phase Noise VCXO (for 12 25MHz Crystals)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/20/06 Page 5
8. LVDS Electrical Characteristics
PARAMETERS SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Output Differential Voltage
V
OD
247
355
454
mV
V
DD
Magnitude Change
V
OD
-50
50 mV
Output High Voltage
V
OH
1.4
1.6
V
Output Low Voltage
V
OL
0.9
1.1
V
Offset Voltage
V
OS
1.125
1.2
1.375
V
Offset Magnitude Change
V
OS
R
L
= 100
(see figure)
0
3 25 mV
Power-off Leakage
I
OXD
V
out
= V
DD
or GND
V
DD
= 0V
1
10
uA
Output Short Circuit Current
I
OSD
-5.7 -8
mA
9. LVDS Switching Characteristics
PARAMETERS SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Differential Clock Rise Time
t
r
0.2 0.7 1.0 ns
Differential Clock Fall Time
t
f
R
L
= 100
C
L
= 10 pF
(see figure)
0.2 0.7 1.0 ns
OUT
OUT
V
OD
V
OS
50
50
OUT
V
DIFF
R
L
= 100
C
L
= 10pF
C
L
= 10pF
LVDS Switching Test Circuit
LVDS Levels Test Circuit
LVDS Transistion Time Waveform
OUT
OUT
OUT
0V (Differential)
0V
20%
80%
20%
80%
t
R
t
F
V
DIFF
PLL502-30
750kHz 800MHz Low Phase Noise VCXO (for 12 25MHz Crystals)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/20/06 Page 6
10. PECL Electrical Characteristics
PARAMETERS SYMBOL CONDITIONS
MIN. MAX.
UNITS
Output High Voltage
V
OH
V
DD
1.025
V
Output Low Voltage
V
OL
R
L
= 50
to (V
DD
2V)
(see figure)
V
DD
1.620
V
11. PECL Switching Characteristics
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
Clock Rise Time
t
r
@20/80% - PECL
0.6
1.5
ns
Clock Fall Time
t
f
@80/20% - PECL
0.5
1.5
ns
OUT
OUT
50
50
PECL Levels Test Circuit
PECL Transistion Time Waveform
OUT
OUT
50%
20%
80%
t
R
t
F
VDD
DUTY CYCLE
45 - 55%
55 - 45%
50%
OUT
OUT
t
SKEW
PECL Output Skew
2.0V
PLL502-30
750kHz 800MHz Low Phase Noise VCXO (for 12 25MHz Crystals)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/20/06 Page 7
PAD ASSIGNMENT
Pad #
Name
X (
m) Y
(
m)
Description
1 GND
248
109
Ground.
2 GND
361
109
Ground.
3 GND
473
109
Ground.
4 GND
587
109
Ground.
5 GND
702
109
Ground.
6 N/C
874
109
No
Connection.
7 GND
1042
109
Ground.
8
GNDBUF
1171
109
Ground, buffer circuitry.
9 OE_SELECT
1400
125
Used to select between PECL or CMOS logic states for OE.
Internal pull up.
10 LVDS
1400
259
LVDS Output.
11 PECL
1400
476
PECL
Output.
12
VDDBUF
1400
616
3.3V power supply, Buffer circuitry.
13
VDDBUF
1400
716
3.3V power supply, Buffer circuitry.
14 PECLB
1400
871
Complementary PECL Output.
15
LVDSB
1400
1089
Complementary LVDS Output.
16 CMOS
1400
1227
CMOS
Output.
17 GNDBUF
1389
1365
Ground, buffer circuitry.
18 OUTSEL1
1232
1365
Used to select CMOS, PECL or LVDS output type. Internal pull
up.
19
SEL1
1042
1365
Used to select multiplication factor. Internal pull up.
20 SEL0 854
1365
Used to select multiplication factor. Internal pull up.
21 VDD 659
1365
3.3V
power
supply.
22 VDD 559
1365
3.3V
power
supply.
23 VDD 459
1365
3.3V
power
supply.
24 VDD 358
1365
3.3V power supply.
25 OUTSEL0 194
1365
Used to select CMOS, PECL or LVDS output type. Internal pull
up.
26
XIN
109
1223
Crystal input. See crystal specification page 3.
27 XOUT 109
1017
Crystal output. See crystal specification page 3.
28
SEL3
109
858
Used to select multiplication factor. Internal pull up.
29
SEL2
109
646
Used to select multiplication factor. Internal pull up.
30 OE_CTRL 109
397
Used to enable/disable the output(s). See Output Selection and
Enable table on page 1.
31 VCON 109
181
Voltage Control Input. 0V to 3.3V.
PLL502-30
750kHz 800MHz Low Phase Noise VCXO (for 12 25MHz Crystals)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/20/06 Page 8
ORDERING INFORMATION
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL502-30 D C
Order Number
Marking
Package Option
PLL502-30DC P502-30DC
Die (Waffle Pack)
PART NUMBER
TEMPERATURE
C=COMMERCIAL
I=INDUSTRAL
PACKAGE TYPE
D=DIE
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