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Электронный компонент: P520-19OC

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PLL520-17/-18/-19
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1
FEATURES
65MHz to 130MHz Fundamental Mode Crystal.
Output range: 65MHz 800MHz (selectable 1x,
2x, 4x and 8x multipliers).
Low Injection Power for crystal 50uW.
Available outputs: PECL, LVDS, or CMOS.
Integrated variable capacitors.
Supports 3.3V-Power Supply.
Available in 16 pin (TSSOP or SOIC)
DESCRIPTION
The PLL520-17/-18/-19 family of VCXO IC's is
specifically designed to pull high frequency
fundamental crystals. They achieve very low current
into the crystal resulting in better overall stability.
Their internal varicaps allow an on chip frequency
pulling, controlled by the VCON input.
BLOCK DIAGRAM
PIN CONFIGURATION
^: Internal pull-up
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
0 (Default) Output enabled
PLL520-18
1 Tri-state
0 Tri-state
PLL520-17
PLL520-19
1 (Default) Output enabled
OE input: Logical states defined by PECL levels for PLL520-18
Logical states defined by CMOS levels for PLL520-17/-19
XIN
XOUT
OE
Q
PLL520-17/-18/-19
VCON
Q
PLL by-pass
SEL
PLL
(Phase
Locked
Loop)
Oscillator
Amplifier
w/
integrated
varicaps
PLL 520-1x
1
2
3
4
5
6
7
8
VDD
9
10
11
12
13
14
15
16
XIN
XOUT
SEL3^
SEL2^
OE
VCON
GND
SEL0^
SEL1^
GND
CLKC
VDD
CLKT
GND
GND
PLL520-17/-18/-19
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2
PIN DESCRIPTIONS
Name Number
Type
Description
XIN
2
I
Crystal input. See Crystal Specification on page 3.
XOUT
3
I
Crystal output. See Crystal Specification on page 3.
OE
6
I
Output enable. See Output Enable Logic Levels on page 1.
VCON
7
I
Voltage control input.
GND
8,9, 10, 14
P
Ground.
CLKT 11 O
True output PECL (PLL520-18) or LVDS (PLL520-19).
No Connect for CMOS (PLL520-17).
CLKC 13 O
Complementary output PECL (PLL520-18) or LVDS (PLL520-19).
CMOS output for (PLL520-17).
SEL 4,5,15,16
I
Multiplier selector pins. These pins have an internal pull-up that will
default SEL to `1' when not connected to GND.
VDD
1, 12
P
+3.3V power supply.
FREQUENCY SELECTION TABLE
Pin #4
SEL3
Pin #5
SEL2
Pin #15
SEL1
Pin #16
SEL0
Selected Multiplier
0
0
1
1
Fin x 8
1
0
1
1
Fin x 4
1
1
1
0
Fin x 2
1 1 1 1
No
multiplication
All pins have internal pull-ups (default value is 1). Connect to GND to set to 0.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
V
DD
4.6 V
Input Voltage, dc
V
I
-0.5
V
DD
+0.5 V
Output Voltage, dc
V
O
-0.5
V
DD
+0.5 V
Storage Temperature
T
S
-65 150
C
Ambient Operating Temperature*
T
A
-40 85
C
Junction Temperature
T
J
125
C
Lead Temperature (soldering, 10s)
260
C
ESD Protection, Human Body Model
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
PLL520-17/-18/-19
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 3
2. Crystal Specifications
3. Voltage Control Crystal Oscillator
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
VCXO Stabilization Time *
T
VCXOSTB
From power valid
10
ms
VCXO Tuning Range
F
XIN
= 100 200MHz;
XTAL C
0
/C
1
< 250
0V
VCON 3.3V
200* ppm
CLK output pullability
VCON=1.65V,
1.65V
100*
ppm
On-chip Varicaps control range
VCON = 0 to 3.3V
4 18*
pF
Linearity
10*
%
VCXO Tuning Characteristic
65
ppm/V
VCON input impedance
60
k
VCON modulation BW
0V
VCON 3.3V, -3dB
25 kHz
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
Supply Current (Loaded
Outputs)
I
DD
PECL/LVDS/CMOS
100/80/40
mA
Operating Voltage
V
DD
2.97
3.63
V
Output Clock Duty Cycle
@ 1.4V (CMOS)
@ 1.25V (LVDS)
@ Vdd 1.3V (PECL)
45
45
45
50
50
50
55
55
55
%
Short Circuit Current
50
mA
PARAMETERS SYMBOL
CONDITIONS
MIN.
MAX.
UNITS
CX+
2
Built-in Capacitance
CX-
2
Inter-electrode capacitance
C
0
65MHz to 130MHz
(VDD=3.3V)
2
pF
C0/C1 ratio (gamma)
300
-
Oscillation Frequency
OF
Fund.
120
200
MHz
PLL520-17/-18/-19
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 4
5. Jitter Specifications
PARAMETERS CONDITIONS
MIN.
TYP.
MAX.
UNITS
77.76MHz
2.5
155.52MHz
4
Period jitter RMS
622.08MHz
5
ps
77.76MHz
24
155.52MHz
29
Period jitter peak-to-peak
622.08MHz
32
ps
Integrated 12 kHz to 20 MHz at 77.76MHz
0.5
Integrated 12 kHz to 20 MHz at 155.52MHz
1.5
Integrated jitter RMS
Integrated 12 kHz to 20 MHz at 622.08MHz
1.5
ps
6. Phase Noise Specifications
PARAMETERS FREQUENCY @10Hz
@100Hz @1kHz @10kHz @100kHz UNITS
77.76MHz -75 -95
-125
-145
-155
155.52MHz -75 -95
-120
-125
-123
Phase Noise relative
to carrier
622.08MHz -75 -95
-115
-118
-115
dBc/Hz
Note: Phase Noise measured at VCON = 0V
7. CMOS Output Electrical Specifications
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
I
OH
V
OH
= V
DD
-0.4V, V
DD
=3.3V 30 mA
Output drive current
(High Drive)
I
OL
V
OL
= 0.4V, V
DD
= 3.3V
30
mA
I
OH
V
OH
= V
DD
-0.4V, V
DD
=3.3V 10 mA
Output drive current
(Standard Drive)
I
OL
V
OL
= 0.4V, V
DD
= 3.3V
10
mA
Output Clock Rise/Fall Time
(Standard Drive)
0.3V ~ 3.0V with 15 pF load
2.4
Output Clock Rise/Fall Time
(High Drive)
0.3V ~ 3.0V with 15 pF load
1.2
ns
PLL520-17/-18/-19
Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 5
8. LVDS Electrical Characteristics
PARAMETERS SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Output Differential Voltage
V
OD
247
355
454
mV
V
DD
Magnitude Change
V
OD
-50 50 mV
Output High Voltage
V
OH
1.4
1.6
V
Output Low Voltage
V
OL
0.9
1.1
V
Offset Voltage
V
OS
1.125
1.2
1.375
V
Offset Magnitude Change
V
OS
R
L
= 100
(see figure)
0 3 25 mV
Power-off Leakage
I
OXD
V
out
= V
DD
or GND
V
DD
= 0V
1
10
uA
Output Short Circuit Current
I
OSD
-5.7 -8
mA
9. LVDS Switching Characteristics
PARAMETERS SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Differential Clock Rise Time
t
r
0.2 0.7 1.0 ns
Differential Clock Fall Time
t
f
R
L
= 100
C
L
= 10 pF
(see figure)
0.2 0.7 1.0 ns
OUT
OUT
V
OD
V
OS
50
50
OUT
V
DIFF
R
L
= 100
C
L
= 10pF
C
L
= 10pF
LVDS Switching Test Circuit
LVDS Levels Test Circuit
LVDS Transistion Time Waveform
OUT
OUT
OUT
0V (Differential)
0V
20%
80%
20%
80%
t
R
t
F
V
DIFF