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Электронный компонент: pl56047qi

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Analog Frequency Multiplier
VCXO Family of Products
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 02/10/05 Page 1
PRODUCT DESCRIPTION
PhaseLink's Analog Frequency Multiplier
TM
(AFMs)
are the industry's first `Balanced Oscillator' utilizing
analog multiplication of the fundamental frequency
(at double or quadruple frequency), combined with
an attenuation of the fundamental of the reference
crystal, without the use of a phase locked loop, in
CMOS technology.

PhaseLink's patent pending PL56X family of AFM
products can achieve up to 800 MHz output
frequency with practically no jitter or phase noise
deterioration. In addition, the low frequency input
crystal requirement makes the AFMs the most
affordable high performance timing source in the
market.

PL560-XX family of products utilize a low-power
CMOS technology and are housed in a 16-pin
(T)SSOP, and 16-pin 3x3 QFN.
FEATURES
Non Phase Locked Loop frequency multiplication
Input frequency from 30-200 MHz
Output frequency from 60-800-MHz
Low Phase noise and jitter (equivalent to fundamental
crystal at the output frequency)
Unbeatably low jitter
o RMS phase jitter < 0.25ps (12kHz-20MHz)
o RMS period jitter < 2.5 ps
Low Phase Noise
o -142 dBc/Hz @100kHz Offset from 155.52MHz
o -150 dBc/Hz @10MHz Offset from 155.52MHz
High linearity pull range (typ. 5%)
+/- 120 PPM pullability VCXO
Low input frequency eliminates the need for
expensive crystals
Differential output levels (PECL, LVDS), or single-
ended CMOS
Single 2.5V or 3.3V +/- 10% power supply
Optional industrial temperature range (-40C to
+85
C)
Available in 16-pin (T) SSOP, and 3x3 QFN
Figure 1: 2x AFM Phase Noise at 311.04MHz
Analog Frequency Multiplier
VCXO Family of Products
47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev.:03-22-05 Page 2
O s c illa to r
A m p lifie r
O E C T R L
Q
Q B A R
F re q u e n c y
X 2
X IN
X O U T
L 2 X
V C o n
F re q u e n c y
X 4
L 4 X
O n ly re q u ire d in x 4 d e s ig n s
Figure 2: Overall VCXO AFM Block Diagram

Figure 3 shows the jitter histogram of the 2x Analog Frequency Multiplier at 155.52MHz, while figure 4 shows the very low
rejection levels of sub-harmonics that correspond to the exceptionally low jitter performance.
Figure 3: Jitter Histogram at 311.04 MHz Figure 4: Spectrum Analysis at 311.04 MHz
Analog Frequency Multiplier (2x)
Analog Frequency Multiplier (2x)
with 155.52MHz crystal
with sub-harmonic below 72 dBc
OE LOGIC SELECTION
OUTPUT OESEL OE Output
State
0 (Default)
Enabled
0 (Default)
1 Tri-state
0 Tri-state
PECL
1
1 (Default)
Enabled
0 Tri-state
0 (Default)
1 (Default)
Enabled
0 (Default)
Enabled
LVDS or CMOS
1
1 Tri-state
OESEL and OE: Connect to VDD to set to "1", connect to GND to set to "0". Internally set to default through pull-down / -up.
Analog Frequency Multiplier
VCXO Family of Products
47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev.:03-22-05 Page 3

PRODUCT SELECTION GUIDE


FREQUENCY VERSUS PHASE NOISE PERFORMANCE

Phase Noise AT Frequency Offset From Carrier (dBc/Hz)
Part
Number
Input
Frequency
Range (MHz)
Analog
Frequency
Multiplication
Factor
Output
Frequency
Range (MHz)
Output
Type
Carrier
Freq.
(MHz)
10 Hz
100 Hz
1 KHz
10
KHz
100
KHz
1 MHz
10
MHz
PL560-08
75 - 200
4
300 - 800
PECL
622.08
-55
-85 -110 -130 -137 -148 -150
PL560-09
75 - 200
4
300 - 800
LVDS
622.08
-55
-85
-110
-130
-137
-148
-150
PL560-37
30 - 80
4
120 - 320
CMOS
155.52
-50 -82 -110 -128 -142 -148 -150
PL560-38
30 - 80
4
120 - 320
PECL
155.52
-50
-82
-110
-128
-142
-148
-150
PL560-39
30 - 80
4
120 - 320
LVDS
155.52
-50 -82 -110 -128 -142 -148 -150
PL560-47
30 - 80
2
60 - 160
CMOS
155.52
-65
-95
-122
-138
-142
-148
-149
PL560-48
30 - 80
2
60 - 160
PECL
155.52
-65
-95 -122 -138 -142 -148 -149
PL560-49
30 - 80
2
60 - 160
LVDS
155.52
-65
-95
-122
-138
-142
-148
-149
PL560-68
75 - 200
2
150 - 400
PECL
311.04
-60
-85 -112 -135 -142 -150 -151
PL560-69
75 - 200
2
150 - 400
LVDS
311.04
-60
-85
-112
-135
-142
-150
-151
Phase Noise numbers were obtained using Agilent 5500.


FREQUENCY VERSUS JITTER, AND SUB-HARMONIC PERFORMANCE
RMS Period
Jitter
(Ps)
Peak to Peak
Period Jitter
(Ps)
RMS Accumulated
(L.T.) Jitter (Ps)
Phase Jitter
(12 KHz-20MHz)
(Ps)
Spectral Specifications / Sub-harmonic Content
(dB), Frequency (MHz)
Part
Number
Jitter
Calc.
Freq.
(MHz)
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Carrier
Freq.
(Fc)
@
-75%
(Fc)
@
-50%
(Fc)
@
-25%
(Fc)
@
+25%
(Fc)
@
+50%
(Fc)
@
+75%
(Fc)
PL560-08
622 4 6 25
30
6 0.09 622 -50 -50 -45 -47 -47 -55
PL560-09
622
4
6
25
30
6
0.09
622
-50
-50
-45
-47
-47
-55
PL560-37
155 2.5
3 18
20
3 0.25
155.52
-75
-62 -65
-75
PL560-38
155
2.5
3
18
20
3
0.25
155.52 -75
-62
-65
-75
PL560-39
155 2.5
3 18
20
3 0.25
155.52
-75
-62 -65
-75
PL560-47
155
2.5
3
18
20
3
0.25
155.52
-68
-68
PL560-48
155 2.5
3 18
20
3 0.25
155.52
-68 -68
PL560-49
155
2.5
3
18
20
3
0.27
155.52
-68
-68
PL560-68
311 2.5
3 18
20
3 0.18
311.04
-72 -85
PL560-69
311
2.5
3
18
20
3
0.18
311.04
-72
-85
Note: Wavecrest Data 10,000 hits. No Filtering was used in Jitter Calculations.
Agilent 5500 was used for Phase Jitter Calculations.
Spectral Specifications were obtained using Agilent E7401A.
Analog Frequency Multiplier
VCXO Family of Products
47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev.:03-22-05 Page 4
CRYSTAL SPECIFICATIONS AND BOARD LAYOUT CONSIDERATIONS
BOARD LAYOUT CONSIDERATIONS
To minimize parasitic effects, and improve performance:
Place the crystal as close as possible to the IC.
Make the board traces that are connected to the crystal pins symmetrical.
The board trace symmetry is important, as it reduces the negative parasitic effects, for a clean frequency multiplication with low
jitter. Parasitic have negative effect on frequency pulling of a VCXO and jitter.
CRYSTAL SPECIFICATIONS & TUNING PERFORMANCE
CRYSTAL SPECIFICATIONS
TUNING PERFORMANCE
CL (xtal)
ESR
(R
E
)
CRYSTAL TUNING
(Typical)
PART
NUMBER
CRYSTAL
RESONATOR
FREQUENCY
(FXIN)
MOD
E
CONDI-
TIONS
TYP. Max.
CRYSTAL
FREQ
(MHz)
C0 C1 C0/C1
VC:
1.65V 0V
VC:
1.65V 3.4V
155.52
3.0pF
12.2fF
245
-145 ppm
+108 ppm
PL560-08/09
PL560-68/69
75~200MHz
Funda-
mental
At
Vcon
=
1.65V
5pF
30
155.52
1.8pF
5.7fF
316
-134 ppm
+87 ppm
30.72
2.8pF
12.4fF
228
-167ppm
+176ppm
30.72
4.5pF
19.1fF
236
-163ppm
+167ppm
38.88
5.1pF
20.9fF
242
-131ppm
+98ppm
38.88
5.3pF
25.6fF
207
-157ppm
+141ppm
PL560-
37/38/39
PL560-
47/48/49
30~80MHz
Funda-
mental
At
Vcon
=
1.65V
5pF
30
77.76
2.0pF
6.7fF
305
-92ppm
+110ppm
Note: Non specified parameters can be chosen as standard values from crystal suppliers.
CL ratings larger than 5pF require a crystal frequency adjustment. Request detailed crystal specifications from PhaseLink.
XTA
XTAL
Ceramic
SMD
AFM IC
XIN (Pin # 4)
XOUT (Pin # 5)
AFM IC
XIN (Pin # 4)
XOUT (Pin # 5)
Analog Frequency Multiplier
VCXO Family of Products
47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev.:03-22-05 Page 5
VOLTAGE CONTROL SPECIFICATION
PARAMETERS SYMBOL
CONDITIONS MIN.
TYP.
MAX.
UNITS
VCXO Stabilization Time
T
VCXOSTB
From power valid
10
ms
VCXO Tuning Range
XTAL C
0
/C
1
<300
200 ppm
CLK output pullability
VCON= 1.65V
1.65V
XTAL C
0
/C
1
<300
100
120
ppm
Linearity
5
10
%
VCON input impedance
130
k
VCON modulation BW
0V < VCON < 3.3V, -3dB
25
kHz
EXTERNAL COMPONENT VALUES
INDUCTOR VALUE OPTIMIZATION

The required inductor value(s) for the best performance depends on the operating frequency, and the board
layout specifications. The listed values in this datasheet are based on the calculated parasitic values from
PhaseLink's evaluation board design (Gerber file available upon request). These inductor values provide the user
with a starting point to determine the optimum inductor values. Additional fine-tuning may be required to
determine the optimal solution.

To assist with the inductor value optimization, PhaseLink has developed the "AFM Tuning Assistant" software.
You can download this software from PhaseLink's web site (www.phaselink.com). The software consists of two
worksheets. The first worksheet (named L2) is used to fine-tune the `L2' inductor value, and the second
worksheet (named L4) is used for fine tuning of the `L4' (used in 4x AFMs only) inductor value.

For those designs using PhaseLink's recommended board layout, you can use the "AFM Tuning Assistant" to
determine the optimum values for the required inductors. This software is developed based on the parasitic
information from PhaseLink's board layout and can be used to determine the required inductor and parallel
capacitor (see LWB1 and Cstray parameters) values. For those employing a different board layout in their
design, we recommend to use the parasitic information of their board layout to calculate the optimized inductor
values. Please use the following fine tuning procedure: