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Электронный компонент: PL580-38QCL

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(Preliminary)
PL580-37/38/39
38MHz-320MHz Low Phase Noise VCXO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 1
FEATURES
Less than 0.4ps RMS (12KHz-20MHz) phase
jitter for
all frequencies
.
Less than 25ps (typ.) peak to peak jitter for all
frequencies.
Low phase noise output (@ 1MHz frequency
offset
-144dBc/Hz for 155.52MHz
-140dBC/Hz for 311.04MHz
19MHz-40MHz crystal input.
38MHz-320MHz output.
Available in PECL, LVDS, or CMOS outputs.
No external varicap required.
Output Enable selector.
Wide pull range (+/-200ppm).
3.3V operation.
Available in 3x3 QFN or 16-pin TSSOP
packages.
DESCRIPTION
The PL580-3X is a monolithic low jitter and low
phase noise VCXO, capable of 0.4ps RMS phase
jitter and CMOS, LVDS, or PECL outputs, covering a
wide frequency output range up to 320MHz. It allows
the control of the output frequency with an input
voltage (VCON), using a low cost crystal.
The frequency selector pads of PL580-3X enable
output frequencies of (2, 4, 8, or 16) * F
XIN
. The
PL580-3X is designed to address the demanding
requirements of high performance applications such
as SONET, GPS, Video, etc.
BLOCK DIAGRAM

PACKAGE PIN ASSIGNMENT
16-pin TSSOP

3x3 QFN
Note1: QBAR is used for single ended CMOS output
.
Note2: ^ Denotes internal pull up resistor.
PL5
80-3
X
1
2
3
4
5
6
7
8
VDDANA
9
10
11
12
13
14
15
16
XIN
XOUT
SEL2^
OE_CTRL
VCON
GNDANA
LP
SEL0^
GNDBUF
SEL1^
GNDBUF
QBAR
VDDBUF
Q
LM
PL580-3X
GNDBUF
VDDBUF
Q
QBAR
XI
N
SEL0
^
SEL1
^
VDD
A
NA
SEL2^
XOUT
OE_CTRL
VCON
LP
GN
DA
N
A
LM
GN
D
B
UF
4
16
15
14
13
12
11
10
9
8
7
6
5
1
2
3
Phase
Detector
Charge
Pump
Loop
Filter
VCO
(F
XiN
x16)
VCO
Divider
XTAL
OSC
QBAR
OE
XIN
XOUT
Q
VCON
VARICAP
+
Performance Tuner
Output
Divider
(1,2,4,8)
(Preliminary)
PL580-37/38/39
38MHz-320MHz Low Phase Noise VCXO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 2
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
0 (Default)
Output enabled
PLL580-38 (PECL)
1 Tri-state
0 Tri-state
PLL580-37 & 39 (CMOS or LVDS)
1 (Default)
Output enabled
PIN DESCRIPTIONS
Name
TSSOP
Pin number
3x3mm QFN
Pin number
Type Description
VDDANA
1
11
P
VDD for analog Circuitry.
XIN
2
12
I
Crystal input pin. (See Crystal Specifications on page 4).
XOUT
3
13
O
Crystal output pin. (See Crystal Specifications on page 4).
SEL2
4
14
I
Output frequency Selector pin.
OE_CTRL
5
15
I
Output enable control pin. (See OE_CTRL Logic Levels).
VCON
6
16
I
Voltage control input.
GNDANA
7
1
P
Ground for analog circuitry.
LP 8 2
-
LM 9 3
-
Tuning inductor connection. The inductor is recommended to be
a high Q small size 0402 or 0603 SMD component, and must be
placed between LP and adjacent LM pin. Place inductor as close
to the IC as possible to minimize parasitic effects and to
maintain inductor Q.
GNDBUF
10
4
P
GND connection for output buffer circuitry.
Q
11
5
O
PECL or LVDS output.
VDDBUF 12
6 P
VDD connection for output buffer circuitry. VDDBUF should be
separately decoupled from other VDDs whenever possible.
QBAR
13
7
O
Complementary PECL, LVDS, Or single ended CMOS output.
GNDBUF
14
8
P
GND connection for output buffer circuitry.
SEL1
15
9
I
Output frequency Selector pin.
SEL0
16
10
I
Output frequency Selector pin.
(Preliminary)
PL580-37/38/39
38MHz-320MHz Low Phase Noise VCXO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 3
FREQUENCY SELECTION TABLE
SEL2 SEL1
SEL0
Selected Multiplier/Output Frequency
0 0 0
VCO
Max*
0 0 1
VCO
Min*
0 1 0
Reserved
0 1 1
Reserved
1 0 0
Fin
x
2
1 0 1
Fin
x
8
1 1 0
Fin
x
16
1 1 1
Fin
x
4
All SEL pads have internal pull-ups (default value is `1'). Bond to GND to set to 0.
* Special Test Modes to help selecting the inductor value for the target output frequency.
PERFORMANCE TUNING & INDUCTOR VALUE SELECTION
Please refer to PhaseLink's `PhasorV Tuning Assistance' software to automatically calculate the optimum inductor
values for your application. In addition, the chart below could be used as a reference for quick inductor value
selection. Please note that the inductor values mentioned in the table below, or when using `PhasorV Tuning
Assistance' are derived based on the parasitic values of PhaseLink's evaluation board. For performance
enhancement of your custom board design, please follow the following instruction:

Use the special test modes "VCO Max" and "VCO Min" to determine the optimum inductor value. "VCO Max"
represents the high end of the VCO range and "VCO Min" represents the low end of the VCO range. The output
frequency in the "VCO Max" and "VCO Min" test modes is VCO/16. This means that the output frequencies are
around the crystal frequency that will be used. The optimum inductor value is where the target crystal frequency
is closest to the middle between the "VCO Max" and "VCO Min" output frequencies. In this case the VCO will lock
in the middle of its tuning range with maximum margin on either side.
(Preliminary)
PL580-37/38/39
38MHz-320MHz Low Phase Noise VCXO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 4
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
V
DD
4.6 V
Input Voltage, dc
V
I
-0.5
V
DD
+0.5 V
Output Voltage, dc
V
O
-0.5
V
DD
+0.5 V
Storage Temperature
T
S
-65 150
C
Ambient Operating Temperature*
T
A
-40 85
C
Junction Temperature
T
J
125
C
Lead Temperature (soldering, 10s)
260
C
ESD Protection, Human Body Model
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
Crystal Resonator Frequency
F
XIN
Parallel Fundamental Mode
19
40
MHz
at VCON = 0V
17.7
at VCON = 1.65V
9.5
Crystal Loading Rating
C
L (xtal)
at VCON = 3.3V
5.4
pF
Crystal Pullability
C
0
/C
1 (xtal)
AT
cut
250
-
Recommended ESR
R
E
AT cut
30
Note: Crystal Loading rating: The listed numbers are for the IC only. Specify the crystal for the value at VCON = 1.65V and add the PCB & package
parasitic. A round number (i.e. 12pF) can be achieved by adding external capacitors. Try to add the same value to XIN and XOUT, and please note,
that frequency pulling and oscillator gain may decrease.
3. Voltage Control Crystal Oscillator
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
VCXO Stabilization Time *
T
VCXOSTB
From power valid
10
ms
VCXO Tuning Range
F
XIN
= 19 40MHz;
XTAL C
0
/C
1
< 250
0V
VCON 3.3V
500 ppm
CLK output pullability
VCON=1.65V,
1.65V
200
ppm
VCXO Tuning Characteristic
150
ppm/V
Pull range linearity
10
%
VCON pin input impedance
60
80
k
VCON modulation BW
0V
VCON 3.3V, -3dB
25
kHz
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
(Preliminary)
PL580-37/38/39
38MHz-320MHz Low Phase Noise VCXO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 5

4. General Electrical Specifications
PARAMETERS SYMBOL
CONDITIONS
MIN. TYP. MAX. UNITS
38MHz<Fout<100MHz
65/45/30
Supply Current,
Dynamic (with
Loaded Outputs)
I
DD
PECL/LVDS/CMOS
100MHz<Fout<320MHz
80/60/40
mA
Operating Voltage
V
DD
2.97 3.63 V
Output Clock
Duty Cycle
@ 50% V
DD
(CMOS)
@ 1.25V (LVDS)
@ V
DD
1.3V (PECL)
45
45
45
50
50
50
55
55
55
%
Short Circuit
Current
50
mA
Note: CMOS operation is not advised above 200MHz with 15pF load; and 320MHz with 10pF load.
5. Jitter Specifications
PARAMETERS CONDITIONS
FREQUENCY MIN. TYP. MAX. UNITS
155.52MHz 0.4
0.5
Integrated jitter RMS
Integrated 12 kHz to 20 MHz
311.04MHz 0.4
0.5
ps
77.76MHz 2.5
4
155.52MHz 3 5
Period jitter RMS
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
311.04MHz 4 7
ps
77.76MHz 18
30
155.52MHz 20 30
Period jitter Peak-to-
Peak
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
311.04MHz
25 35
ps
6. Phase Noise Specifications
PARAMETERS FREQ.
@10Hz @100Hz @1kHz
@10kHz @100kHz @1M @10M
UNITS
77.76MHz -66 -96 -124 -134 -132 -145 -149
155.52MHz -62 -92 -120 -132 -128 -144 -150
Phase Noise
relative to
carrier (typical)
311.04MHz -59 -86 -116 -129 -124 -140 -148
dBc/Hz
Note: Phase Noise measured at VCON = 0V.
7. CMOS Electrical Characteristics
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
I
OH
V
OH
= V
DD
-0.4V, V
DD
=3.3V 30 mA
Output drive current
I
OL
V
OL
= 0.4V, V
DD
= 3.3V
30
mA
Output Clock Rise/Fall Time
0.3V ~ 3.0V with 15 pF load
0.7
ns
Output Clock Rise/Fall Time
20%-80% with 50 Load
0.3 ns
(Preliminary)
PL580-37/38/39
38MHz-320MHz Low Phase Noise VCXO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 6
8. LVDS Electrical Characteristics
PARAMETERS SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Output Differential Voltage
V
OD
247
355
454
mV
V
DD
Magnitude Change
V
OD
-50
50 mV
Output High Voltage
V
OH
1.4
1.6
V
Output Low Voltage
V
OL
0.9
1.1
V
Offset Voltage
V
OS
1.125
1.2
1.375
V
Offset Magnitude Change
V
OS
R
L
= 100
(see figure)
0
3 25 mV
Power-off Leakage
I
OXD
V
out
= V
DD
or GND
V
DD
= 0V
1
10
uA
Output Short Circuit Current
I
OSD
-5.7 -8
mA
9. LVDS Switching Characteristics
PARAMETERS SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Differential Clock Rise Time
t
r
0.2 0.7 1.0 ns
Differential Clock Fall Time
t
f
R
L
= 100
C
L
= 10 pF
(see figure)
0.2 0.7 1.0 ns
OUT
OUT
V
OD
V
OS
50
50
OUT
V
DIFF
R
L
= 100
C
L
= 10pF
C
L
= 10pF
LVDS Switching Test Circuit
LVDS Levels Test Circuit
LVDS Transistion Time Waveform
OUT
OUT
OUT
0V (Differential)
0V
20%
80%
20%
80%
t
R
t
F
V
DIFF
(Preliminary)
PL580-37/38/39
38MHz-320MHz Low Phase Noise VCXO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 7
10. PECL Electrical Characteristics
PARAMETERS SYMBOL CONDITIONS
MIN. MAX.
UNITS
Output High Voltage
V
OH
V
DD
1.025
V
Output Low Voltage
V
OL
R
L
= 50
to (V
DD
2V)
(see figure)
V
DD
1.620
V
11. PECL Switching Characteristics
PARAMETERS SYMBOL
FREQ.
CONDITIONS MIN. TYP. MAX. UNITS
Clock Rise & Fall Times
<150MHz
0.2 0.5 0.7
Clock Rise & Fall Times
t
r &
t
f
>150MHz
<320MHz
@20/80% - PECL
@80/20% - PECL
0.2 0.4 0.55
ns
OUT
OUT
50
50
PECL Levels Test Circuit
PECL Transistion Time Waveform
OUT
OUT
50%
20%
80%
t
R
t
F
VDD
DUTY CYCLE
45 - 55%
55 - 45%
50%
OUT
OUT
t
SKEW
PECL Output Skew
2.0V
(Preliminary)
PL580-37/38/39
38MHz-320MHz Low Phase Noise VCXO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 8
LAYOUT RECOMMENDATIONS


PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION
The following guidelines are to assist you with a performance optimized PCB design:
- Keep all the PCB traces to PL580 as short as
possible, as well as keeping all other traces as
far away from it as possible.
- Place the crystal as close as possible to both
crystal pins of the device. This will reduce the
cross-talk between the crystal and the other
signals.
- Separate crystal pin traces from the other signals
on the PCB, but allow ample distance between
the two crystal pin traces.
- Place a 0.01F~0.1F decoupling capacitor
between VDD and GND, on the component side
of the PCB, close to the VDD pin. It is not
recommended to place this component on the
backside of the PCB. Going through vias will
reduce the signal integrity, causing additional
jitter and phase noise.
- It is highly recommended to keep the VDD and
GND traces as short as possible.
- When connecting long traces (> 1 inch) to a
CMOS output, it is important to design the traces
as a transmission line or `stripline', to avoid
reflections or ringing. In this case, the CMOS
output needs to be matched to the trace
impedance. Usually `striplines' are designed for
50 impedance and CMOS outputs usually have
lower than 50 impedance so matching can be
achieved by adding a resistor in series with the
CMOS output pin to the `stripline' trace.
- Please contact PhaseLink for the application note
on how to design outputs driving long traces or
the Gerber files for the PL580 layout.
(Preliminary)
PL580-37/38/39
38MHz-320MHz Low Phase Noise VCXO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 9
PACKAGE INFORMATION
16-PIN SSOP
C
L
A
E
H
D
A1
e
B
16 PIN TSSOP ( mm )
Symbol
Min.
Max.
A
-
1.20
A1
0.05
0.15
B
0.19
0.30
C
0.09
0.20
D
4.90
5.10
E
4.30
4.50
H
6.40 BSC
L
0.45
0.75
e
0.65 BSC


16-PIN 3x3 QFN




(Preliminary)
PL580-37/38/39
38MHz-320MHz Low Phase Noise VCXO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/29/05 Page 10
ORDERING INFORMATION

PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PL580-3X
X C L R
Order Number
Marking
Package Option
PL580-37OC
P580-37OC
TSSOP - Tube
PL580-37OC-R
P580-37OC
TSSOP - Tape & Reel
PL580-37OCL
P580-37OCL
TSSOP - Tube (GREEN Package)
PL580-37OCL-R
P580-37OCL
TSSOP - Tape & Reel (GREEN Package)
PL580-37QC
P580-37QC
QFN - Tube
PL580-37QC-R
P580-37QC
QFN - Tape & Reel
PL580-37QCL
P580-37QCL
QFN - Tube (GREEN Package)
PL580-37QCL-R
P580-37QCL
QFN - Tape & Reel (GREEN Package)
PL580-38OC
P580-38OC
TSSOP - Tube
PL580-38OC-R
P580-38OC
TSSOP - Tape & Reel
PL580-38OCL
P580-38OCL
TSSOP - Tube (GREEN Package)
PL580-38OCL-R
P580-38OCL
TSSOP - Tape & Reel (GREEN Package)
PL580-38QC
P580-38QC
QFN - Tube
PL580-38QC-R
P580-38QC
QFN - Tape & Reel
PL580-38QCL
P580-38QCL
QFN - Tube (GREEN Package)
PL580-38QCL-R
P580-38QCL
QFN - Tape & Reel (GREEN Package)
PL580-39OC
P580-39OC
TSSOP - Tube
PL580-39OC-R
P580-39OC
TSSOP - Tape & Reel
PL580-39OCL
P580-39OCL
TSSOP - Tube (GREEN Package)
PL580-39OCL-R
P580-39OCL
TSSOP - Tape & Reel (GREEN Package)
PL580-39QC
P580-39QC
QFN - Tube
PL580-39QC-R
P580-39QC
QFN - Tape & Reel
PL580-39QCL
P580-39QCL
QFN - Tube (GREEN Package)
PL580-39QCL-R
P580-39QCL
QFN - Tape & Reel (GREEN Package)
TEMPERATURE
C=COMMERCIAL
I=INDUSTRAL
PACKAGE TYPE
O=TSSOP
Q= QFN 4x4
L= GREEN PACKAGE
NONE= REGULAR PACKAGE
R= TAPE & REEL
NONE= TUBE
PART NUMBER