Preliminary
PL623-38
Low Phase Noise XO (for 3
rd
O.T.) For 65-130MHz
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 05/03/05 Page 1
FEATURES
Input: 65-130MHz 3
rd
Overtone or fundamental
Crystal
Output frequency: Up to 130MHz
Selectable /2, /4, /8 output dividers with 60K
pull up resistor on the selector pins
Available output: PECL
Supports 2.5V or 3.3V-Power Supply
Available in die form
DESCRIPTION
PL623-38 is an XO IC specifically designed to work
with high frequency 3
rd
overtone or fundamental
crystals from 65MHz to 135MHz. It requires an
external resistor for the 3
rd
overtone selection. Its
design was optimized to tolerate higher limits of
inter-electrodes capacitance and bonding
capacitance to improve yield. It achieves very low
current into the crystal resulting in better overall
stability. It is ideal for XO applications requiring
PECL output levels at high frequencies.
BLOCK DIAGRAM
DIE CONFIGURATION
Note: `^' Denotes 60k pull-up resistor
DIE SPECIFICATIONS
Name Value
Size
57.5 x 56.5 mil
Reverse side
GND
Pad dimensions
80 micron x 80 micron
Thickness 10
mil
OE SELECTION
Pad #12
OESEL
Pad #22
OECTRL
State
0 Tri-state
1
1
Output enabled (default)
0
Output enabled (default)
0
(default)
1 Tri-state
Pad #12: Bond to VDD to set to "1"
Pad #22: Logical states defined by PECL levels
OUTPUT DIVIDER SELECTOR LOGIC
SEL 0
SEL1
Output
0 0
No
Divider
1
0
Divide by 2
0
1
Divide by 4
1
1
Divide by 8
XIN
XOUT
OECTRL
Q
PL623-38
Q
Oscillator
Amplifier
3
rd
OT
Re
si
stor
Y
X
(0,0)
(1460,1435)
56.5 mil
57.5 mil
VDDA
N
A
XIN
XOUT
GNDBUF
Q
Q
VDDBUF
GNDBU
F
GNDAS
H
IELD
GNDA
N
A
OECTRL
OESEL (pull down)
SE
L0
VDDBUF
GN
DB
S
H
IE
L
D
SE
L
1
VD
DO
SC
GN
D
O
S
C
GN
D
O
S
C
VDDB
U
F
OECTRL
GN
DO
SC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Die ID: C560A-FFFF-FP
^
^
Preliminary
PL623-38
Low Phase Noise XO (for 3
rd
O.T.) For 65-130MHz
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 05/03/05 Page 2
DIE PAD ASSIGNMENT
Pad #
Name
X (
m) Y
(
m)
Pad Description
1
GNDOSC
329.6
110.1
GND connection for oscillator circuitry.
2
GNDOSC
498.3
110.0
GND connection for oscillator circuitry.
3
GNDANA
696.2
110.0
GND connection for analog circuitry.
4 GNDSHIELD 825.0 110.0
GND shielding connection.
5 GNDSHIELD 973.6 110.0
GND shielding connection.
6
GNDBUF
1150.0
109.1
GND connection for output buffer circuitry.
7
GNDBUF
1183.6
302.2
GND connection for output buffer circuitry.
8 Q 1183.6
452.3
PECL
output.
9 QBAR
1183.6 613.5
Complementary
PECL
output.
10 VDDBUF 1182.4
745.9
VDD connection for output buffer circuitry. VDDBUF should be
separately decoupled from other VDDs whenever possible.
11 VDDBUF 1252.4
903.6
VDD connection for output buffer circuitry. VDDBUF should be
separately decoupled from other VDDs whenever possible.
12 OESEL 1252.4
1081.3
This is the selector input to choose the OE control logic to be
applied, as presented on the OE SELECTION TABLE on page `1'.
13 VDDBUF 1058.5
1221.6
VDD connection for output buffer circuitry.
VDDBUF should be separately decoupled from other VDDs
whenever possible.
14 VDDANA 864.5
1221.6
VDD connection for analog circuitry. VDDANA should be
separately decoupled from other VDDs whenever possible.
15 VDDOSC 624.0
1222.7
VDD connection for oscillator circuitry. VDDOSC should be
separately decoupled from other VDDs whenever possible.
16 SEL1 467.1
1222.6
Output Divider Selector pin as presented on the DIVIDER
SELECTOR TABLE on page `1'.
17 SEL0 271.1
1222.6
Output Divider Selector pin as presented on the DIVIDER
SELECTOR TABLE on page `1'.
18
GNDOSC
109.4
1222.9
GND connection for oscillator circuitry.
19
OECTRL
108.9
1062.1
Output Enable input pad. See OE SELECTION TABLE on page 1.
20 XIN 109.0
865.8
Crystal connector pad. This pad is the input of the crystal
oscillator circuitry. The crystal should be mounted as close to the
IC as possible, with minimum parasitic capacitance.
21 XOUT 108.6
358.4
Crystal connector pad. This pad is the input of the crystal
oscillator circuitry. The crystal should be mounted as close to the
IC as possible, with minimum parasitic capacitance.
22
OECTRL
108.6
146.5
Output Enable input pad. See OE SELECTION TABLE on page 1.
Preliminary
PL623-38
Low Phase Noise XO (for 3
rd
O.T.) For 65-130MHz
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 05/03/05 Page 3
EXTERNAL COMPONENT VALUES 3
RD
OVERTONE RESISTOR SELECTIONS
This resistor is only required when a third overtone crystal is used. The chart below indicates the calculated and the nearest "E12"
resistor values versus frequency for PL623-38.
Frequency
(MHz)
R3OT
()
E12 Pick
K
Frequency
(MHz)
R3OT
()
E12 Pick
K
65 2,162 2.2 100 1,406 1.5
67.5 2,082 2.2
102.5 1,372 1.5
70 2,008 2.2 105 1,339 1.2
75 1,875 1.8 107.5
1,308 1.2
77.5 1,815 1.8 110 1,278 1.2
80 1,758 1.8 112.5
1,250 1.2
82.5 1,705 1.8 115 1,223 1.2
85 1,654 1.8 117.5
1,197 1.2
87.5 1,607 1.5 120 1,172 1.2
90 1,563 1.5 122.5
1,148 1.2
92.5 1,520 1.5 125 1,125 1.2
95 1,480 1.5 127.5
1,103 1.2
97.5 1,442 1.5 130 1,082 1.0
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
V
DD
4.6 V
Input Voltage, dc
V
I
V
SS
-0.5 V
DD
+0.5 V
Output Voltage, dc
V
O
V
SS
-0.5 V
DD
+0.5 V
Storage Temperature
T
S
-65 150
C
Ambient Operating Temperature
T
A
-40 +85
C
Input Static Discharge Voltage Protection
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
Preliminary
PL623-38
Low Phase Noise XO (for 3
rd
O.T.) For 65-130MHz
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 05/03/05 Page 4
2. Crystal Specifications
3. General Electrical Specifications
PARAMETERS
SYMBO
L
CONDITIONS MIN.
TYP.
MAX.
UNITS
Supply Current (Loaded
Outputs)
I
DD
PECL
85/55 mA
Operating Voltage
V
DD
2.25
3.63 V
Output Clock Duty Cycle
@ Vdd 1.3V (PECL)
45 50 55
%
Short Circuit Current
50
mA
4. Jitter Specifications
PARAMETERS CONDITIONS
MIN.
TYP.
MAX.
UNITS
Period jitter RMS at 106.25MHz
2.0
Period jitter peak-to-peak at 106.25MHz
With capacitive decoupling
between VDD and GND.
17.0
ps
Integrated jitter RMS at 106.25MHz
Integrated 12 kHz to 20 MHz
0.3*
ps
*Measured on Agilent E5500.
5. Phase Noise Specifications
PARAMETERS FREQUENCY @10Hz
@100Hz @1kHz @10kHz @100kHz UNITS
Phase Noise vs. carrier
with fund. crystal.
106.25MHz -55 -90 -110 -135 -145
dBc/Hz
*: Note: Phase noise to be measured. Based on P520-20 product (fundamental 155MHz VCXO).
Name Symbol
Conditions
Min. Max. Units
Parallel Resonant mode
3
rd
Overtone
N/A
Load capacitance (capacitance on
built-in on die seen by crystal)
C
L
Die only, no bond wire,
no package
5 pF
Inter-electrode capacitance
C
0
4
pF
Equivalent Series Resistance
ESR
35
Oscillation Frequency
3
rd
Overtone
65
130
MHz
Preliminary
PL623-38
Low Phase Noise XO (for 3
rd
O.T.) For 65-130MHz
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 05/03/05 Page 5
8. PECL Electrical Characteristics
PARAMETERS SYMBOL CONDITIONS
MIN. MAX.
UNITS
Output High Voltage
V
OH
V
DD
1.025
V
Output Low Voltage
V
OL
R
L
= 50
to (V
DD
2V)
(see figure)
V
DD
1.620
V
9. PECL Switching Characteristics
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
Clock Rise Time
t
r
@20/80% - PECL
0.2
0.4
ns
Clock Fall Time
t
f
@80/20% - PECL
0.2
0.4
ns
OUT
OUT
50
50
PECL Levels Test Circuit
PECL Transistion Time Waveform
OUT
OUT
50%
20%
80%
t
R
t
F
VDD
DUTY CYCLE
45 - 55%
55 - 45%
50%
OUT
OUT
t
SKEW
PECL Output Skew
2.0V
Preliminary
PL623-38
Low Phase Noise XO (for 3
rd
O.T.) For 65-130MHz
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 05/03/05 Page 6
ORDERING INFORMATION
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PL623-38 D
X
Order Number
Marking
Package Option
PL623-38DC
P623-38
Waffle Pack
PART NUMBER
TEMPERATURE
C= COMMERCIAL
I= INDUSTRIAL
PACKAGE TYPE
D=DIE
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