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Электронный компонент: PL680-37OCL-R

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(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 1
FEATURES
Less than 0.4ps RMS (12KHz-20MHz) phase
jitter for
all frequencies
.
Less than 25ps peak to peak jitter for all
frequencies.
Low phase noise output (@ 1MHz frequency
offset
-144dBc/Hz for 106.25MHz
-144dBc/Hz for 156.25MHz
-144dBc/Hz for 212.5MHz
-140dBc/Hz for 312.5MHz,
-131dBC/Hz for 622.08MHz
19MHz-40MHz crystal input.
38MHz-640MHz output.
Available in PECL, LVDS, or CMOS outputs.
Output Enable selector.
2.5V & 3.3V operation.
Available in 3x3 QFN or 16-pin TSSOP
packages.
DESCRIPTION
The PL680-3X is a monolithic low jitter and low
phase noise high performance clock, capable of
maintaining 0.4ps RMS phase jitter and CMOS,
LVDS or PECL outputs, covering a wide frequency
output range up to 640MHz. It allows high
performance and high frequency output, using a low
cost fundamental crystal of between 19-40MHz..
The frequency selector pads of PL680-3X enable
output frequencies of (2, 4, 8, or 16) * F
XIN
. The
PL680-3X is designed to address the demanding
requirements of high performance applications such
Fiber Channel, serial ATA, Ethernet, SAN, etc.

PACKAGE PIN ASSIGNMENT
16-pin TSSOP

3x3 QFN
Note1: QBAR is used for single ended CMOS output
.
Note2: ^ Denotes internal pull up resistor.
BLOCK DIAGRAM
PL6
80-3
X
1
2
3
4
5
6
7
8
VDDANA
9
10
11
12
13
14
15
16
XIN
XOUT
SEL2^
OE_CTRL
DNC
GNDANA
LP
SEL0^
GNDBUF
SEL1^
GNDBUF
QBAR
VDDBUF
Q
LM
PL680-3X
GNDBUF
VDDBUF
Q
QBAR
XI
N
SEL0
^
SEL1
^
VDD
A
NA
SEL2^
XOUT
OE_CTRL
DNC
LP
GN
DA
N
A
LM
G
NDBU
F
4
16
15
14
13
12
11
10
9
8
7
6
5
1
2
3
Phase
Detector
Charge
Pump
Loop
Filter
VCO
(F
XiN
x16)
VCO
Divider
XTAL
OSC
QBAR
OE
XIN
XOUT
Q
+
Performance Tuner
Output
Divider
(1,2,4,8)
(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 2
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
0 (Default)
Output enabled
PL680-38 (PECL)
1 Tri-state
0 Tri-state
PL680-37 & 39 (CMOS or LVDS)
1 (Default)
Output enabled
PIN DESCRIPTIONS
Name
TSSOP
Pin number
3x3mm QFN
Pin number
Type Description
VDDANA
1
11
P
VDD for analog Circuitry.
XIN
2
12
I
Crystal input pin. (See Crystal Specifications on page 3).
XOUT
3
13
O
Crystal output pin. (See Crystal Specifications on page 3).
SEL2
4
14
I
Output frequency Selector pin.
OE_CTRL 5
15 I
Output enable control pin. (See OE_CTRL Logic Levels on page
1).
DNC
6
16
-
Do Not Connect
GNDANA
7
1
P
Ground for analog circuitry.
LP 8 2
-
LM 9 3
-
Tuning inductor connection. The inductor is recommended to be
a high Q small size 0402 or 0603 SMD component, and must be
placed between LP and adjacent LM pin. Place inductor as close
to the IC as possible to minimize parasitic effects and to
maintain inductor Q.
GNDBUF
10
4
P
GND connection for output buffer circuitry.
Q
11
5
O
PECL or LVDS output.
VDDBUF 12
6 P
VDD connection for output buffer circuitry. VDDBUF should be
separately decoupled from other VDDs whenever possible.
QBAR 13 7
O
Complementary PECL, LVDS output; Or single ended CMOS
output.
GNDBUF
14
8
P
GND connection for output buffer circuitry.
SEL1
15
9
I
Output frequency Selector pin.
SEL0
16
10
I
Output frequency Selector pin.
(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 3
FREQUENCY SELECTION TABLE
SEL2 SEL1
SEL0
Selected Multiplier/Output Frequency
0 0 0
VCO
Max*
0 0 1
VCO
Min*
0 1 0
Reserved
0 1 1
Reserved
1 0 0
Fin
x
2
1 0 1
Fin
x
8
1 1 0
Fin
x
16
1 1 1
Fin
x
4
All SEL pads have internal pull-ups (default value is `1'). Bond to GND to set to 0.
* Special Test Modes to help selecting the inductor value for the target output frequency.
PERFORMANCE TUNING & INDUCTOR VALUE SELECTION
Please refer to PhaseLink's `PhasorV Tuning Assistance' software to automatically calculate the optimum inductor
values. In addition, the chart below could be used as a reference for quick inductor value selection.

Use the special test modes "VCO Max" and "VCO Min" to determine the optimum inductor value. "VCO Max"
represents the high end of the VCO range and "VCO Min" represents the low end of the VCO range. The output
frequency in the "VCO Max" and "VCO Min" test modes is VCO/16. This means that the output frequencies are
around the crystal frequency that will be used. The optimum inductor value is where the target crystal frequency
is closest to the middle between the "VCO Max" and "VCO Min" output frequencies. In this case the VCO will lock
in the middle of its tuning range with maximum margin on either side.
(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 4
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
V
DD
4.6 V
Input Voltage, dc
V
I
-0.5
V
DD
+0.5 V
Output Voltage, dc
V
O
-0.5
V
DD
+0.5 V
Storage Temperature
T
S
-65 150
C
Ambient Operating Temperature*
T
A
-40 85
C
Junction Temperature
T
J
125
C
Lead Temperature (soldering, 10s)
260
C
ESD Protection, Human Body Model
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.

2. Crystal Specifications
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
Crystal Resonator Frequency
F
XIN
Parallel Fundamental Mode
19
40
MHz
Crystal Loading Rating
C
L (xtal)
17.7
pF
Crystal Shunt Capacitance
C
0 (xtal)
5
pF
Recommended ESR
R
E
AT cut
30
Note: Crystal Loading rating: 17.7pF is the loading the crystal sees from the XO chip. It is assumed that the crystal will be at nominal frequency at this
load. If the crystal requires less load to be at nominal frequency, then a capacitor can placed in series with the crystal. If the crystal requires more
load to be at nominal frequency, capacitors can be placed from XIN and XOUT to ground. This however may reduce the oscillator gain.
3. General Electrical Specifications
PARAMETERS SYMBOL
CONDITIONS
MIN. TYP. MAX. UNITS
PECL/LVDS/CMOS 38MHz<Fout<320MHz
65/45/30
Supply Current,
Dynamic (with
Loaded Outputs)
I
DD
PECL/LVDS 320MHz<Fout<640MHz
90/70
mA
Operating Voltage
V
DD
2.25
3.63
V
Output Clock
Duty Cycle
@ 50% V
DD
(CMOS)
@ 1.25V (LVDS)
@ V
DD
1.3V (PECL)
45
45
45
50
50
50
55
55
55
%
Short Circuit
Current
50
mA
Note: CMOS operation is not advised above 200MHz with 15pF load; and 320MHz with 10pF load.
(Preliminary)
PL680-37/38/39
38-640MHz Low Phase Noise XO
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 5
4. Jitter Specifications
PARAMETERS CONDITIONS
FREQUENCY MIN. TYP. MAX. UNITS
106.25MHz 0.4
0.5
156.25MHz 0.4
0.5
212.5MHz 0.4
0.5
312.5MHz 0.4
0.5
Integrated jitter RMS
Integrated 12 kHz to 20 MHz
622.08MHz 0.4
0.5
ps
106.25MHz 3 5
156.25MHz 3 5
212.5MHz 3 5
312.5MHz 3 5
Period jitter RMS
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
622.08MHz 6 8
ps
106.25MHz 20 30
156.25MHz 20 30
212.5MHz 20
30
312.5MHz 20
30
Period jitter Peak-to-
Peak
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
622.08MHz 40 50
ps

5. Phase Noise Specifications
PARAMETERS FREQ.
@10Hz @100Hz @1kHz @10kHz @100kHz @1M @10M
UNITS
106.25MHz -66 -96 -122 -132 -126 -144 -150
156.25MHz -62 -92 -120 -132 -128 -140 -150
212.5MHz -62 -92 -118 -126 -120 -140 -150
312.5MHz -59 -85 -117 -128 -125 -139 -148
Phase Noise
relative to carrier
(typical)
622.08MHz -49 -84 -111 -120 -118 -128 -138
dBc/Hz
6. CMOS Electrical Characteristics
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
I
OH
V
OH
= V
DD
-0.4V, V
DD
=3.3V 30 mA
Output drive current
I
OL
V
OL
= 0.4V, V
DD
= 3.3V
30
mA
Output Clock Rise/Fall Time
0.3V ~ 3.0V with 15 pF load
0.7
ns
Output Clock Rise/Fall Time
20%-80% with 50 Load
0.3 ns