PLL130-68/-69
High Speed Translator Buffers: Single ended to PECL or LVDS
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1
FEATURES
Differential PECL (PLL130-68) or LVDS
(PLL130-69) output.
Accepts any single-ended REFIN input (with
as low as 100mV swing).
Internal AC coupling of REFIN
Input range from 1.0MHz to 1.0 GHz.
No Vref required.
No external current source required.
2.5 to 3.3V operation.
Available in 3x3mm QFN.
DESCRIPTION
The PLL130-68 and PLL130-69 are low cost,
high performance, high speed, translator buffers
that reproduce any input frequency from DC to
1.0GHz. They provide a pair of differential out-
puts (PECL for PLL130-68 or LVDS for PLL130-
69). Thanks to an internal AC coupling of the
reference input (REFIN), any input signal with at
least 100mV swing can be used as reference
signal, regardless of its DC value. These chips
are ideal for conversion from clipped sine wave,
TTL, CMOS, or differential signal to LVDS or
PECL.
PIN CONFIGURATION
(TOP VIEW)
OUTPUT ENABLE LOGICAL LEVELS
PLL130-68
OESEL OECTRL
OUTPUT STATE
0 (Default)
Output enabled
0 (Default)
1 Tri-state
0 Tri-state
1
1 (Default)
Output enabled
OECTRL input: Logical states defined by PECL levels.
PLL130-69
OESEL OECTRL
OUTPUT STATE
0 Tri-state
0 (Default)
1 (Default)
Output enabled
0 (Default)
Output enabled
1
1 Tri-state
OECTRL input: Logical states defined by CMOS levels.
BLOCK DIAGRAM
Input
Amplifier
Q_BAR
REFIN
Q
AC
Coupling
PLL130-6x
NC
Q_bar
OESEL
Q
5
6
7
8
16
15
14
13
1
2
3
4
12
11
10
9
Q_
ba
r
NC
VD
D
Q
REFIN
NC
NC
NC
NC
OEC
T
RL
GND
NC
PLL130-68/-69
High Speed Translator Buffers: Single ended to PECL or LVDS
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/29/04 Page 2
PIN DESCRIPTION
Name Pin
number Type
Description
NC
1, 3, 4, 6,
8, 12, 14
- No
connection.
REFIN 2
I
Reference input signal. The frequency of this signal will be reproduced
at the output (after translation to PECL or LVDS level).
OECTRL
5
I
Output enable input (See OE Logic Table on page 1).
GND 7 P
Ground
connector.
OESEL
9
I
Output enable logic selector (See OE Logic Table on page 1).
Q_BAR 10
O
Complementary output. PECL_bar on PLL130-68, LVDS_bar on
PLL130-69.
Q
11
O
True output. PECL on PLL130-68, LVDS on PLL130-69.
VDD 13 P
3.3V
Power
supply.
Q 15 O
Additional true output. PECL on PLL130-68, LVDS on PLL130-69. This
output is the same as pin 11.
Q_BAR 16
O
Additional complementary output. PECL_bar on PLL130-68, LVDS_bar
on PLL130-69. This output is the same as pin 10.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
V
DD
4.6 V
Input Voltage, dc
V
I
-0.5
V
DD
+0.5 V
Output Voltage, dc
V
O
-0.5
V
DD
+0.5 V
Storage Temperature
T
S
-65 150
C
Ambient Operating Temperature*
T
A
-40 85
C
Junction Temperature
T
J
125
C
Lead Temperature (soldering, 10s)
260
C
ESD Protection, Human Body Model
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. General Electrical Specifications
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
Fout = 156.25MHz, PECL
45
48
51
Supply Current
(both outputs loaded)
I
DD
Fout = 156.25MHz, LVDS
22
25
28
mA
Operating Voltage
V
DD
2.97 3.63 V
@ Vdd 1.3V (PECL)
Same as input
Output Clock Duty Cycle
@ 1.25V (LVDS)
Same as input
%
Short Circuit Current
50
mA
PLL130-68/-69
High Speed Translator Buffers: Single ended to PECL or LVDS
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/29/04 Page 3
3. AC Specifications
PARAMETERS CONDITIONS
MIN.
TYP.
MAX.
UNITS
Input Frequency
0
1000
MHz
Input signal swing
REFIN input
100
mV
Output Frequency
0
1000
MHz
4. PECL Electrical Characteristics
PARAMETERS SYMBOL CONDITIONS
MIN. MAX.
UNITS
Output High Voltage
V
OH
V
DD
1.025
V
DD
0.880
V
Output Low Voltage
V
OL
R
L
= 50
to (V
DD
2V)
(see figure)
V
DD
1.810
V
DD
1.620
V
5. PECL Switching Characteristics
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
Clock Rise Time
t
r
@20/80% - PECL
0.2
0.5
ns
Clock Fall Time
t
f
@80/20% - PECL
0.2
0.5
ns
OUT
OUT
50
50
PECL Levels Test Circuit
PECL Transistion Time Waveform
OUT
OUT
50%
20%
80%
t
R
t
F
VDD
DUTY CYCLE
45 - 55%
55 - 45%
50%
OUT
OUT
t
SKEW
PECL Output Skew
2.0V
PLL130-68/-69
High Speed Translator Buffers: Single ended to PECL or LVDS
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/29/04 Page 4
6. LVDS Electrical Characteristics
PARAMETERS SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Output Differential Voltage
V
OD
247
355
454
mV
V
DD
Magnitude Change
V
OD
-50
50 mV
Output High Voltage
V
OH
1.4
1.6
V
Output Low Voltage
V
OL
0.9
1.1
V
Offset Voltage
V
OS
1.125
1.2
1.375
V
Offset Magnitude Change
V
OS
R
L
= 100
(see figure)
0
3 25 mV
Power-off Leakage
I
OXD
V
out
= V
DD
or GND
V
DD
= 0V
1
10
uA
Output Short Circuit Current
I
OSD
-5.7 -8
mA
7. LVDS Switching Characteristics
PARAMETERS SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Differential Clock Rise Time
t
r
0.2 0.5 1.0 ns
Differential Clock Fall Time
t
f
R
L
= 100
C
L
= 10 pF
(see figure)
0.2 0.5 1.0 ns
OUT
OUT
V
OD
V
OS
50
50
OUT
V
DIFF
R
L
= 100
C
L
= 10pF
C
L
= 10pF
LVDS Switching Test Circuit
LVDS Levels Test Circuit
LVDS Transistion Time Waveform
OUT
OUT
OUT
0V (Differential)
0V
20%
80%
20%
80%
t
R
t
F
V
DIFF
PLL130-68/-69
High Speed Translator Buffers: Single ended to PECL or LVDS
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/29/04 Page 5
PACKAGE INFORMATION
Important note: pin 1 indicator (bottom side) is metallized and connected to GND through the leadframe. Traces in contact with the pin
1 indicator may result is short circuit to GND.
ORDERING INFORMATION
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the ex-
press written approval of the President of PhaseLink Corporation.
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL130-6X Q C
Order Number
Marking
Package Option
PLL130-68QC-R P130-68
QFN - Tape and Reel
PLL130-68QC
P130-68
QFN - Tube
PLL130-69QC-R P130-69
QFN - Tape and Reel
PLL130-69QC
P130-69
QFN - Tube
PART NUMBER
TEMPERATURE
C=COMMERCIAL
I=INDUSTRIAL
PACKAGE TYPE
Q=QFN
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