PLL202-11
Motherboard Clock Generator for 440BX Type with 133MHz FSB
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 10/19/00 Page 1
FEATURES
Generates all clock frequencies for Pentium
systems with INTEL 440BX or VIA Apollo Pro133
or Promedia chip sets, requiring multiple CPU
clocks and high speed SDRAM buffers.
Support 2 CPU clocks, 6PCI and 13 high-speed
SDRAM buffers for 3-DIMM applications.
One 24MHz clock and one 48MHz clock.
One 2.5V IOAPIC clock.
Two14.318MHz reference clocks.
Built-in programmable watchdog timer up to 63
secs with 1-second interval. It will generate a
LOW reset output when timer expired.
Support 2-wire I2C serial bus interface with built-
in Vendor ID, Device ID and Revision ID.
Single byte micro-step linear Frequency
Programming via I2C with Glitch free smooth
switching.
Spread Spectrum
0.25% center.
50% duty cycle with low jitter.
Available in 300 mil 48 pin SSOP.
BLOCK DIAGRAM
PIN CONFIGURATION
Note: ^: Pull up, #: Active Low
*
: Bi-directional latched at power-up
I/O MODE CONFIGURATION
MODE (Pin 7)
PIN 2
1 (OUTPUT)
REF0
0 (INPUT)
PCI_STOP
POWER GROUP
VDD1: REF, XIN, XOUT, PLL CORE
VDD2: PCI_F, PCI(0:4)
VDD3: SDRAM_F, SDRAM(0:11)
VDD4: 48MHz, 24MHz, SDATA, SCLK
VDDL1: IOAPIC
VDDL2: CPU_F, CPU1
KEY SPECIFICATIONS
CPU Cycle to Cycle jitter: 250ps.
PCI Cycle to Cycle jitter: 250ps.
SDRAM to SDRAM skew: 500ps.
PCI to PCI skew: 500ps.
CPU to CPU skew 250ps
CPU to PCI skew: 1 ~ 4ns, typical 2ns
SDRAMIN to SDRAM skew: 3 ~ 4ns,
typical 3.5ns.
WDRESET#
SDRAM_F
GND
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PLL202-11
VDDL1
IOAPIC
REF1/FS2*^
GND
CPU_F
CPU_1
VDDL2
VDD3
SDRAM6
SDRAM7
VDD4
48MHz/FS0*^
24MHz/FS1*^
SCLK
GND
SDRAM8
SDRAM9
VDD3
SDRAM10
SDRAM11
GND
SDRAMIN
VDD2
PCI1
GND
PCI0/FS3*
v
PCI_F/MODE*^
VDD2
XOUT
XIN
GND
REF0//PCI_STOP#^
VDD1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PCI2
PCI3
PCI4
SDRAM_F
GND
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
CPU_F
CPU_1
VDDL2
VDD3
SDRAM7
VDD4
SCLK
GND
SDRAM8
SDRAM9
VDD3
SDRAM10
GND
VDD2
GND
VDD2
GND
VDD1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PCI2
PCI3
PCI4
Control
Logic
VDDL1
IOAPIC
VDD1
REF(0:1)
XIN
XOUT
XTAL
OSC
SDRAM (0:11)
VDD3
SDRAM_F
SDRAMIN
FS (0:3)*
PLL1
SST
24Mhz
VDD4
48Mhz
PLL2
VDDL2
CPU1
CPU_F
VDD2
PCI(0:4)
PCI_F
Watch
Dog
SDATA
SCLK
I2C
Logic
WDRESET#
PLL202-11
Motherboard Clock Generator for 440BX Type with 133MHz FSB
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 10/19/00 Page 2
PIN DESCRIPTIONS
Name
Number
Type
Description
VDD1
1
P
Power supply for REF0, REF1, and crystal oscillator.
VDD2
6,14
P
Power supply for PCI_F, PCI(0:4).
VDD3
19,30,36
P
Power supply for SDRAM(0:11), SDRAM_F.
VDD4
27
P
Power supply for 24MHz and 48MHz.
VDDL1
48
P
Power supply for IOAPIC (2.5V).
VDDL2
42
P
Power supply for CPU_F and CPU1 (2.5V).
GND
3,9,16,22,
33,39,45
P
Ground.
XIN
4
I
14.318MHz crystal input to be connected to one end of the crystal.
XOUT
5
O
14.318MHz crystal output.
PCI0/F3*
REF1/F2*
24MHz/F1*
48MHz/F0*
8,46,25,26
B
At power up, these pins are input pins and will determine the CPU clock
frequency. After input sampling, these pins will generate output clocks.
FS0, FS1 and FS2 have internal pull up (high by default) while FS3 has
internal pull down (low by default).
PCI_F, PCI(0:4)
7,8,10,11,12, 13
O
PCI clocks with frequencies defined by Frequency Table. These pins
except PCI_F will be LOW when PCI_STOP is LOW.
CPU_F, CPU1
44,43
O
CPU clocks with frequencies defined by Frequency Table.
SDRAM (0:11),
SDRAM_F
38,37,35,34,32,
31,29,28,21,20,
18,17,40
O
3.3V SDRAM Clocks with frequencies defined in Frequency Selection
table. SDRAM_F is free running output.
SDATA
23
B
SCLK
24
I
Serial data input for serial interface port.
REF0//PCI_STOP
2
B
Multiplexed pin controlled by MODE signal. PCI_STOP will stop PCI
clock except PCI_F when LOW.
WDRESET
41
O
This pin is an open drain output. Will be Low at watchdog timer
expiration.
PCI_F/MODE
7
B
At power-on, MODE function will be activated. When MODE is Low, Pin
2 is input for PCI_STOP. When high, Pin2 is output for REF0. After input
data latched, this pin will generate free running PCI bus clock.
48MHz
26
B
48MHz output for USB after input data latched during power-on.
24MHz
25
B
24MHz output for SUPER I/O after input data latched during power-on.
REF1/FS2
46
B
Buffered reference clock output after input data latched during power-on.
SDRAMIN
15
I
Buffer input pin: The signal provided to this input pin is buffered to 13
SDRAM outputs.
IOAPIC
47
O
2.5V Buffered reference clock.
PLL202-11
Motherboard Clock Generator for 440BX Type with 133MHz FSB
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 10/19/00 Page 3
POWER MANAGEMENT
PCI_SOTP
CPU1
PCI
PCI_F,CPU_F,SDRAM_F
SDRAM
IOAPIC
XTAL,VCO
1
Running
Running
Running
Running
Running
Running
0
Running
Low
Running
Running
Running
Running
FREQUENCY (MHz) SELECTION TABLE
I2C
Byte0
Bit2
FS3
FS2
FS1
FS0
CPU
PCI
0
0
0
0
80
40.0
0
0
0
1
75
37.5
0
0
1
0
83.3
41.7
0
0
1
1
66.8
33.4
0
1
0
0
103
34.3
0
1
0
1
112
37.3
0
1
1
0
68
34.0
0
1
1
1
100.2
33.4
1
0
0
0
120
40.0
1
0
0
1
115
38.3
1
0
1
0
110
36.3
1
0
1
1
105
35.0
1
1
0
0
140
35.0
1
1
0
1
150
37.5
1
1
1
0
124
31.0
0
(default)
1
1
1
1
133.3
33.3
0
0
0
0
135
33.8
0
0
0
1
130
32.5
0
0
1
0
126
31.5
0
0
1
1
118
39.3
0
1
0
0
116
38.4
0
1
0
1
95
31.7
0
1
1
0
90
30.0
0
1
1
1
85
28.3
1
0
0
0
166
41.5
1
0
0
1
160
40.0
1
0
1
0
155
38.8
1
0
1
1
148
37.0
1
1
0
0
146
36.5
1
1
0
1
144
36.0
1
1
1
0
142
35.5
1
1
1
1
1
138
34.5
PLL202-11
Motherboard Clock Generator for 440BX Type with 133MHz FSB
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 10/19/00 Page 4
I2C BUS CONFIGURATION SETTING
Address Assignment
A6 A5 A4 A3 A2 A1 A0 R/W
1 1 0 1 0 0 1 _
Slave
Receiver/Transmitter
Provides both slave write and readback functionality
Data Transfer Rate
Standard mode at 100kbits/s
Serial Bits Reading
The serial bits will be read or sent by the clock driver in the following order
Byte 0 Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 Bits 7, 6, 5, 4, 3, 2, 1, 0
-
Byte N Bits 7, 6, 5, 4, 3, 2, 1, 0
Data Protocol
This serial protocol is designed to allow both blocks write and read from the controller. The
bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred
must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will
terminate the transfer. The write or read block both begins with the master sending a slave
address and a write condition (0xD2) or a read condition (0xD3).
Following the acknowledge of this address byte, in
Write Mode: the Command Byte and Byte
Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte
Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at
power-up is = (0x09).
I2C CONTROL REGISTERS
1. BYTE 0: Functional and Frequency Select Clock Register (1=Enable, 0=Disable)
Bit
Pin#
Default
Description
Bit 7
8
0
FS3 ( see Frequency selection Table )
Bit 6
46
0
FS2 ( see Frequency selection Table )
Bit 5
25
0
FS1 ( see Frequency selection Table )
Bit 4
26
0
FS0 ( see Frequency selection Table )
Bit 3
-
0
Frequency selection control bit 1=Via I2C, 0=Via External jumper
Bit 2
-
0
I2C Selection ( see Frequency selection Table )
Bit 1
-
1
0=Normal 1=Spread Spectrum enable,
0.25% Center Spread
Bit 0
-
0
0=Normal 1=Tristate Mode for all outputs
PLL202-11
Motherboard Clock Generator for 440BX Type with 133MHz FSB
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 10/19/00 Page 5
2. BYTE 1: CPU Clock Register (1=Enable, 0=Disable)
Bit
Pin#
Default
Description
Bit 7
46
X
Inverted Power on latched FS2 value (Read only)
Bit 6
-
1
Reserved
Bit 5
-
1
Reserved
Bit 4
-
1
Reserved
Bit 3
40
1
SDRAM_F ( Active/Inactive )
Bit 2
-
1
Reserved
Bit 1
43
1
CPU1 ( Active/Inactive )
Bit 0
44
1
CPU_F (Active/Inactive)
3. BYTE 2: PCI Clock Register (1=Enable, 0=Disable)
Bit
Pin#
Default
Description
Bit 7
-
1
Reserved
Bit 6
7
1
PCI_F ( Active/Inactive )
Bit 5
-
1
Reserved
Bit 4
13
1
PCI4 ( Active/Inactive )
Bit 3
12
1
PCI3 ( Active/Inactive )
Bit 2
11
1
PCI2 ( Active/Inactive )
Bit 1
10
1
PCI1 ( Active/Inactive )
Bit 0
8
1
PCI0 ( Active/Inactive )
4. BYTE 3: SDRAM Clock Register (1=Enable, 0=Disable)
Bit
Pin#
Default
Description
Bit 7
-
1
Reserved
Bit 6
26
X
Inverted Power on latched FS0 value (Read only)
Bit 5
26
1
48MHz
Bit 4
25
1
24MHz
Bit 3
-
1
Reserved
Bit 2
21,20,18,17
1
SDRAM ( 8:11 ) ( Active/Inactive )
Bit 1
32,31,29,28
1
SDRAM ( 4:7 ) ( Active/Inactive )
Bit 0
38,37,35,34
1
SDRAM ( 0:3 ) ( Active/Inactive )
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