47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/10/01 Page 1
Clock frequency generator for VIA Pentium4
chipsets.
Provides 1 REF clock, 3 CPU (including one at
2.5V for the Chipset), 3 AGP, and 9 PCI clocks.
One 48MHz clock, one 24_48MHz clock.
Enhanced PCI Output Drive selectable by I2C.
Two 2.5V APIC and one 14.318MHz ref. Clocks.
Power management control for CPU and PCI.
Single byte micro-step linear Frequency
Programming via I2C with glitch free smooth
switching.
Built-in programmable watchdog timer up to 63
seconds with 1-second interval. It will generate a
low reset output when timer expired, with
programmable WD reset frequency.
Spread Spectrum
0.25% center,
0.5% center,
0.75% center.
50% duty cycle with low jitter.
Available in 300 mil 48 pin SSOP.
Note: ^: Pull up
v
: Pull down #: Active low **: 2x drive strength
3.3V: VDD and VDDCPU for REF, XIN, XOUT,
PLL CORE, PCI, AGP, APIC, CPUT(0:1), and
CPUC(0:1)
2.5V: VDD_APIC and VDD_CPU_CS for
CPUC_CS and CPUT_CS
CPU Cycle to Cycle jitter: 250ps.
PCI Cycle to Cycle jitter: 500ps.
PCI to PCI skew: 500ps.
CPU to CPU skew 175ps.
CPU to PCI skew (CPU lead): typical 2ns.
AGP to AGP skew: 250ps.
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47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/10/01 Page 2
Name Number
Type
Description
SEL24_48/REF 1 B
Bi-directional pin. At power-up, the SEL24_48 input value is sensed and
internally latched. 0 = 24MHz, 1 = 48MHz. After power-up, the pin acts
as 3.3V REF 14.318MHz output (2x drive strength). This pin has a
100k
internal pull-down.
XIN
4
I
14.318Mhz crystal input to be connected to one end of the crystal.
XOUT
5
O
14.318Mhz crystal output.
FS3/48MHz 7 B
Bi-directional pin. At power-up, the FS3 input value is sensed and
internally latched. After power-up, the pin acts as fixed 48MHz output.
This pin has a 100k
internal pull-down.
FS2/24_48MHz 8 B
Bi-directional pin. At power-up, the FS2 input value is sensed and
internally latched. After power-up, the pin acts as fixed 48 or 24MHz
output (I2C selectable). This pin has a 100k
internal pull-down.
FS0/PCI_F 10 B
Bi-directional pin. At power-up, the FS0 input value is sensed and
internally latched. After power-up, the pin acts as PCI_F output. This pin
has a 100k
internal pull-up.
FS1/PCI0 11
B
Bi-directional pin. At power-up, the FS1 input value is sensed and
internally latched. After power-up, the pin acts as PCI1 output. This pin
has a 100k
internal pull-down.
MULT_SEL1/PCI1 12 B
Bi-directional pin. At power-up, the MULT_SEL1 input value is sensed
and internally latched. After power-up, the pin acts as PCI1 output.
MULT_SEL1 is used to define the current multiplier of the CPU clock
outputs. 0 selects Ioh = 4 x IREF, 1 selects Ioh = 6 x IREF. This pin has
a 100k
internal pull-up.
PCI(2:7)
14,15,17,
18,19,21
O
PCI clock outputs.
PD# 22
I
Power Down Control input. When low, Power Down will disable all clock
outputs including internal VCO and crystal clock. This pin has a 100k
internal pull-up.
AGP(0:2)
23,26,27
O
AGP clock outputs.
SCLK 28
B
SDATA 29
I
Serial data input for serial interface port.
WDRESET#
30
O
Watchdog timer reset signal.
PCI_STOP# 31 I
Halts PCI clocks when low (except PCI_F which is free running). This pin
has a 100k
internal pull-up.
CPU_STOP# 32 I
Halts CPU clocks when input low. This pin has a 100k
internal pull-up
Vtt_PWRG# 33 I
This 3.3V LVTTL input is a level sensitive strobe used to determine
when FS (0:3) and MULT_SEL1 inputs are valid and ready to be
sampled (active low).
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/10/01 Page 3
CPUT(0:1)
35,40
O
True clock of differential pair of CPU outputs.
CPUC(0:1)
34,39
O
Complementary clock of differential pair of CPU outputs.
IREF 37
I
This pin establishes the reference current for the CPU pairs, it requires a
fixed precision resistor tied to ground in order to establish the
appropriate current.
CPUT_CS
42
O
True CPU output for the Chipset (2.5V push-pull output).
CPUC_CS
41
O
Complementary CPU output for the Chipset (2.5V push-pull output).
APIC(0:1)
45,46
O
APIC clock outputs running at half of PCI output frequency.
VDD
2,6,16,24,38,48
P
3.3V Power Supply.
VDD_CPU_CS
43
P
2.5V Power Supply for CPUT_CS and CPUC_CS outputs.
VDD_APIC
48
P
2.5V Power Supply for APIC outputs.
GND
3,9,13,20,
25,36,44,47
P
Ground (0.0V) connector.
MULT_SEL1 Board target trace (Z) Reference R (Rr); IREF = VDD/(3*Rr) Output Current
Voh @ Z
0
50
Rr = 221
(1%); IREF = 5.00mA
Ioh = 4 x IREF
1.0V @ 50
1
50
Rr = 475
(1%); IREF = 2.32mA
Ioh = 6 x IREF
0.7V @ 50
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/10/01 Page 4
! "
FS4 FS3 FS2 FS1 FS0
CPU
AGP
PCI
Spread
Spectrum
0 0 0 0 0 66.67
66.66
33.33
0.25%
0 0 0 0 1
100
66.67
33.33
0.25%
0 0 0 1 0 133.33
66.67
33.33
0.25%
0 0 0 1 1
200
66.66
33.33
0.25%
0 0 1 0 0 100.9
67.27
33.63
0.25%
0 0 1 0 1
103
68.67
34.33
0.25%
0 0 1 1 0
107
71.33
35.67
0.25%
0 0 1 1 1
110
73.33
36.67
0.25%
0 1 0 0 0 133.9
66.95
33.48
0.25%
0 1 0 0 1 137.33
68.66
34.33
0.25%
0 1 0 1 0
140
70
35
0.25%
0 1 0 1 1 142.66
71.33
35.67
0.25%
0 1 1 0 0 145.33
72.66
36.33
0.25%
0 1 1 0 1 146.66
73.33
36.67
0.25%
0 1 1 1 0 153.33
76.66
38.33
0.25%
0 1 1 1 1
160
80
40
0.25%
1 0 0 0 0 66.67
66.66
33.33
0.50%
1 0 0 0 1
100
66.67
33.33
0.50%
1 0 0 1 0 133.33
66.67
33.33
0.50%
1 0 0 1 1
200
66.66
33.33
0.50%
1 0 1 0 0 66.67
66.66
33.33
0.75%
1 0 1 0 1
100
66.67
33.33
0.75%
1 0 1 1 0 133.33
66.67
33.33
0.75%
1 0 1 1 1
200
66.66
33.33
0.75%
1 1 0 0 0
201
67
35.5
0.25%
1 1 0 0 1
203
67.67
33.83
0.25%
1 1 0 1 0
205
68.33
34.17
0.25%
1 1 0 1 1
207
69
34.5
0.25%
1 1 1 0 0 66.66 66.66 33.33
0.25%
1 1 1 0 1
100 66.66 33.33
0.25%
1 1 1 1 0
200 66.66 33.33
0.25%
1 1 1 1 1 133.3 66.66 33.33
0.25%
Note: FS4 available through I2C only
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/10/01 Page 5
#$%&'$(
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1. When Power-Down (PD#) is sampled low by two consecutive rising edges of CPUC clock, then all clock outputs
must be held low on their next high to low transition (except CPUT which must be driven high with a value of 2 x
IREF).
2. After the clocks have all been stopped, the internal PLL stages and the Crystal oscillator will all be driven to a low
power stopped condition.
PD# assertion (Transition from Logic '1' to Logic '0')
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1. Power-Down (PD#) pin is taken from Low to High transition to return to normal running operation.
2. The Crystal Oscillator and the two PLL stages are released from PD to start-up to normal operation.
3. The CPU PLL clocks (differential CPU outputs) are then operating.
4. After the PCI clocks are released.
5. Following the 48 MHz (DOT and USB clocks) and the REF ( 14.318MHz) clocks are released.
PD# de-assertion (Transition from Logic '0' to Logic '1')
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-23
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