PLL203-01
Motherboard Clock Generator for 815 with 133MHz FSB
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/01/00 Page 1
Generates all clock frequencies for INTEL 815
Chip sets.
Supports 2 CPU clocks, 9 high-speed SDRAM
clocks for 2-DIMM applications and 7 PCI clocks.
Three 3.3V 3V66MHz clocks.
One 24/48MHz clock and two 48MHz clocks.
One double-strength 2.5V IOAPIC clock.
One double-strength 14.318MHz reference
clock.
Support 2-wire I2C serial bus interface with built-
in Vendor ID, Device ID and Revision ID.
Single byte micro-step linear Frequency
programming via I2C with glitch free and smooth
switching.
Spread Spectrum
0.25% center spread, 0 to
0.5% downspread.
50% duty cycle with low jitter.
Available in 300 mil 48 pin SSOP.
BLOCK DIAGRAM
PIN CONFIGURATION
Note: v: pull down,
^
:
Pull up,
#: Active low,
*
: Bi-directional latched at power-up
POWER GROUP
VDD1: REF, XIN, XOUT, PLL CORE
VDD2: 3V66(0:2)
VDD3: PCI(0:6)
VDD4: 48MHz_0, 48MHz_1 & 24_48MHz
VDD5: SDRAM(0:7)& SDRAM_F
VDDL1: IOAPIC
VDDL2: CPU(0:1)
KEY SPECIFICATIONS
Cycle to Cycle jitter:
1)
250ps: CPU, SDRAM
2)
500ps: APIC, 48Mhz, 3V66, PCI
Pin to Pin Skew:
1)
250ps: CPU, 3V66
2)
500ps: SDRAM, APIC, PCI, 48Mhz
Clock Offset (@CPU=100Mhz):
1)
4.5~5.5ns: CPU-SDRAM, CPU-3V66
2)
1.5~3.5ns: 3V66-PCI
3)
-0.5~0.5ns: SDRAM-3V66, PCI-APIC
PD
XIN
XOUT
SDATA
SCLK
FS (0:4)*
XTAL
OSC
I2C
Logic
Control
Logic
VDD1
REFx2
VDDL2
IOAPIC
VDD2
3V66 (0:2)
PCI (0:6)
SDRAM (0:7)
VDDL1
VDD3
VDD5
SDRAM_F
VDD4
48Mhz_0
24_48Mhz
2
48Mhz_1
PLL2
PLL1
SST
CPU (0:1)
PLL203-01
PD#
PCI6
PCI5
VDD3
PCI4
PCI3
PCI2
GND
PCI0x2/FS0
VDD3
3V66_2
3V66_1
3V66_0
GND
XOUT
XIN
VDD1
REFx2/SEL24_48
SDATA
SCLK
GND
VDD2
GND
SDRAM0
SDRAM1
SDRAM2
VDD5
SDRAM3
SDRAM4
SDRAM5
GND
SDRAM6
SDRAM7
VDDL1
IOAPICx2
VDDL2
CPU0
CPU1
GND
SDRAM_F
24_48Mhz/FS2
VDD5
GND
48Mhz_0x2/FS4
VDD4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
41
42
44
43
45
46
47
48
*
PCI1x2/FS1
*
v
GND
48Mhz_1/FS3
v
*
^
*
^
*
^
*
^
PLL203-01
Motherboard Clock Generator for 815 with 133MHz FSB
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/01/00 Page 2
PIN DESCRIPTIONS
Name
Number
Type
Description
REFx2/SEL24_48
1
B
At power up, this pin will select 24MHz (when high) or 48MHz (when low)
for pin 28 output. After input sampling, this pin is double strength REF
output. This pin has internal pull-up resistor.
XIN
3
I
14.318Mhz crystal input to be connected to one end of the crystal.
XOUT
4
O
14.318Mhz crystal output.
3V66(0:2)
7,8,9
O
66MHz clock output. (See Frequency Selection table on page3).
SDRAM(0:7),
SDRAM_F
41,40,39,37,
36,35,33,32,31
O
3.3V SDRAM Clocks with frequencies defined in Frequency Selection
table. SDRAM_F is free running clock output.
PCI0x2/FS0,
PCI1x2/FS1
12,13
B
PCI clock output. These pins latch FS(0:1) value at power-on. (See
Frequency Selection table on page 3). FS0 has internal pull up resistor,
while FS1 has internal pull down resistor.
PCI(2:6)
15,16,17,19,20
O
PCI bus clock output. (See Frequency Selection table on page 3)
48MHz_0x2/FS4
26
B
Double strength 48MHz clock output. This pin latches FS4 value at power-
on. (See Frequency selection table on page3). This pin has internal pull
up resistor.
48MHz_1/FS3
27
B
48MHz clock output. This pin latches FS3 value at power-on. (See
Frequency selection table on page3). This pin has internal pull up
resistor.
24_48MHz/FS2
28
B
At power up, this pin is input pin and will determine the CPU clock
frequency. It has internal pull down resistor.
SDATA
24
B
SCLK
23
I
Serial data inputs for serial interface port (I2C).
PD#
22
I
Power Down Control input. When low, it will disable all clock outputs
including internal VCO and crystal clock.
CPU(0:1)
45,44
O
2.5V CPU Clocks with frequencies defined in Frequency Selection table
on page3.
IOAPICx2
47
O
2.5V double strength IOAPIC clock output.
VDD1
2
P
Power supply for REF, crystal oscillator, PLL Core.
VDD2
10
P
Power supply for 3V66(0:2).
VDD3
11,18
P
Power supply for PCI (0:6).
VDD4
25
P
Power supply for 48MHz or 24_48MHz.
VDD5
30,38
P
Power supply for SDRAM (0:7), SDRAM_F.
VDDL1
48
P
Power supply for IOAPIC 2.5V.
VDDL2
46
P
Power supply for CPU (0:1) 2.5V.
GND
5,6,14,21,29,
34,42,43
P
Ground.
PLL203-01
Motherboard Clock Generator for 815 with 133MHz FSB
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/01/00 Page 3
FREQUENCY (MHz) SELECTION TABLE
I2C
Byte0
Bit2
FS3
FS2
FS1
FS0
CPU
SDRAM
3V66
PCI
IOAPIC
Spread
Spectrum
Modulation
0
0
0
0
66.6
100.0
66.6
33.3
16.6
0 to -0.5%
0
0
0
1
66.8
100.3
66.8
33.4
16.7
0.25%
0
0
1
0
68.6
103.0
68.6
34.3
17.1
0.25%
0
0
1
1
71.3
107.0
71.3
35.6
17.8
0.25%
0
1
0
0
100.0
100.0
66.6
33.3
16.6
0 to -0.5%
0
1
0
1
100.3
100.3
66.8
33.4
16.7
0.25%
0
1
1
0
103.0
103.0
68.6
34.3
17.1
0.25%
0
1
1
1
107.0
107.0
71.3
35.6
17.8
0.25%
1
0
0
0
133.3
133.3
66.6
33.3
16.6
0 to -0.5%
1
0
0
1
133.7
133.7
66.8
33.4
16.7
0.25%
1
0
1
0
137.3
137.3
68.6
34.3
17.1
0.25%
1
0
1
1
120.0
120.0
60.0
30.0
15.0
0.25%
1
1
0
0
133.3
100.0
66.6
33.3
16.6
0 to -0.5%
1
1
0
1
133.7
100.3
66.8
33.4
16.7
0.25%
1
1
1
0
137.3
103.0
68.6
34.3
17.1
0.25%
0
default
1
1
1
1
120.0
90.0
60.0
30.0
15.0
0.25%
0
0
0
0
136.0
136.0
68.0
34.0
17.0
0.25%
0
0
0
1
140.0
140.0
70.0
35.0
17.5
0.25%
0
0
1
0
142.6
142.6
71.3
35.6
17.8
0.25%
0
0
1
1
145.3
145.3
72.6
36.3
18.1
0.25%
0
1
0
0
136.0
102.0
68.0
34.0
17.0
0.25%
0
1
0
1
140.0
105.0
70.0
35.0
17.5
0.25%
0
1
1
0
142.6
107.0
71.3
35.6
17.8
0.25%
0
1
1
1
145.3
109.0
72.6
36.3
18.1
0.25%
1
0
0
0
146.6
146.6
73.3
36.6
18.3
0.25%
1
0
0
1
153.3
153.3
76.6
38.3
19.1
0.25%
1
0
1
0
160.0
160.0
80.0
40.0
20.0
0.25%
1
0
1
1
166.6
166.6
83.3
41.6
20.8
0.25%
1
1
0
0
146.6
110.0
73.3
36.6
18.3
0.25%
1
1
0
1
160.0
120.0
80.0
40.0
20.0
0.25%
1
1
1
0
166.6
125.0
83.3
41.6
20.8
0.25%
1
1
1
1
1
200.0
200.0
100.0
50.0
25.0
0.25%
PLL203-01
Motherboard Clock Generator for 815 with 133MHz FSB
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/01/00 Page 4
FREQUENCY (MHz) SELECTION TABLE BY GROUP TIMING
Group Timing
(CPU:SDRAM:3V66)
FS4
FS3
FS2
FS1
FS0
CPU
SDRAM
3V66
PCI
IOAPIC
0
0
0
0
0
66.6
100.0
66.6
33.3
16.6
0
0
0
0
1
66.8
100.3
66.8
33.4
16.7
0
0
0
1
0
68.6
103.0
68.6
34.3
17.1
A
(66:100:66)
0
0
0
1
1
71.3
107.0
71.3
35.6
17.8
0
0
1
0
0
100.0
100.0
66.6
33.3
16.6
0
0
1
0
1
100.3
100.3
66.8
33.4
16.7
0
0
1
1
0
103.0
103.0
68.6
34.3
17.1
B
(100:100:66)
0
0
1
1
1
107.0
107.0
71.3
35.6
17.8
0
1
0
1
1
120.0
120.0
60.0
30.0
15.0
0
1
0
0
0
133.3
133.3
66.6
33.3
16.6
0
1
0
0
1
133.7
133.7
66.8
33.4
16.7
1
0
0
0
0
136.0
136.0
68.0
34.0
17.0
0
1
0
1
0
137.3
137.3
68.6
34.3
17.1
1
0
0
0
1
140.0
140.0
70.0
35.0
17.5
1
0
0
1
0
142.6
142.6
71.3
35.6
17.8
1
0
0
1
1
145.3
145.3
72.6
36.3
18.7
1
1
0
0
0
146.6
146.6
73.3
36.6
18.3
1
1
0
0
1
153.3
153.3
76.6
38.3
19.1
1
1
0
1
0
160.0
160.0
80.0
40.0
20.0
1
1
0
1
1
166.6
166.6
83.3
41.6
20.8
C
(133:133:66)
1
1
1
1
1
200.0
200.0
100.0
50.0
25.0
0
1
1
1
1
120.0
90.0
60.0
30.0
15.0
0
1
1
0
0
133.3
100.0
66.6
33.3
16.6
0
1
1
0
1
133.7
100.3
66.8
33.4
16.7
0
1
1
1
0
137.3
103.0
68.6
34.3
17.1
1
0
1
0
0
136.0
102.0
68.0
34.0
17.0
1
0
1
0
1
140.0
105.0
70.0
35.0
17.5
1
0
1
1
0
142.6
107.0
71.3
35.6
17.8
1
0
1
1
1
145.3
109.0
72.6
36.3
18.1
1
1
1
0
0
146.6
110.0
73.3
36.6
18.3
1
1
1
0
1
160.0
120.0
80.0
40.0
20.0
D
(133:100:66)
1
1
1
1
0
166.6
125.0
83.3
41.6
20.8
PLL203-01
Motherboard Clock Generator for 815 with 133MHz FSB
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/01/00 Page 5
GROUP OFFSET TIMING RELATIONSHIP
Cycle Repeats
0ns
10ns
20ns
30ns
40ns
CPU 133MHz
SDRAM 100MHz
3V66 66MHz
0.0ns
0.0ns
0.0ns
Group D
CPU 66MHz
SDRAM 100MHz
3V66 66MHz
Cycle Repeats
0ns
10ns
20ns
30ns
40ns
Cycle Repeats
0ns
10ns
20ns
30ns
40ns
CPU 100MHz
SDRAM 100MHz
3V66 66MHz
7.5ns
2.5ns
0.0ns
5.0ns
5.0ns
0.0ns
Group A
Group B
Cycle Repeats
0ns
10ns
20ns
30ns
40ns
CPU 133MHz
SDRAM 133MHz
3V66 66MHz
0.0ns
0.0ns
Group C
3.75ns
3.75ns
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