ChipFind - документация

Электронный компонент: PLL203-61

Скачать:  PDF   ZIP
PLL203-61
Programmable Clock Generator for 815 with 133MHz FSB
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/13/00 Page 1
FEATURES
Generates all clock frequencies for INTEL 815
Chip sets.
Supports 2 CPU clocks, 13 high-speed SDRAM
clocks for 3-DIMM applications and 8 PCI clocks.
Three 3V66MHz clocks and one 2.5v APIC clock.
One 24MHz clock and one 48MHz clock.
One double strength 14.318MHz reference clock.
Support 2-wire I2C serial bus with built-in
Vendor ID, Device ID and Revision ID.
Single byte micro-step linear Frequency
programming via I2C with glitch free and smooth
switching.
Built-in programmable watchdog timer up to 63
seconds with 1-second interval. It will generate a
LOW reset output when timer expired.
Spread Spectrum
0.25% center spread.
50% duty cycle with low jitter.
Available in 300 mil 56 pin SSOP.
BLOCK DIAGRAM
PIN CONFIGURATION
Note:
^
:
Pull up,
#: Active low,
*
: Bi-directional latched at power-up
POWER GROUP
VDD1: REF, XIN, XOUT, PLL CORE
VDD2: 3V66(0:2)
VDD3: PCI(0:7)
VDD4: 48MHz or 24_48MHz
VDD5: SDRAM(0:11)& SDRAM_F
VDDL1: APIC
VDDL2: CPU(0:1)
KEY SPECIFICATIONS
Cycle to Cycle jitter:
1)
250ps: CPU, SDRAM
2)
500ps: APIC, 48Mhz, 3V66, PCI
Pin to Pin Skew:
1)
250ps: CPU, 3V66
2)
500ps: SDRAM, APIC, PCI, 48Mhz
Clock Offset (@CPU=100Mhz):
1)
4.5~5.5ns: CPU-SDRAM, CPU-3V66
2)
1.5~3.5ns: 3V66-PCI
3)
-0.5~0.5ns: SDRAM-3V66, PCI-APIC
PLL203-61
PD#/WDRESET#
PCI7
PCI6
VDD3
PCI5
PCI4
PCI3
GND
PCI2/SIO
PCI1x2/FS1
PCI0x2/FS0
VDD2
3V66_2
3V66_1
3V66_0
GND
GND
XOUT
XIN
VDD1
GND
SDRAM10
SDRAM11
VDD5
SDATA
SCLK
GND
VDD3
*
^
*
^
GND
SDRAM0
SDRAM1
SDRAM2
VDD5
SDRAM3
SDRAM4
SDRAM5
GND
SDRAM6
SDRAM7
REFx2/FS4
*
^
VDDL1
APIC
VDDL2
CPU0
CPU1
GND
SDRAM_F
24_48MHzx2/FS2
VDD5
GND
48Mhzx2/FS3
*
^
GND
SDRAM9
SDRAM8
VDD5
VDD4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
49
50
52
51
53
54
55
56
*
^
*
^
XIN
XOUT
SDATA
SCLK
XTAL
OSC
Control
Logic
VDD1
REFx2
VDDL2
CPU (0:1)
APIC
VDD2
3V66 (0:2)
PCI (0:7)
VDDL1
VDD3
SDRAM_F
FS (0:4)*
PLL1
SST
I2C
Logic
WATCH
DOG
SDRAM (0:11)
VDD5
WDRESET#
PLL2
24_48Mhz
VDD4
48Mhz
2
SIO
PLL203-61
Programmable Clock Generator for 815 with 133MHz FSB
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/13/00 Page 2
PIN DESCRIPTIONS
Name
Number
Type
Description
REFX2/FS4
56
B
Reference 14.318Mhz Clock with 2x Drive strength. This pin latches in
FS4 value at power-up. (See Frequency Selection table on page 3).
XIN
2
I
14.318 Mhz crystal input to be connected to one end of the crystal.
XOUT
3
O
14.318 Mhz crystal output.
3V66(0:2)
6,7,8
O
66MHz clock output. (See Frequency Selection table on page3).
SDRAM(0:11),
SDRAM_F
48,47,46,44,
43,42,40,39,
31,30,27,26,38
O
3.3V SDRAM Clocks with frequencies defined in Frequency Selection
table. SDRAM_F is free running clock output.
PCI0X2/FS0,
PCI1X2/FS1
11,12
B
PCI clock output with 2X drive strength. These pins latch FS(0:1) value at
power-up. (See Frequency Selection table on page 3). These pins have
internal pull up resistors.
PCI(3:7)
15,16,
17,19,20
O
PCI bus clock output. (See Frequency Selection table on page 3)
PCI2/SIO
13
B
At power-up, SIO function will be activated. When SIO is Low, the output
frequency of pin35 is 48MHz. When High, Pin35 is 24MHz. After input
data latched, this pin is PCI clock output. Has internal pull up resistor.
48MHzX2/FS3
34
B
48MHz Clock output with 2X drive strength. This pin latches FS3 value at
power-up. (See Frequency selection table on page3). This pin has internal
pull up resistor.
24_48MHzx2/FS2
35
B
24 or 48MHz Clock output with 2X drive strength. This pin latches FS2
value at power-up. (See Frequency selection table on page3). This pin
has internal pull up resistor.
SDATA
24
B
SCLK
23
I
Serial data inputs for serial interface port.
PD# /
WDRESET#
22
B
Power Down Control input. When low, it will disable all clock outputs
including internal VCO and crystal clock. The enable of the watchdog
timer masks the PD action.
CPU(0:1)
52,51
O
2.5V CPU Clocks with frequencies defined in Frequency Selection table
on page3.
APIC
54
O
2.5V APIC Clock output running Synchronous with PCI/2 clock output.
VDD1
1
P
Power supply for REF, crystal oscillator, PLL Core.
VDD2
9
P
Power supply for 3V66(0:2).
VDD3
10,18
P
Power supply for PCI (0:7).
VDD4
33
P
Power supply for 48MHz or 24MHz.
VDD5
25,32,37,45
P
Power supply for SDRAM (0:11), SDRAM_F.
VDDL1
55
P
Power supply for APIC 2.5V.
VDDL2
53
P
Power supply for CPU (0:1) 2.5V.
GND
4,5,14,21,28,
29,36,41,49,50
P
Ground.
PLL203-61
Programmable Clock Generator for 815 with 133MHz FSB
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/13/00 Page 3
FREQUENCY (MHz) SELECTION TABLE
FS4
FS3
FS2
FS1
FS0
CPU
SDRAM
3V66
PCI
APIC
0
0
0
0
0
55.0
82.5
55.0
27.5
13.8
0
0
0
0
1
60.0
90.0
60.0
30.0
15.0
0
0
0
1
0
66.8
100.2
66.8
33.4
16.7
0
0
0
1
1
68.3
102.5
68.3
34.0
17.1
0
0
1
0
0
70.0
105.0
70.0
35.0
17.5
0
0
1
0
1
72.0
108.0
72.0
36.0
18.0
0
0
1
1
0
75.0
112.5
75.0
37.5
18.8
0
0
1
1
1
77.0
115.5
77.0
38.5
19.3
0
1
0
0
0
83.3
83.3
55.5
27.8
13.9
0
1
0
0
1
90.0
90.0
60.0
30.0
15.0
0
1
0
1
0
100.3
100.3
66.9
33.4
16.7
0
1
0
1
1
103.0
103.0
68.7
34.3
17.2
0
1
1
0
0
112.5
112.5
75.0
37.5
18.8
0
1
1
0
1
115.0
115.0
76.7
38.3
19.2
0
1
1
1
0
120.0
120.0
80.0
40.0
20.0
0
1
1
1
1
125.0
125.0
83.3
41.7
20.8
1
0
0
0
0
128.0
128.0
64.0
32.0
16.0
1
0
0
0
1
130.0
130.0
65.0
32.5
16.3
1
0
0
1
0
133.7
133.7
66.9
33.4
16.7
1
0
0
1
1
137.0
137.0
68.5
34.3
17.1
1
0
1
0
0
140.0
140.0
70.0
35.0
17.5
1
0
1
0
1
145.0
145.0
72.5
36.3
18.1
1
0
1
1
0
150.0
150.0
75.0
37.5
18.8
1
0
1
1
1
153.3
153.3
76.7
38.3
19.2
1
1
0
0
0
125.0
93.8
62.5
31.3
15.6
1
1
0
0
1
130.0
97.5
65.0
32.5
16.3
1
1
0
1
0
133.7
100.3
66.9
33.4
16.7
1
1
0
1
1
137.0
102.8
68.5
34.3
17.1
1
1
1
0
0
140.0
105.0
70.0
35.0
17.5
1
1
1
0
1
145.0
108.8
72.5
36.3
18.1
1
1
1
1
0
150.0
112.5
75.0
37.5
18.8
1
1
1
1
1
153.3
115.0
76.7
38.3
19.2
PLL203-61
Programmable Clock Generator for 815 with 133MHz FSB
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/13/00 Page 4
FREQUENCY (MHz) SELECTION TABLE BY GROUP TIMING
Group Timing
(CPU:SDRAM:3V66)
FS4
FS3
FS2
FS1
FS0
CPU
SDRAM
3V66
PCI
APIC
0
0
0
0
0
55.0
82.5
55.0
27.5
13.8
0
0
0
0
1
60.0
90.0
60.0
30.0
15.0
0
0
0
1
0
66.8
100.2
66.8
33.4
16.7
0
0
0
1
1
68.3
102.5
68.3
34.0
17.1
0
0
1
0
0
70.0
105.0
70.0
35.0
17.5
0
0
1
0
1
72.0
108.0
72.0
36.0
18.0
0
0
1
1
0
75.0
112.5
75.0
37.5
18.8
A
(66:100:66)
0
0
1
1
1
77.0
115.5
77.0
38.5
19.3
0
1
0
0
0
83.3
83.3
55.5
27.8
13.9
0
1
0
0
1
90.0
90.0
60.0
30.0
15.0
0
1
0
1
0
100.3
100.3
66.9
33.4
16.7
0
1
0
1
1
103.0
103.0
68.7
34.3
17.2
0
1
1
0
0
112.5
112.5
75.0
37.5
18.8
0
1
1
0
1
115.0
115.0
76.7
38.3
19.2
0
1
1
1
0
120.0
120.0
80.0
40.0
20.0
B
(100:100:66)
0
1
1
1
1
125.0
125.0
83.3
41.7
20.8
1
0
0
0
0
128.0
128.0
64.0
32.0
16.0
1
0
0
0
1
130.0
130.0
65.0
32.5
16.3
1
0
0
1
0
133.7
133.7
66.9
33.4
16.7
1
0
0
1
1
137.0
137.0
68.5
34.3
17.1
1
0
1
0
0
140.0
140.0
70.0
35.0
17.5
1
0
1
0
1
145.0
145.0
72.5
36.3
18.1
1
0
1
1
0
150.0
150.0
75.0
37.5
18.8
C
(133:133:66)
1
0
1
1
1
153.3
153.3
76.7
38.3
19.2
1
1
0
0
0
125.0
93.8
62.5
31.3
15.6
1
1
0
0
1
130.0
97.5
65.0
32.5
16.3
1
1
0
1
0
133.7
100.3
66.9
33.4
16.7
1
1
0
1
1
137.0
102.8
68.5
34.3
17.1
1
1
1
0
0
140.0
105.0
70.0
35.0
17.5
1
1
1
0
1
145.0
108.8
72.5
36.3
18.1
1
1
1
1
0
150.0
112.5
75.0
37.5
18.8
D
(133:100:66)
1
1
1
1
1
153.3
115.0
76.7
38.3
19.2
PLL203-61
Programmable Clock Generator for 815 with 133MHz FSB
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/13/00 Page 5
GROUP OFFSET TIMING RELATIONSHIP
Cycle Repeats
0ns
10ns
20ns
30ns
40ns
CPU 133MHz
SDRAM 100MHz
3V66 66MHz
0.0ns
0.0ns
0.0ns
Group D
CPU 66MHz
SDRAM 100MHz
3V66 66MHz
Cycle Repeats
0ns
10ns
20ns
30ns
40ns
Cycle Repeats
0ns
10ns
20ns
30ns
40ns
CPU 100MHz
SDRAM 100MHz
3V66 66MHz
7.5ns
2.5ns
0.0ns
5.0ns
5.0ns
0.0ns
Group A
Group B
Cycle Repeats
0ns
10ns
20ns
30ns
40ns
CPU 133MHz
SDRAM 133MHz
3V66 66MHz
0.0ns
0.0ns
Group C
3.75ns
3.75ns