PLL205-03
Motherboard Clock Generator for AMD - K7
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 06/23/00 Page 1
FEATURES
Generates all clock frequencies for VIA K7 chip
sets requiring multiple CPU clocks and high
speed SDRAM buffers.
Support one pair of differential CPU clocks, one
3.3V push-pull CPU clock, 6 PCI and 13 high-
speed SDRAM buffers for 3-DIMM applications.
One 24_48MHz clock and one 48MHz clock.
Two14.318MHz reference clocks.
Power management control to stop CPU, and
Power down Mode from I2C programming.
Support 2-wire I2C serial bus interface with built-
in Vendor ID, Device ID and Revision ID.
Single byte micro-step linear Frequency Progra-
mming via I2C with Glitch free smooth switching.
Enhanced CPU and SDRAM output Drive
selectable by I2C.
Spread Spectrum
0.25% center spread, 0 to
-0.5% downspread.
50% duty cycle with low jitter.
Available in 300 mil 48 pin SSOP.
BLOCK DIAGRAM
PIN CONFIGURATION
Note: ^: Pull up, #: Active Low
*
: Bi-directional latched at power-up
I/O MODE CONFIGURATION
MODE (Pin 7)
PIN 2
1 (OUTPUT)
REF0
0 (INPUT)
CPU_STOP
POWER GROUP
VDD0: PLL CORE
VDD1: REF(0:1), XIN, XOUT
VDD2: PCI(0:5)
VDD3: SDRAM(0:12)
VDD4: 48MHz, 24_48MHz
KEY SPECIFICATIONS
CPU Cycle to Cycle jitter: 250ps.
PCI to PCI output skew: 500ps.
CPU to CPU output skew:
175ps
SDRAM to SDRAM output skew: 250ps.
CPU to PCI skew (CPU leads): 0 ~ 3 ns.
SDRAM12
GND
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PLL205-03
GND
CPUT1
GND
CPUC0
CPUT0
VDD3
VDD3
SDRAM6
SDRAM7
VDD4
SCLK
GND
SDRAMIN
VDD2
GND
VDD1
XOUT
XIN
GND
VDD0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PCI2
PCI3
PCI4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SDRAM8
SDRAM9
VDD3
SDRAM11
GND
SDRAM10
PD#^
REF1/FS2*^
REF0//CPU_STOP#^
PCI5/MODE*^
PCI1/SEL24_48*^
PCI0/FS3*^
24_48MHz/FS1*^
48MHz/FS0*^
VDD2
PCI(0:4)
PCI5
CPUT0
CPUC0
Control
Logic
SDATA
SCLK
I2C
Logic
VDD1
REF(0:1)
XIN
XOUT
XTAL
OSC
SDRAM(0:11)
VDD3
SDRAM12
FS (0:3)*
PLL1
SST
PLL2
PD
48Mhz
VDD4
24_48Mhz
SDRAMIN
2
CPUT1
PLL205-03
Motherboard Clock Generator for AMD - K7
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 06/23/00 Page 2
PIN DESCRIPTIONS
Name
Number
Type
Description
VDD0
1
P
Power supply for PLL CORE.
VDD1
6
P
Power supply for REF0, REF1, and crystal oscillator.
VDD2
14
P
Power supply for PCI (0:5).
VDD3
19,30,36,42
P
Power supply for SDRAM (0:12).
VDD4
27
P
Power supply for 24_48MHz and 48MHz.
GND
3,9,16,22,
33,39,45,47
P
Ground.
XIN
4
I
14.318MHz crystal input that has internal loads cap (36pF) and feedback
resistor from XOUT.
XOUT
5
O
14.318MHz crystal output. It has internal load cap (36pF).
REF0//CPU_STOP
2
B
Multiplexed pin controlled by MODE signal. When CPU_STOP is low, it
will halt CPUT (0:1), CPUC0 and SDRAM (0:11) outputs. In output
mode, this pin will generate buffered reference clock output.
PCI5/MODE
7
B
At power-up, MODE function will be activated. When MODE is Low, Pin
2 is input for CPU_STOP. When high, Pin 2 is output for REF0. After
input data latched, this pin will generate PCI bus clock.
PCI0/FS3
8
B
At power-up, this pin is input pin and will determine CPU clock
frequency. After input sampling, this pin will generate output clocks. FS3
has internal pull up (high by default).
PCI1/SEL24_48
10
B
At power-up, this pin will select 24MHz (when high) or 48MHz (when
low) for pin25 output. After input sampling, this pin is PCI output. It has
internal pull up resistor.
PCI(2:4)
11,12,13
O
PCI clock outputs.
SDRAMIN
15
I
Buffer input pin: The signal provided to this input pin is buffered to 13
SDRAM outputs.
SDRAM(0:11)
17,18,20,21,28,
29,31,32,34,35,
37,38
O
SDRAM clock outputs, Fan-out Buffer outputs from SDRAMIN pin.
SDATA
23
B
SCLK
24
I
Serial data inputs for serial interface port.
24_48MHz/FS1,
24MHz/FS0
25,26
B
At power-up, these pins are input pins and will determine the CPU clock
frequency. FS0, FS1 have internal pull up (high by default).
SDRAM12
40
O
When CPU_STOP is low, this pin is still free running. When the power
down is low, this SDRAM will be stopped.
PD#
41
I
When low, it will stop all clock outputs. It has internal pull-up resistor.
CPUT0
43
O
"True" clock of differential pair open-drain CPU output.
CPUC0
44
O
"Complementary" clocks of differential pair open-drain CPU outputs.
CPUT1
46
O
"True" clock of push-pull CPU output.
REF1/FS2
48
B
Buffered reference clock output after input data latched during power-up.
PLL205-03
Motherboard Clock Generator for AMD - K7
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 06/23/00 Page 3
FREQUENCY (MHz) SELECTION TABLE
I2C
Byte0
Bit2
FS3
FS2
FS1
FS0
CPU
PCI
Spread Spectrum
Modulation
0
0
0
0
124.0
41.3
0.25%
0
0
0
1
75.0
37.5
0.25%
0
0
1
0
83.3
41.7
0.25%
0
0
1
1
66.8
33.4
0.25%
0
1
0
0
103.0
34.3
0.25%
0
1
0
1
112.0
37.3
0.25%
0
1
1
0
133.3
44.4
0.25%
0
1
1
1
100.0
33.3
0.25%
1
0
0
0
120.0
40.0
0.25%
1
0
0
1
115.0
38.3
0.25%
1
0
1
0
110.0
36.7
0.25%
1
0
1
1
105.0
35.0
0.25%
1
1
0
0
140.0
35.0
0.25%
1
1
0
1
150.0
37.5
0.25%
1
1
1
0
124.0
31.0
0.25%
0
default
1
1
1
1
133.3
33.3
0.25%
0
0
0
0
90.0
30.0
0.25%
0
0
0
1
92.5
30.8
0.25%
0
0
1
0
95.0
31.7
0.25%
0
0
1
1
97.5
32.5
0.25%
0
1
0
0
101.5
33.8
0.25%
0
1
0
1
127.0
42.3
0.25%
0
1
1
0
136.5
34.1
0.25%
0
1
1
1
100.0
33.3
0 to -0.5%
1
0
0
0
120.0
40.0
0 to -0.5%
1
0
0
1
117.5
39.2
0.25%
1
0
1
0
122.0
40.7
0.25%
1
0
1
1
107.5
35.8
0.25%
1
1
0
0
145.0
36.3
0.25%
1
1
0
1
155.0
38.7
0.25%
1
1
1
0
130.0
32.5
0.25%
1
1
1
1
1
133.3
33.3
0 to -0.5%
POWER MANAGEMENT
CPU_STOP
CPUC0
CPUT (0:1)
SDRAM (0:11)
SDRAM12
CRYSTAL
VCO
0
Stopped Low
Stopped Low
Stopped Low
Running
Running
Running
1
Running
Running
Running
Running
Running
Running
PLL205-03
Motherboard Clock Generator for AMD - K7
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 06/23/00 Page 4
POWER MANAGEMENT (Continued)
PD
CPUC0
CPUT (0:1)
SDRAM (0:11)
SDRAM12
CRYSTAL
VCO
0
Stopped Low
Stopped Low
Stopped Low
Stopped Low
Stopped
Stopped
1
Running
Running
Running
Running
Running
Running
I2C BUS CONFIGURATION SETTING
Address Assignment
A6 A5 A4 A3 A2 A1 A0 R/W
1 1 0 1 0 0 1 _
Slave
Receiver/Transmitter
Provides both slave write and readback functionality
Data Transfer Rate
Standard mode at 100kbits/s
Serial Bits Reading
The serial bits will be read or sent by the clock driver in the following order
Byte 0 Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 Bits 7, 6, 5, 4, 3, 2, 1, 0
-
Byte N Bits 7, 6, 5, 4, 3, 2, 1, 0
Data Protocol
This serial protocol is designed to allow both blocks write and read from the controller. The
bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred
must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will
terminate the transfer. The write or read block both begins with the master sending a slave
address and a write condition (0xD2) or a read condition (0xD3).
Following the acknowledge of this address byte, in
Write Mode: the Command Byte and Byte
Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte
Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at
power-up is = (0x09).
I2C CONTROL REGISTERS
1. BYTE 0: Functional and Frequency Select Clock Register (1=Enable, 0=Disable)
Bit
Pin#
Default
Description
Bit 7
8
0
FS3 ( see Frequency selection Table )
Bit 6
48
1
FS2 ( see Frequency selection Table )
Bit 5
25
0
FS1 ( see Frequency selection Table )
Bit 4
26
0
FS0 ( see Frequency selection Table )
Bit 3
-
0
Frequency selection control bit 1=Via I2C, 0=Via External jumper
Bit 2
-
0
FS4 ( see Frequency selection Table )
Bit 1
-
1
0=Normal 1=Spread Spectrum enable
Bit 0
-
0
0=Normal 1=Tristate Mode for all outputs
PLL205-03
Motherboard Clock Generator for AMD - K7
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 06/23/00 Page 5
BYTE 1: CPU Clock Register (1=Enable, 0=Disable)
Bit
Pin#
Default
Description
Bit 7
-
1
Reserved
Bit 6
17,18,20,21,
28,29,31,32,
34,35,37,38
1
High Strength SDRAM Select ( 1=Normal, 0= Enhanced by 25% )
Bit 5
46
1
Enhanced CPUT1 Drive Select ( 1=Normal, 0=Enhanced by 25% )
Bit 4
43,44
1
Enhanced CPUT0, CPUC0 Drive Select
(1=Normal, 0=Enhanced by 25%)
Bit 3
40
1
SDRAM12 ( Active/Inactive )
Bit 2
-
1
Reserved
Bit 1
43,44
1
CPUT0, CPUC0 ( Active/Inactive )
Bit 0
46
1
CPUT1 ( Active/Inactive )
3. BYTE 2: PCI Clock Register (1=Enable, 0=Disable)
Bit
Pin#
Default
Description
Bit 7
-
1
Reserved
Bit 6
7
1
PCI5 ( Active/Inactive )
Bit 5
-
1
Reserved
Bit 4
13
1
PCI4 ( Active/Inactive )
Bit 3
12
1
PCI3 ( Active/Inactive )
Bit 2
11
1
PCI2 ( Active/Inactive )
Bit 1
10
1
PCI1 ( Active/Inactive )
Bit 0
8
1
PCI0 ( Active/Inactive )
4. BYTE 3: SDRAM Clock Register (1=Enable, 0=Disable)
Bit
Pin#
Default
Description
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