Preliminary
PLL205-54
Programmable Clock Generator for VIA KT-266 Chipset
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 12/04/00 Page 1
FEATURES
Generates all clock frequencies for VIA KT266
chipset.
Support one pair of differential CPU clocks, one
pair of differential push-pull CPU clocks, 3 AGP
and 10 PCI.
Enhanced PCI Output Drive selectable by I2C.
One 48MHz clock and 24_48MHz clock via I2C.
Three 14.318MHz reference clocks.
Program 5-bit CPU VID (Voltage Identification)
through I2C.
Power management control to stop CPU, PCI,
REF, 24_48MHz, 48MHz and AGP clocks.
Supports 2-wire I2C serial bus interface with
readback.
Single byte micro-step linear Frequency
Programming via I2C with glitch free smooth
switching.
Built-in programmable watchdog timer.
Spread Spectrum
0.25% center,
0.5% center,
0.75% center, and 0 to -0.5% downspread.
50% duty cycle with low jitter.
Available in 300 mil 48 Pin SSOP.
BLOCK DIAGRAM
PIN CONFIGURATION
Note: ^: Pull up v: Pull down #: Active low
*
: Bi-directional up latched at power-up
POWER GROUP
VDD1: REF(0:1), REF_F, XIN, XOUT
VDD2: 48MHz or 24_48MHz
VDD3: PCI(0:8), PCI9_E
VDD4: AGP(0:2)
VDD5: I2C, VID
VDDL1: CPUT0, CPUC0, CPUT_CS, CPUC_CS
VDDL2: PLL Core
KEY SPECIFICATIONS
CPU Cycle to Cycle jitter: 250ps.
PCI Cycle to Cycle jitter: 500ps.
PCI to PCI skew: 500ps.
CPU to CPU skew: 175ps.
AGP to AGP skew: 250ps.
48MHz
24_48MHz
PD
XIN
XOUT
FS (0:4)*
XTAL
OSC
PLL1
SST
Control
Logic
VDD1
REF(0:1)
VDD4
AGP (0:2)
PCI (0:8)
PCI9_E
VDD3
VDD2
PLL2
2
REF_F
CPUT0
CPUC0
CPUT_CS
CPUC_CS
VDDL1
SDATA
SCLK
Registers
VID (0:4)
PLL205-54
PCI7
GND
PCI6
PCI5
PCI4
VDD3
PCI3
GND
PCI1
PCI_F
GND
24_48Mhz/FS4*
v
VDD2
XOUT
XIN
GND
VDD1
VDD5
VIDENB^
SEL24_48#^
VDD3
PCI8/FS2*^
PCI0
CPUC0
VDDL1
CPUT_CS
CPUC_CS
GND
CPU_STOP#^
PCI_STOP/WDRESET#
PD#
VDDL2
GND
SDATA
REF0/FS0*^
REF1/FS1*^
REF_F
REF_STOP#^
AGP_STOP#^
GND
CPUT0
SCLK
AGP1
GND
AGP2
AGP0
VID3^
VID4^
GND
VDD4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
49
50
52
51
53
54
55
56
PCI2
48MHz/FS3*^
PCI9_E/SELPCI9_E#
VID0^
VID1^
VID2^
Preliminary
PLL205-54
Programmable Clock Generator for VIA KT-266 Chipset
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 12/04/00 Page 2
PIN DESCRIPTIONS
Name
Number
Type
Description
VDD(1:5)
1,5,15,23,33,31
P
Power Supplies. (See Power Group on page1)
VDDL1
48
P
Power supply for CPUT0, CPUC0, CPUT_CS and CPUC_CS.
VDDL2
41
P
Power supply for PLL CORE.
GND
2,8,12,19,32,
37,40,45,51
P
Ground.
XIN
3
I
14.318MHz crystal input to be connected to one end of the crystal.
XOUT
4
O
14.318MHz crystal output.
PD#
42
I
PD is Asynchronous active low input used to power down the device
into a low power state. The internal clocks are disabled and the VCO
and the crystal are stopped.
PCI_STOP/
WDRESET#
43
B
When input is Low, it will stop PCI(0:8) and PCI9_E. The enable of the
watchdog timer masks the PCI_STOP action.
CPU_STOP
44
I
When input is Low, it will disable CPUT_CS and CPUC_CS.
AGP_STOP
52
I
When input is Low, it will stop AGP(0:2).
REF_STOP
53
I
When input is Low, it will disable REF(0:1), 24_48MHz and 48MHz
except REF_F output.
PCI(0:8)
10,11,13,14,
16,17,18,20,21
O
PCI clocks with frequencies defined by Frequency Table. These pins
will be LOW when PCI_STOP is LOW.
PCI9_E/SELPCI9_E
22
B
At power up, this pin is an input pin and will determine the operating
frequency of PCI9_E output. After input sampling, this pin will generate
PCI output clock. If SELPCI9_E=1, PCI9_E will arrive 2 ns earlier than
other PCI clocks, if SELPCI9_E=0, PCI9_E will be normal PCI output
like other PCI clock outputs.
PCI_F, REF_F
9,54
O
Free running PCI and REF clocks.
CPUT0
50
O
"True" clock of differential pair open drain CPU outputs.
CPUC0
49
O
"Complementary" clock of differential pair open drain CPU outputs.
CPUT_CS,
CPUC_CS
47,46
O
Differential CPU clock outputs for the chipset. They are push-pull
outputs. These outputs will be disabled when CPU_STOP is low.
AGP(0:2)
34,35,36
O
AGP clocks outputs defined as 2x PCI.
SDATA
39
B
SCLK
38
I
Serial data input for serial interface port.
REF0/FS0*
REF1/FS1*
PCI8/FS2*
48MHz/FS3*
24_48MHz/FS4*
56,55,21,6,7
B
At power up, these pins are input pins. After input sampling, these pins
will generate output clocks. FS(0:3) have internal pull-up resistor while
FS4 has internal pull-down resistor.
VIDENB
25
I
When input is Low, it will disable the output of VID(0:4) which allows
CPU VID data directly sent to PWM. When High, it enables the override
of the CPU VID data by writing Byte5 of I2C register. This pin has 120K
internal pull up.
VID(0:4)
26,27,28,29,30
O
CPU voltage ID ouput
SEL24_48#
24
I
This pin will select 24MHz (when High) or 48MHz (when Low) for pin7.
Preliminary
PLL205-54
Programmable Clock Generator for VIA KT-266 Chipset
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 12/04/00 Page 3
POWER MANAGEMENT
CPU_STOP
PCI_STOP
CPUT0
CPUC0
PCI
PCI_F
XTAL,VCO
1
1
Running
Running
Running
Running
Running
0
1
Stopped Low
Stopped Low
Running
Running
Running
1
0
Running
Running
Stopped Low
Running
Running
FREQUENCY (MHz) SELECTION TABLE
FS4
FS3
FS2
FS1
FS0
CPU
AGP
PCI
Spread
Spectrum
0
0
0
0
0
90.00
60.00
30.00
0.25%
0
0
0
0
1
100.00
66.67
33.33
0.25%
0
0
0
1
0
101.00
67.33
33.67
0.25%
0
0
0
1
1
102.00
68.00
34.00
0.25%
0
0
1
0
0
103.00
68.67
34.33
0.25%
0
0
1
0
1
105.00
70.00
35.00
0.25%
0
0
1
1
0
107.00
71.33
35.67
0.25%
0
0
1
1
1
110.00
73.33
36.67
0.25%
0
1
0
0
0
113.00
75.33
37.67
0.25%
0
1
0
0
1
115.00
76.67
38.33
0.25%
0
1
0
1
0
117.00
78.00
39.00
0.25%
0
1
0
1
1
120.00
80.00
40.00
0.25%
0
1
1
0
0
120.00
60.00
30.00
0.25%
0
1
1
0
1
125.00
62.50
31.25
0.25%
0
1
1
1
0
133.33
66.67
33.33
0.25%
0
1
1
1
1
135.00
67.50
33.75
0.25%
1
0
0
0
0
100.00
66.67
33.33
0 to -0.5%
1
0
0
0
1
100.00
66.67
33.33
0.5%
1
0
0
1
0
100.00
66.67
33.33
0.75%
1
0
0
1
1
136.00
68.00
34.00
0.25%
1
0
1
0
0
138.00
69.00
34.50
0.25%
1
0
1
0
1
140.00
70.00
35.00
0.25%
1
0
1
1
0
142.00
71.00
35.50
0.25%
1
0
1
1
1
145.00
72.50
36.25
0.25%
1
1
0
0
0
150.00
75.00
37.50
0.25%
1
1
0
0
1
155.00
77.50
38.75
0.25%
1
1
0
1
0
166.00
66.40
33.20
0.25%
1
1
0
1
1
180.00
72.00
36.00
0.25%
1
1
1
0
0
200.00
80.00
40.00
0.25%
1
1
1
0
1
133.33
66.67
33.33
0 to -0.5%
1
1
1
1
0
133.33
66.67
33.33
0.5%
1
1
1
1
1
133.33
66.67
33.33
0.75%
Preliminary
PLL205-54
Programmable Clock Generator for VIA KT-266 Chipset
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 12/04/00 Page 4
FREQUENCY (MHz) SELECTION TABLE BY GROUP TIMING
Divider Ratio
(CPU:AGP)
FS4
FS3
FS2
FS1
FS0
CPU
AGP
PCI
Spread
Spectrum
0
0
0
0
0
90.00
60.00
30.00
0.25%
0
0
0
0
1
100.00
66.67
33.33
0.25%
1
0
0
0
0
100.00
66.67
33.33
0 to -0.5%
1
0
0
0
1
100.00
66.67
33.33
0.5%
1
0
0
1
0
100.00
66.67
33.33
0.75%
0
0
0
1
0
101.00
67.33
33.67
0.25%
0
0
0
1
1
102.00
68.00
34.00
0.25%
0
0
1
0
0
103.00
68.67
34.33
0.25%
0
0
1
0
1
105.00
70.00
35.00
0.25%
0
0
1
1
0
107.00
71.33
35.67
0.25%
0
0
1
1
1
110.00
73.33
36.67
0.25%
0
1
0
0
0
113.00
75.33
37.67
0.25%
0
1
0
0
1
115.00
76.67
38.33
0.25%
0
1
0
1
0
117.00
78.00
39.00
0.25%
A ( 1.5 : 1 )
0
1
0
1
1
120.00
80.00
40.00
0.25%
0
1
1
0
0
120.00
60.00
30.00
0.25%
0
1
1
0
1
125.00
62.50
31.25
0.25%
0
1
1
1
0
133.33
66.67
33.33
0.25%
1
1
1
0
1
133.33
66.67
33.33
0 to -0.5%
1
1
1
1
0
133.33
66.67
33.33
0.5%
1
1
1
1
1
133.33
66.67
33.33
0.75%
0
1
1
1
1
135.00
67.50
33.75
0.25%
1
0
0
1
1
136.00
68.00
34.00
0.25%
1
0
1
0
0
138.00
69.00
34.50
0.25%
1
0
1
0
1
140.00
70.00
35.00
0.25%
1
0
1
1
0
142.00
71.00
35.50
0.25%
1
0
1
1
1
145.00
72.50
36.25
0.25%
1
1
0
0
0
150.00
75.00
37.50
0.25%
B ( 2 : 1 )
1
1
0
0
1
155.00
77.50
38.75
0.25%
1
1
0
1
0
166.00
66.40
33.20
0.25%
1
1
0
1
1
180.00
72.00
36.00
0.25%
C ( 2.5 : 1 )
1
1
1
0
0
200.00
80.00
40.00
0.25%
Preliminary
PLL205-54
Programmable Clock Generator for VIA KT-266 Chipset
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 12/04/00 Page 5
I2C BUS CONFIGURATION SETTING
Address Assignment
A6 A5 A4 A3 A2 A1 A0 R/W
1 1 0 1 0 0 1 _
Slave
Receiver/Transmitter
Provides both slave write and readback functionality
Data Transfer Rate
Standard mode at 100kbits/s
Serial Bits Reading
The serial bits will be read or sent by the clock driver in the following order
Byte 0 Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 Bits 7, 6, 5, 4, 3, 2, 1, 0
-
Byte N Bits 7, 6, 5, 4, 3, 2, 1, 0
Data Protocol
This serial protocol is designed to allow both blocks write and read from the controller. The
bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred
must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will
terminate the transfer. The write or read block both begins with the master sending a slave
address and a write condition (0xD2) or a read condition (0xD3).
Following the acknowledge of this address byte, in
Write Mode: the Command Byte and Byte
Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte
Count Byte will be read by the master then all other Data Byte.
I2C CONTROL REGISTERS
1. BYTE 0: Functional and Frequency Select Clock Register (1=Enable, 0=Disable)
Bit
Pin#
Default
Description
Bit 7
6
0
FS3 ( see Frequency selection Table )
Bit 6
21
0
FS2 ( see Frequency selection Table )
Bit 5
55
0
FS1 ( see Frequency selection Table )
Bit 4
56
0
FS0 ( see Frequency selection Table )
Bit 3
-
0
Frequency selection control bit 1=Via I2C, 0=Via External jumper
Bit 2
7
0
FS4 ( see Frequency selection Table )
Bit 1
-
1
0 = OFF, 1 = Spread Spectrum Enable
Bit 0
-
0
0 = Normal, 1 = Tristate Mode for all outputs
PDF 
ZIP