PRELIMINARY
PLL208-101
Programmable Clock Generator for AMD K8
TM
and
VIA
K8
TM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/15/02 Page 1
48Mhz
24_48Mhz
XIN
XOUT
SDATA
SCLK
XTAL
OSC
I2C
Logic
PLL1
SST
Control
Logic
REF (0:2)
VDDCPU (3.3V)
CPUT (0:1)
PCI (0:8)
PCI_F
PLL2
2
Watch
Dog
WDRESET#
CPUC (0:1)
VDD
VDD
PCI_STOP#
FS(0:3)
VDD
FEATURES
Selectable Spread Spectrum Modulation
between
0.3% and -0.5%.
AccuSkew
TM
Programmable Precision skew
tuning channel with maximum 5% precision
over the variation of temperature, process and
voltage with step size as small as 80ps.
AccuDrive
TM
Programmable Output Buffer drive
strength with 6mA step size.
Programmable VCO frequency with one variable
Programmable Output Divider for CPU, HTT and
PCI clock.
2 - Differential pair push-pull CPUCLK.
9 - PCI (including 1 free running) with I
2
C
selectable doubled driving strength on PCI.
4 - Selectable PCI /HTT clock.
1 - 48MHZ for USB @3.3V fixed.
3 - REF 14.318MHz clock outputs.
1 - programmable 24MHz or 48MHz for SIO.
I
2
C serial interface for programmability features.
Built-in programmable watchdog timer
Available in 300 mil 48 pin SSOP.
BLOCK DIAGRAM
PIN CONFIGURATION
Note: ^ : Internal Pull Up (120k
),
v
: Internal Pull down (120k
),
* : Bi-directional latched at power-up
~ : This Output has 2X Drive Strength.
**** : This Output has 2.3X Drive Strength. # : Active low.
POWER GROUP
VDDREF (3.3V), VSSREF: REF, XIN, XOUT
VDDPCI (3.3V), VSSPCI: PCI
VDD48M (3.3V), VSS48M: 48MHz, 24_48MHz
VDDCPU (3.3V), VSSCPU: CPUT/C_[0:1]
VDDA (3.3V), VSSA: PLL Analog
VDDHTT (3.3V), VSSHTT: HTTT/C[0:1]
KEY SPECIFICATIONS
CPU - CPU Output Skew < 150ps.
PCI - PCI Output Skew <500ps
CPU (early) to PCI Skew: 1 to 4 ns (Typ 2ns).
CPU TO HTT Skew < 150ps.
PLL208-101
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
41
42
44
43
45
46
47
48
VDDPCI
PCICLK5
****PCICLK3
****PCICLK2
VSSPCI
PCICLK0
VDDREF
GND
VDDPCI
PCICLK11
PCICLK1
VDDPCI
~PCI_F/ModeC^
~(PCICLK6)PCI_STOP#^
FS0/REF0*^
^PCICLK8/HTTCLK1/ModeB
PCICLK9/HTTCLK2
VSSPCI
~PCICLK10/HTTCLK3
VSSPCI
PCICLK4
^(PCICLK7/HTTCLK0)ModeA
CPUT_0
CPUC_0
VDDREF
VDDCPU
CPUT_1
CPUC_1
REF2/FS2*^
VSSREF
VDD
48MHz/FS3*
v
SCLK
SDATA
REF1/FS1*^
WDRESET#
VDDA
VSSCPU
VDDCPU
VSSCPU
VSS
VSS48M
VDD48M
24_48MHz / Sel24_48#~^
VSS48M
VSSA
X1
X2
PRELIMINARY
PLL208-101
Programmable Clock Generator for AMD K8
TM
and
VIA
K8
TM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/15/02 Page 2
Pin Descriptions
Name Number
Type
Description
REF[0:2]/FS[0:2]
1,45,48
I/O
14.318MHz reference clock output. This pin latch FS[0:2] value at power-
up.(See Frequency Selection table).
XIN
3
IN
14.318MHz crystal input to be connected to one end of the crystal.
XOUT
4
OUT 14.318Mhz crystal output
(PC1CLK7/HTTCLK0)
ModeA
6
I/O
PCI clock output / Hyper Transport output / Mode selection pin, this input
is activated by the ModeB selection pin.
(PCICLK8/HTTCLK1)
ModeB
7
I/O
PCI clock output / Hyper Transport output / Mode selection latch input pin.
PCICLK9/HTTCLK2
8
OUT PCI Clock output / Hyper Transport output.
~PCICLK10/HTTCLK3 11
OUT
PCI Clock output / Hyper Transport output.
PCICLK11 12
OUT
PCI Clock output.
PCICLK0 13
OUT
PCI Clock output.
PCICLK1 14
OUT
PCI Clock output.
****PCICLK2 17
I/O
3.3V LVTTL input for selection the current multiplier for CPU outputs /
3.3V PCI clock output.
****PCICLK3 18
I/O
Early/Normal PCI clock output latched at power up.
PCICLK4 21
OUT
PCI Clock output.
PCICLK5 22
OUT
PCI Clock output.
~^PCI_F/ModeC 23
I/O
Free running PCI clock not affected by PCI_STOP# / Mode selection latch
input pin.
~^(PCICLK6)PCI_STOP# 24 I/O
PCI Clock output, this output is activated by the Mode selection pin /
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when
input low.
SCLK
25
IN
Serial data inputs for serial interface port.
SDATA
26
I/O
Serial data inputs for serial interface port.
24_48MHz/ Sel24_48#~^
28
I/O
24MHz clock output / Latched select input for 24/48MHz output.
0 = 48MHz
1 = 24MHz
48MHz/FS3*
31
I/O
Frequency select latch input pin / Fixed 48MHz clock output.
CPU[C/T]_1
36,37
OUT Differential push-pull K8 pair output.
CPU[C/T]_0
40,41
OUT Differential push-pull
K8 pair output.
WDRESET#
44
OUT Real time system reset signal for frequency gear ratio change or watchdog
timer timeout. This signal is active low.
VDDPCI
9,16,19
PWR 3.3V Power Supply for PCI clock
VDD48M
29
PWR 3.3V Power Supply for 24/48MHz clock outputs.
VDDA
43
PWR 3.3V power for internal PLL.
PRELIMINARY
PLL208-101
Programmable Clock Generator for AMD K8
TM
and
VIA
K8
TM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/15/02 Page 3
VDDCPU
35,38
PWR 3.3V power supply for CPU clocks.
VDDREF
2,46
PWR 3.3V power supply for REF clocks
VDD
32
PWR 3.3V power supply
VSS 5,10,15,
20,27,30,
33,34,39,
42,47
PWR Ground.
Mode Functionality Tables
ModeA ModeB
Pin6
Pin7
Pin8
Pin11
0 0
HTTCLK0
HTTCLK1
HTTCLK2
PCICLK10
0 1
ModeA
(Input only)
HTTCLK1 HTTCLK2 HTTCLK3
1 0 PCICLK7
PCICLK8
PCICLK9
PCICLK10
1 1 ModeA
(Input only)
PCICLK8 PCICLK9 PCICLK10
ModeC Pin24
0 PCICLK6
1 PCI_STOP#
PRELIMINARY
PLL208-101
Programmable Clock Generator for AMD K8
TM
and
VIA
K8
TM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/15/02 Page 4
FREQUENCY (MHz) SELECTION TABLE
Bit4 Bit3 Bit2 Bit1
Bit5
FS3 FS2 FS1 FS0
CPU HTT PCI SST
Amp
VCO
0 0 0 0 0 100.90 67.27 33.63 0.3%
center
403.60
0 0 0 0 1 133.90 66.95 33.48 0.3%
center
535.60
0 0 0 1 0 168.00 67.20 33.60 0.3%
center
672.00
0 0 0 1 1 202.00 67.33 33.67 0.3%
center
404.00
0 0 1 0 0 100.20 66.80 33.40 0.3%
center
400.80
0 0 1 0 1 133.50 66.75 33.38 0.3%
center
534.00
0 0 1 1 0 166.70 66.68 33.34 0.3%
center
666.80
0 0 1 1 1 200.40 66.80 33.40 -0.5%
down
400.80
0 1 0 0 0 270.00 67.50 33.75 0.3%
center
540.00
0 1 0 0 1 233.33 66.67 33.33 -0.5%
down
466.66
0 1 0 1 0 266.67 66.67 33.33 0.3%
center
533.34
0 1 0 1 1 300.00 75.00 37.50 0.3%
center
600.00
0 1 1 0 0 150.00 60.00 30.00 0.3%
center
600.00
0 1 1 0 1 180.00 60.00 30.00 0.3%
center
360.00
0 1 1 1 0 210.00 70.00 35.00 0.3%
center
420.00
0 1 1 1 1 240.00 60.00 30.00 0.3%
center
480.00
1 0 0 0 0 100.00 66.67 33.33 -0.5%
down
400.00
1 0 0 0 1 133.33 66.67 33.33 -0.5%
down
533.32
1 0 0 1 0 166.66 66.66 33.33 -0.5%
down
666.64
1 0 0 1 1 200.00 66.67 33.33 -0.5%
down
400.00
1 0 1 0 0 103.00 68.67 34.33 0.3%
center
412.00
1 0 1 0 1 137.33 38.66 34.33 -0.5%
down
549.32
1 0 1 1 0 171.66 68.66 34.33 0.3%
center
686.64
1 0 1 1 1 206.00 68.67 34.33 0.3%
center
412.00
1 1 0 0 0 278.10 69.53 34.76 0.3%
center
556.20
1 1 0 0 1 240.33 68.67 34.33 0.3%
center
480.66
1 1 0 1 0 274.67 68.67 34.33 0.3%
center
549.34
1 1 0 1 1 309.00 77.25 38.63 0.3%
center
618.00
1 1 1 0 0 154.50 61.80 30.90 0.3%
center
618.00
1 1 1 0 1 185.40 61.80 30.90 0.3%
center
370.80
1 1 1 1 0 216.30 72.10 36.05 0.3%
center
432.60
1 1 1 1 1 247.20 61.80 30.90 0.3%
center
494.40
PRELIMINARY
PLL208-101
Programmable Clock Generator for AMD K8
TM
and
VIA
K8
TM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/15/02 Page 5
I2C BUS CONFIGURATION SETTING
Address Assignment
A6 A5 A4 A3 A2 A1 A0 R/W
1 1 0 1 0 0 1 _
Slave
Receiver/Transmitter
Provides both slave write and read back functionality
Data Transfer Rate
Standard mode at 100kbits/s
Data Protocol
This serial interface is designed to allow multiple protocols to write and read from the
controller. It includes Block Read/Write, Block Index Read/Write, Byte Read/Write and Word
Read/Write. In general, the bytes must be accessed in sequential order from lowest to highest
byte. Each byte transferred must be followed by 1 acknowledge bit. A byte transferred without
acknowledged bit will terminate the transfer. The write or read block both begins with the
master sending a slave address and a write condition (0xD2) or a read condition (0xD3).
WRITE MODE
Block
Write
S
Address
D2
A
Command
00
A
A
A
A
A
A P
Block
Index Write
S
Address
D2
A
Command M
=(00~22)
A
A
A
A
A
A P
Byte Write
S
Address
D2
A
Command M'
=(00~22)+128
A
A P
Word Write S
Address
D2
A
Command M'
=(00~22)+128
A
A
A P
READ MODE
Block
Read
S
Address
D2
A
Command
00
A S
A
A
A
A
A
Data
Byte N
A P
Block
Index Read
S
Address
D2
A
Command M
=(00~22)
A S
A
A
A
A
A
Data
Byte M+N-1
A P
Byte Read
S
Address
D2
A
Command M'
=(00~22)+128
A S
A
A P
Word Read S
Address
D2
A
Command M'
=(00~22)+128
A S
A
A
A P
Legend:
S Start
A
P Stop
Data
Byte M
Address
D3
Byte count
N
Data
--------
Data
Byte M+1
Data
Byte M
Data
Byte N
Byte count
N
Data
Byte M
Data
Byte M+1
Data
--------
Data
Byte M+N-1
Data
Byte 2
Data
--------
Byte count
N
Data
Byte 1
Address
D3
Byte count
N
Data
Byte 1
Data
Byte 2
Data
Byte M+1
Data
--------
Address
D3
Data
Byte M
Data
Byte M
Acknowledge to
host
Address
D3
Data
Byte M
Data
Byte M+1
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